Lines Matching +full:num +full:- +full:ss +full:- +full:bits
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rk3576-power.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
52 xin32k: clock-xin32k {
53 compatible = "fixed-clock";
54 clock-frequency = <32768>;
55 clock-output-names = "xin32k";
56 #clock-cells = <0>;
59 xin24m: clock-xin24m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <24000000>;
63 clock-output-names = "xin24m";
66 spll: clock-spll {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <702000000>;
70 clock-output-names = "spll";
74 #address-cells = <1>;
75 #size-cells = <0>;
77 cpu-map {
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
113 capacity-dmips-mhz = <485>;
115 operating-points-v2 = <&cluster0_opp_table>;
116 #cooling-cells = <2>;
117 dynamic-power-coefficient = <120>;
118 cpu-idle-states = <&CPU_SLEEP>;
123 compatible = "arm,cortex-a53";
125 enable-method = "psci";
126 capacity-dmips-mhz = <485>;
128 operating-points-v2 = <&cluster0_opp_table>;
129 cpu-idle-states = <&CPU_SLEEP>;
134 compatible = "arm,cortex-a53";
136 enable-method = "psci";
137 capacity-dmips-mhz = <485>;
139 operating-points-v2 = <&cluster0_opp_table>;
140 cpu-idle-states = <&CPU_SLEEP>;
145 compatible = "arm,cortex-a53";
147 enable-method = "psci";
148 capacity-dmips-mhz = <485>;
150 operating-points-v2 = <&cluster0_opp_table>;
151 cpu-idle-states = <&CPU_SLEEP>;
156 compatible = "arm,cortex-a72";
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
161 operating-points-v2 = <&cluster1_opp_table>;
162 #cooling-cells = <2>;
163 dynamic-power-coefficient = <320>;
164 cpu-idle-states = <&CPU_SLEEP>;
169 compatible = "arm,cortex-a72";
171 enable-method = "psci";
172 capacity-dmips-mhz = <1024>;
174 operating-points-v2 = <&cluster1_opp_table>;
175 cpu-idle-states = <&CPU_SLEEP>;
180 compatible = "arm,cortex-a72";
182 enable-method = "psci";
183 capacity-dmips-mhz = <1024>;
185 operating-points-v2 = <&cluster1_opp_table>;
186 cpu-idle-states = <&CPU_SLEEP>;
191 compatible = "arm,cortex-a72";
193 enable-method = "psci";
194 capacity-dmips-mhz = <1024>;
196 operating-points-v2 = <&cluster1_opp_table>;
197 cpu-idle-states = <&CPU_SLEEP>;
200 idle-states {
201 entry-method = "psci";
203 CPU_SLEEP: cpu-sleep {
204 compatible = "arm,idle-state";
205 arm,psci-suspend-param = <0x0010000>;
206 entry-latency-us = <120>;
207 exit-latency-us = <250>;
208 min-residency-us = <900>;
209 local-timer-stop;
214 cluster0_opp_table: opp-table-cluster0 {
215 compatible = "operating-points-v2";
216 opp-shared;
218 opp-408000000 {
219 opp-hz = /bits/ 64 <408000000>;
220 opp-microvolt = <700000 700000 950000>;
221 clock-latency-ns = <40000>;
224 opp-600000000 {
225 opp-hz = /bits/ 64 <600000000>;
226 opp-microvolt = <700000 700000 950000>;
227 clock-latency-ns = <40000>;
230 opp-816000000 {
231 opp-hz = /bits/ 64 <816000000>;
232 opp-microvolt = <700000 700000 950000>;
233 clock-latency-ns = <40000>;
236 opp-1008000000 {
237 opp-hz = /bits/ 64 <1008000000>;
238 opp-microvolt = <700000 700000 950000>;
239 clock-latency-ns = <40000>;
242 opp-1200000000 {
243 opp-hz = /bits/ 64 <1200000000>;
244 opp-microvolt = <700000 700000 950000>;
245 clock-latency-ns = <40000>;
248 opp-1416000000 {
249 opp-hz = /bits/ 64 <1416000000>;
250 opp-microvolt = <725000 725000 950000>;
251 clock-latency-ns = <40000>;
254 opp-1608000000 {
255 opp-hz = /bits/ 64 <1608000000>;
256 opp-microvolt = <750000 750000 950000>;
257 clock-latency-ns = <40000>;
260 opp-1800000000 {
261 opp-hz = /bits/ 64 <1800000000>;
262 opp-microvolt = <825000 825000 950000>;
263 clock-latency-ns = <40000>;
264 opp-suspend;
267 opp-2016000000 {
268 opp-hz = /bits/ 64 <2016000000>;
269 opp-microvolt = <900000 900000 950000>;
270 clock-latency-ns = <40000>;
273 opp-2208000000 {
274 opp-hz = /bits/ 64 <2208000000>;
275 opp-microvolt = <950000 950000 950000>;
276 clock-latency-ns = <40000>;
280 cluster1_opp_table: opp-table-cluster1 {
281 compatible = "operating-points-v2";
282 opp-shared;
284 opp-408000000 {
285 opp-hz = /bits/ 64 <408000000>;
286 opp-microvolt = <700000 700000 950000>;
287 clock-latency-ns = <40000>;
288 opp-suspend;
291 opp-600000000 {
292 opp-hz = /bits/ 64 <600000000>;
293 opp-microvolt = <700000 700000 950000>;
294 clock-latency-ns = <40000>;
297 opp-816000000 {
298 opp-hz = /bits/ 64 <816000000>;
299 opp-microvolt = <700000 700000 950000>;
300 clock-latency-ns = <40000>;
303 opp-1008000000 {
304 opp-hz = /bits/ 64 <1008000000>;
305 opp-microvolt = <700000 700000 950000>;
306 clock-latency-ns = <40000>;
309 opp-1200000000 {
310 opp-hz = /bits/ 64 <1200000000>;
311 opp-microvolt = <700000 700000 950000>;
312 clock-latency-ns = <40000>;
315 opp-1416000000 {
316 opp-hz = /bits/ 64 <1416000000>;
317 opp-microvolt = <712500 712500 950000>;
318 clock-latency-ns = <40000>;
321 opp-1608000000 {
322 opp-hz = /bits/ 64 <1608000000>;
323 opp-microvolt = <737500 737500 950000>;
324 clock-latency-ns = <40000>;
327 opp-1800000000 {
328 opp-hz = /bits/ 64 <1800000000>;
329 opp-microvolt = <800000 800000 950000>;
330 clock-latency-ns = <40000>;
333 opp-2016000000 {
334 opp-hz = /bits/ 64 <2016000000>;
335 opp-microvolt = <862500 862500 950000>;
336 clock-latency-ns = <40000>;
339 opp-2208000000 {
340 opp-hz = /bits/ 64 <2208000000>;
341 opp-microvolt = <925000 925000 950000>;
342 clock-latency-ns = <40000>;
345 opp-2304000000 {
346 opp-hz = /bits/ 64 <2304000000>;
347 opp-microvolt = <950000 950000 950000>;
348 clock-latency-ns = <40000>;
352 gpu_opp_table: opp-table-gpu {
353 compatible = "operating-points-v2";
355 opp-300000000 {
356 opp-hz = /bits/ 64 <300000000>;
357 opp-microvolt = <700000 700000 850000>;
360 opp-400000000 {
361 opp-hz = /bits/ 64 <400000000>;
362 opp-microvolt = <700000 700000 850000>;
365 opp-500000000 {
366 opp-hz = /bits/ 64 <500000000>;
367 opp-microvolt = <700000 700000 850000>;
370 opp-600000000 {
371 opp-hz = /bits/ 64 <600000000>;
372 opp-microvolt = <700000 700000 850000>;
375 opp-700000000 {
376 opp-hz = /bits/ 64 <700000000>;
377 opp-microvolt = <725000 725000 850000>;
380 opp-800000000 {
381 opp-hz = /bits/ 64 <800000000>;
382 opp-microvolt = <775000 775000 850000>;
385 opp-900000000 {
386 opp-hz = /bits/ 64 <900000000>;
387 opp-microvolt = <825000 825000 850000>;
390 opp-950000000 {
391 opp-hz = /bits/ 64 <950000000>;
392 opp-microvolt = <850000 850000 850000>;
398 compatible = "arm,scmi-smc";
399 arm,smc-id = <0x82000010>;
401 #address-cells = <1>;
402 #size-cells = <0>;
406 #clock-cells = <1>;
411 pmu_a53: pmu-a53 {
412 compatible = "arm,cortex-a53-pmu";
417 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>;
420 pmu_a72: pmu-a72 {
421 compatible = "arm,cortex-a72-pmu";
426 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
430 compatible = "arm,psci-1.0";
435 compatible = "arm,armv8-timer";
443 compatible = "simple-bus";
444 #address-cells = <2>;
445 #size-cells = <2>;
449 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
454 clock-names = "ref_clk", "suspend_clk", "bus_clk";
456 power-domains = <&power RK3576_PD_USB>;
460 phy-names = "usb2-phy", "usb3-phy";
463 snps,dis-u1-entry-quirk;
464 snps,dis-u2-entry-quirk;
465 snps,dis-u2-freeclk-exists-quirk;
466 snps,dis-del-phy-power-chg-quirk;
467 snps,dis-tx-ipgap-linecheck-quirk;
468 snps,parkmode-disable-hs-quirk;
469 snps,parkmode-disable-ss-quirk;
474 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
479 clock-names = "ref_clk", "suspend_clk", "bus_clk";
481 power-domains = <&power RK3576_PD_PHP>;
485 phy-names = "usb2-phy", "usb3-phy";
488 snps,dis-u1-entry-quirk;
489 snps,dis-u2-entry-quirk;
490 snps,dis-u2-freeclk-exists-quirk;
491 snps,dis-del-phy-power-chg-quirk;
492 snps,dis-tx-ipgap-linecheck-quirk;
494 snps,parkmode-disable-hs-quirk;
495 snps,parkmode-disable-ss-quirk;
496 dma-coherent;
501 compatible = "rockchip,rk3576-sys-grf", "syscon";
506 compatible = "rockchip,rk3576-bigcore-grf", "syscon";
511 compatible = "rockchip,rk3576-litcore-grf", "syscon";
516 compatible = "rockchip,rk3576-cci-grf", "syscon";
521 compatible = "rockchip,rk3576-gpu-grf", "syscon";
526 compatible = "rockchip,rk3576-npu-grf", "syscon";
531 compatible = "rockchip,rk3576-vo0-grf", "syscon";
536 compatible = "rockchip,rk3576-usb-grf", "syscon";
541 compatible = "rockchip,rk3576-php-grf", "syscon";
546 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd";
551 compatible = "rockchip,rk3576-pmu1-grf", "syscon";
556 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
561 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
566 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon";
571 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
573 #address-cells = <1>;
574 #size-cells = <1>;
576 u2phy0: usb2-phy@0 {
577 compatible = "rockchip,rk3576-usb2phy";
580 reset-names = "phy", "apb";
584 clock-names = "phyclk", "aclk", "aclk_slv";
585 clock-output-names = "usb480m_phy0";
586 #clock-cells = <0>;
589 u2phy0_otg: otg-port {
590 #phy-cells = <0>;
594 interrupt-names = "otg-bvalid", "otg-id", "linestate";
599 u2phy1: usb2-phy@2000 {
600 compatible = "rockchip,rk3576-usb2phy";
603 reset-names = "phy", "apb";
607 clock-names = "phyclk", "aclk", "aclk_slv";
608 clock-output-names = "usb480m_phy1";
609 #clock-cells = <0>;
612 u2phy1_otg: otg-port {
613 #phy-cells = <0>;
617 interrupt-names = "otg-bvalid", "otg-id", "linestate";
624 compatible = "rockchip,rk3576-vo1-grf", "syscon";
630 compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
635 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
639 cru: clock-controller@27200000 {
640 compatible = "rockchip,rk3576-cru";
642 #clock-cells = <1>;
643 #reset-cells = <1>;
645 assigned-clocks =
654 assigned-clock-parents = <&cru PLL_AUPLL>;
655 assigned-clock-rates =
667 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
670 clock-names = "i2c", "pclk";
672 pinctrl-names = "default";
673 pinctrl-0 = <&i2c0m0_xfer>;
674 #address-cells = <1>;
675 #size-cells = <0>;
680 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
682 reg-shift = <2>;
683 reg-io-width = <4>;
685 clock-names = "baudclk", "apb_pclk";
688 pinctrl-names = "default";
689 pinctrl-0 = <&uart1m0_xfer>;
693 pmu: power-management@27380000 {
694 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
697 power: power-controller {
698 compatible = "rockchip,rk3576-power-controller";
699 #power-domain-cells = <1>;
700 #address-cells = <1>;
701 #size-cells = <0>;
703 power-domain@RK3576_PD_NPU {
705 #power-domain-cells = <1>;
706 #address-cells = <1>;
707 #size-cells = <0>;
709 power-domain@RK3576_PD_NPUTOP {
724 #power-domain-cells = <1>;
725 #address-cells = <1>;
726 #size-cells = <0>;
728 power-domain@RK3576_PD_NPU0 {
733 #power-domain-cells = <0>;
735 power-domain@RK3576_PD_NPU1 {
740 #power-domain-cells = <0>;
745 power-domain@RK3576_PD_GPU {
749 #power-domain-cells = <0>;
752 power-domain@RK3576_PD_NVM {
757 #power-domain-cells = <1>;
758 #address-cells = <1>;
759 #size-cells = <0>;
761 power-domain@RK3576_PD_SDGMAC {
778 #power-domain-cells = <0>;
782 power-domain@RK3576_PD_PHP {
790 #power-domain-cells = <1>;
791 #address-cells = <1>;
792 #size-cells = <0>;
794 power-domain@RK3576_PD_SUBPHP {
796 #power-domain-cells = <0>;
800 power-domain@RK3576_PD_AUDIO {
802 #power-domain-cells = <0>;
805 power-domain@RK3576_PD_VEPU1 {
810 #power-domain-cells = <0>;
813 power-domain@RK3576_PD_VPU {
830 #power-domain-cells = <0>;
833 power-domain@RK3576_PD_VDEC {
838 #power-domain-cells = <0>;
841 power-domain@RK3576_PD_VI {
860 #power-domain-cells = <1>;
861 #address-cells = <1>;
862 #size-cells = <0>;
864 power-domain@RK3576_PD_VEPU0 {
869 #power-domain-cells = <0>;
873 power-domain@RK3576_PD_VOP {
881 #power-domain-cells = <1>;
882 #address-cells = <1>;
883 #size-cells = <0>;
885 power-domain@RK3576_PD_USB {
894 #power-domain-cells = <0>;
897 power-domain@RK3576_PD_VO0 {
905 #power-domain-cells = <0>;
908 power-domain@RK3576_PD_VO1 {
916 #power-domain-cells = <0>;
923 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
925 assigned-clocks = <&scmi_clk CLK_GPU>;
926 assigned-clock-rates = <198000000>;
928 clock-names = "core";
929 dynamic-power-coefficient = <1625>;
933 interrupt-names = "job", "mmu", "gpu";
934 operating-points-v2 = <&gpu_opp_table>;
935 power-domains = <&power RK3576_PD_GPU>;
936 #cooling-cells = <2>;
941 compatible = "rockchip,rk3576-qos", "syscon";
946 compatible = "rockchip,rk3576-qos", "syscon";
951 compatible = "rockchip,rk3576-qos", "syscon";
956 compatible = "rockchip,rk3576-qos", "syscon";
961 compatible = "rockchip,rk3576-qos", "syscon";
966 compatible = "rockchip,rk3576-qos", "syscon";
971 compatible = "rockchip,rk3576-qos", "syscon";
976 compatible = "rockchip,rk3576-qos", "syscon";
981 compatible = "rockchip,rk3576-qos", "syscon";
986 compatible = "rockchip,rk3576-qos", "syscon";
991 compatible = "rockchip,rk3576-qos", "syscon";
996 compatible = "rockchip,rk3576-qos", "syscon";
1001 compatible = "rockchip,rk3576-qos", "syscon";
1006 compatible = "rockchip,rk3576-qos", "syscon";
1011 compatible = "rockchip,rk3576-qos", "syscon";
1016 compatible = "rockchip,rk3576-qos", "syscon";
1021 compatible = "rockchip,rk3576-qos", "syscon";
1026 compatible = "rockchip,rk3576-qos", "syscon";
1031 compatible = "rockchip,rk3576-qos", "syscon";
1036 compatible = "rockchip,rk3576-qos", "syscon";
1041 compatible = "rockchip,rk3576-qos", "syscon";
1046 compatible = "rockchip,rk3576-qos", "syscon";
1051 compatible = "rockchip,rk3576-qos", "syscon";
1056 compatible = "rockchip,rk3576-qos", "syscon";
1061 compatible = "rockchip,rk3576-qos", "syscon";
1066 compatible = "rockchip,rk3576-qos", "syscon";
1071 compatible = "rockchip,rk3576-qos", "syscon";
1076 compatible = "rockchip,rk3576-qos", "syscon";
1081 compatible = "rockchip,rk3576-qos", "syscon";
1086 compatible = "rockchip,rk3576-qos", "syscon";
1091 compatible = "rockchip,rk3576-qos", "syscon";
1096 compatible = "rockchip,rk3576-qos", "syscon";
1101 compatible = "rockchip,rk3576-qos", "syscon";
1106 compatible = "rockchip,rk3576-qos", "syscon";
1111 compatible = "rockchip,rk3576-qos", "syscon";
1116 compatible = "rockchip,rk3576-qos", "syscon";
1121 compatible = "rockchip,rk3576-qos", "syscon";
1126 compatible = "rockchip,rk3576-qos", "syscon";
1131 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1136 clock-names = "stmmaceth", "clk_mac_ref",
1141 interrupt-names = "macirq", "eth_wake_irq";
1142 power-domains = <&power RK3576_PD_SDGMAC>;
1144 reset-names = "stmmaceth";
1146 rockchip,php-grf = <&ioc_grf>;
1147 snps,axi-config = <&gmac0_stmmac_axi_setup>;
1148 snps,mixed-burst;
1149 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
1150 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
1155 compatible = "snps,dwmac-mdio";
1156 #address-cells = <0x1>;
1157 #size-cells = <0x0>;
1160 gmac0_stmmac_axi_setup: stmmac-axi-config {
1166 gmac0_mtl_rx_setup: rx-queues-config {
1167 snps,rx-queues-to-use = <1>;
1171 gmac0_mtl_tx_setup: tx-queues-config {
1172 snps,tx-queues-to-use = <1>;
1178 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1183 clock-names = "stmmaceth", "clk_mac_ref",
1188 interrupt-names = "macirq", "eth_wake_irq";
1189 power-domains = <&power RK3576_PD_SDGMAC>;
1191 reset-names = "stmmaceth";
1193 rockchip,php-grf = <&ioc_grf>;
1194 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1195 snps,mixed-burst;
1196 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1197 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1202 compatible = "snps,dwmac-mdio";
1203 #address-cells = <0x1>;
1204 #size-cells = <0x0>;
1207 gmac1_stmmac_axi_setup: stmmac-axi-config {
1213 gmac1_mtl_rx_setup: rx-queues-config {
1214 snps,rx-queues-to-use = <1>;
1218 gmac1_mtl_tx_setup: tx-queues-config {
1219 snps,tx-queues-to-use = <1>;
1225 compatible = "rockchip,rk3576-dw-mshc";
1228 clock-names = "biu", "ciu";
1229 fifo-depth = <0x100>;
1231 max-frequency = <200000000>;
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>;
1234 power-domains = <&power RK3576_PD_SDGMAC>;
1236 reset-names = "reset";
1241 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
1243 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
1244 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1248 clock-names = "core", "bus", "axi", "block", "timer";
1250 max-frequency = <200000000>;
1251 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1253 pinctrl-names = "default";
1254 power-domains = <&power RK3576_PD_NVM>;
1258 reset-names = "core", "bus", "axi", "block", "timer";
1259 supports-cqe;
1263 gic: interrupt-controller@2a701000 {
1264 compatible = "arm,gic-400";
1270 interrupt-controller;
1271 #interrupt-cells = <3>;
1272 #address-cells = <2>;
1273 #size-cells = <2>;
1276 dmac0: dma-controller@2ab90000 {
1279 arm,pl330-periph-burst;
1281 clock-names = "apb_pclk";
1284 #dma-cells = <1>;
1287 dmac1: dma-controller@2abb0000 {
1290 arm,pl330-periph-burst;
1292 clock-names = "apb_pclk";
1295 #dma-cells = <1>;
1298 dmac2: dma-controller@2abd0000 {
1301 arm,pl330-periph-burst;
1303 clock-names = "apb_pclk";
1306 #dma-cells = <1>;
1310 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1313 clock-names = "i2c", "pclk";
1315 pinctrl-names = "default";
1316 pinctrl-0 = <&i2c1m0_xfer>;
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1323 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1326 clock-names = "i2c", "pclk";
1328 pinctrl-names = "default";
1329 pinctrl-0 = <&i2c2m0_xfer>;
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1336 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1339 clock-names = "i2c", "pclk";
1341 pinctrl-names = "default";
1342 pinctrl-0 = <&i2c3m0_xfer>;
1343 #address-cells = <1>;
1344 #size-cells = <0>;
1349 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1352 clock-names = "i2c", "pclk";
1354 pinctrl-names = "default";
1355 pinctrl-0 = <&i2c4m0_xfer>;
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1362 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1365 clock-names = "i2c", "pclk";
1367 pinctrl-names = "default";
1368 pinctrl-0 = <&i2c5m0_xfer>;
1369 #address-cells = <1>;
1370 #size-cells = <0>;
1376 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1379 clock-names = "i2c", "pclk";
1381 pinctrl-names = "default";
1382 pinctrl-0 = <&i2c6m0_xfer>;
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1389 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1392 clock-names = "i2c", "pclk";
1394 pinctrl-names = "default";
1395 pinctrl-0 = <&i2c7m0_xfer>;
1396 #address-cells = <1>;
1397 #size-cells = <0>;
1402 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1405 clock-names = "i2c", "pclk";
1407 pinctrl-names = "default";
1408 pinctrl-0 = <&i2c8m0_xfer>;
1409 #address-cells = <1>;
1410 #size-cells = <0>;
1415 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer";
1418 clock-names = "pclk", "timer";
1423 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt";
1426 clock-names = "tclk", "pclk";
1432 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1435 clock-names = "spiclk", "apb_pclk";
1437 dma-names = "tx", "rx";
1439 num-cs = <2>;
1440 pinctrl-names = "default";
1441 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
1442 #address-cells = <1>;
1443 #size-cells = <0>;
1448 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1451 clock-names = "spiclk", "apb_pclk";
1453 dma-names = "tx", "rx";
1455 num-cs = <2>;
1456 pinctrl-names = "default";
1457 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1464 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1467 clock-names = "spiclk", "apb_pclk";
1469 dma-names = "tx", "rx";
1471 num-cs = <2>;
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1480 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1483 clock-names = "spiclk", "apb_pclk";
1485 dma-names = "tx", "rx";
1487 num-cs = <2>;
1488 pinctrl-names = "default";
1489 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>;
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1496 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1499 clock-names = "spiclk", "apb_pclk";
1501 dma-names = "tx", "rx";
1503 num-cs = <2>;
1504 pinctrl-names = "default";
1505 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>;
1506 #address-cells = <1>;
1507 #size-cells = <0>;
1512 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1514 reg-shift = <2>;
1515 reg-io-width = <4>;
1517 clock-names = "baudclk", "apb_pclk";
1519 dma-names = "tx", "rx";
1521 pinctrl-0 = <&uart0m0_xfer>;
1522 pinctrl-names = "default";
1527 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1529 reg-shift = <2>;
1530 reg-io-width = <4>;
1532 clock-names = "baudclk", "apb_pclk";
1534 dma-names = "tx", "rx";
1536 pinctrl-names = "default";
1537 pinctrl-0 = <&uart2m0_xfer>;
1542 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1544 reg-shift = <2>;
1545 reg-io-width = <4>;
1547 clock-names = "baudclk", "apb_pclk";
1549 dma-names = "tx", "rx";
1551 pinctrl-0 = <&uart3m0_xfer>;
1552 pinctrl-names = "default";
1557 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1559 reg-shift = <2>;
1560 reg-io-width = <4>;
1562 clock-names = "baudclk", "apb_pclk";
1564 dma-names = "tx", "rx";
1566 pinctrl-0 = <&uart4m0_xfer>;
1567 pinctrl-names = "default";
1572 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1574 reg-shift = <2>;
1575 reg-io-width = <4>;
1577 clock-names = "baudclk", "apb_pclk";
1579 dma-names = "tx", "rx";
1581 pinctrl-0 = <&uart5m0_xfer>;
1582 pinctrl-names = "default";
1587 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1589 reg-shift = <2>;
1590 reg-io-width = <4>;
1592 clock-names = "baudclk", "apb_pclk";
1594 dma-names = "tx", "rx";
1596 pinctrl-0 = <&uart6m0_xfer>;
1597 pinctrl-names = "default";
1602 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1604 reg-shift = <2>;
1605 reg-io-width = <4>;
1607 clock-names = "baudclk", "apb_pclk";
1609 dma-names = "tx", "rx";
1611 pinctrl-0 = <&uart7m0_xfer>;
1612 pinctrl-names = "default";
1617 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1619 reg-shift = <2>;
1620 reg-io-width = <4>;
1622 clock-names = "baudclk", "apb_pclk";
1624 dma-names = "tx", "rx";
1626 pinctrl-0 = <&uart8m0_xfer>;
1627 pinctrl-names = "default";
1632 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1634 reg-shift = <2>;
1635 reg-io-width = <4>;
1637 clock-names = "baudclk", "apb_pclk";
1639 dma-names = "tx", "rx";
1641 pinctrl-0 = <&uart9m0_xfer>;
1642 pinctrl-names = "default";
1647 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
1650 clock-names = "saradc", "apb_pclk";
1653 reset-names = "saradc-apb";
1654 #io-channel-cells = <1>;
1659 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1662 clock-names = "i2c", "pclk";
1664 pinctrl-names = "default";
1665 pinctrl-0 = <&i2c9m0_xfer>;
1667 reset-names = "i2c", "apb";
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1674 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1676 reg-shift = <2>;
1677 reg-io-width = <4>;
1679 clock-names = "baudclk", "apb_pclk";
1682 pinctrl-names = "default";
1683 pinctrl-0 = <&uart10m0_xfer>;
1688 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1690 reg-shift = <2>;
1691 reg-io-width = <4>;
1693 clock-names = "baudclk", "apb_pclk";
1696 pinctrl-names = "default";
1697 pinctrl-0 = <&uart11m0_xfer>;
1702 compatible = "rockchip,rk3576-naneng-combphy";
1704 #phy-cells = <1>;
1708 clock-names = "ref", "apb", "pipe";
1709 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
1710 assigned-clock-rates = <100000000>;
1713 reset-names = "phy", "apb";
1714 rockchip,pipe-grf = <&php_grf>;
1715 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
1720 compatible = "rockchip,rk3576-naneng-combphy";
1722 #phy-cells = <1>;
1726 clock-names = "ref", "apb", "pipe";
1727 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
1728 assigned-clock-rates = <100000000>;
1731 reset-names = "phy", "apb";
1732 rockchip,pipe-grf = <&php_grf>;
1733 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
1738 compatible = "rockchip,rk3576-usbdp-phy";
1740 #phy-cells = <1>;
1745 clock-names = "refclk", "immortal", "pclk", "utmi";
1751 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
1752 rockchip,u2phy-grf = <&usb2phy_grf>;
1753 rockchip,usb-grf = <&usb_grf>;
1754 rockchip,usbdpphy-grf = <&usbdpphy_grf>;
1755 rockchip,vo-grf = <&vo1_grf>;
1760 compatible = "mmio-sram";
1763 #address-cells = <1>;
1764 #size-cells = <1>;
1767 rkvdec_sram: rkvdec-sram@0 {
1772 scmi_shmem: scmi-shmem@4010f000 {
1773 compatible = "arm,scmi-shmem";
1778 compatible = "rockchip,rk3576-pinctrl";
1780 #address-cells = <2>;
1781 #size-cells = <2>;
1785 compatible = "rockchip,gpio-bank";
1788 gpio-controller;
1789 gpio-ranges = <&pinctrl 0 0 32>;
1791 interrupt-controller;
1792 #gpio-cells = <2>;
1793 #interrupt-cells = <2>;
1797 compatible = "rockchip,gpio-bank";
1800 gpio-controller;
1801 gpio-ranges = <&pinctrl 0 32 32>;
1803 interrupt-controller;
1804 #gpio-cells = <2>;
1805 #interrupt-cells = <2>;
1809 compatible = "rockchip,gpio-bank";
1812 gpio-controller;
1813 gpio-ranges = <&pinctrl 0 64 32>;
1815 interrupt-controller;
1816 #gpio-cells = <2>;
1817 #interrupt-cells = <2>;
1821 compatible = "rockchip,gpio-bank";
1824 gpio-controller;
1825 gpio-ranges = <&pinctrl 0 96 32>;
1827 interrupt-controller;
1828 #gpio-cells = <2>;
1829 #interrupt-cells = <2>;
1833 compatible = "rockchip,gpio-bank";
1836 gpio-controller;
1837 gpio-ranges = <&pinctrl 0 128 32>;
1839 interrupt-controller;
1840 #gpio-cells = <2>;
1841 #interrupt-cells = <2>;
1847 #include "rk3576-pinctrl.dtsi"