Lines Matching +full:riic +full:- +full:rz
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G3E SoC
8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_extal_clk: audio-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
30 cluster0_opp: opp-table-0 {
31 compatible = "operating-points-v2";
33 opp-1700000000 {
34 opp-hz = /bits/ 64 <1700000000>;
35 opp-microvolt = <900000>;
36 clock-latency-ns = <300000>;
38 opp-850000000 {
39 opp-hz = /bits/ 64 <850000000>;
40 opp-microvolt = <800000>;
41 clock-latency-ns = <300000>;
43 opp-425000000 {
44 opp-hz = /bits/ 64 <425000000>;
45 opp-microvolt = <800000>;
46 clock-latency-ns = <300000>;
48 opp-212500000 {
49 opp-hz = /bits/ 64 <212500000>;
50 opp-microvolt = <800000>;
51 clock-latency-ns = <300000>;
52 opp-suspend;
57 #address-cells = <1>;
58 #size-cells = <0>;
61 compatible = "arm,cortex-a55";
64 next-level-cache = <&L3_CA55>;
65 enable-method = "psci";
67 operating-points-v2 = <&cluster0_opp>;
71 compatible = "arm,cortex-a55";
74 next-level-cache = <&L3_CA55>;
75 enable-method = "psci";
77 operating-points-v2 = <&cluster0_opp>;
81 compatible = "arm,cortex-a55";
84 next-level-cache = <&L3_CA55>;
85 enable-method = "psci";
87 operating-points-v2 = <&cluster0_opp>;
91 compatible = "arm,cortex-a55";
94 next-level-cache = <&L3_CA55>;
95 enable-method = "psci";
97 operating-points-v2 = <&cluster0_opp>;
100 L3_CA55: cache-controller-0 {
102 cache-unified;
103 cache-size = <0x100000>;
104 cache-level = <3>;
109 compatible = "arm,psci-1.0", "arm,psci-0.2";
113 qextal_clk: qextal-clk {
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
117 clock-frequency = <0>;
120 rtxin_clk: rtxin-clk {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
124 clock-frequency = <0>;
128 compatible = "simple-bus";
129 interrupt-parent = <&gic>;
130 #address-cells = <2>;
131 #size-cells = <2>;
135 compatible = "renesas,r9a09g047-pinctrl";
138 gpio-controller;
139 #gpio-cells = <2>;
140 gpio-ranges = <&pinctrl 0 0 232>;
141 #interrupt-cells = <2>;
142 interrupt-controller;
143 power-domains = <&cpg>;
147 cpg: clock-controller@10420000 {
148 compatible = "renesas,r9a09g047-cpg";
151 clock-names = "audio_extal", "rtxin", "qextal";
152 #clock-cells = <2>;
153 #reset-cells = <1>;
154 #power-domain-cells = <0>;
158 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
169 interrupt-names = "eri", "rxi", "txi", "bri", "dri",
170 "tei", "tei-dri", "rxi-edge", "txi-edge";
172 clock-names = "fck";
173 power-domains = <&cpg>;
179 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
189 interrupt-names = "tei", "ri", "ti", "spi", "sti",
193 power-domains = <&cpg>;
194 #address-cells = <1>;
195 #size-cells = <0>;
200 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
210 interrupt-names = "tei", "ri", "ti", "spi", "sti",
214 power-domains = <&cpg>;
215 #address-cells = <1>;
216 #size-cells = <0>;
221 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
231 interrupt-names = "tei", "ri", "ti", "spi", "sti",
235 power-domains = <&cpg>;
236 #address-cells = <1>;
237 #size-cells = <0>;
242 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
252 interrupt-names = "tei", "ri", "ti", "spi", "sti",
256 power-domains = <&cpg>;
257 #address-cells = <1>;
258 #size-cells = <0>;
263 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
273 interrupt-names = "tei", "ri", "ti", "spi", "sti",
277 power-domains = <&cpg>;
278 #address-cells = <1>;
279 #size-cells = <0>;
284 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
294 interrupt-names = "tei", "ri", "ti", "spi", "sti",
298 power-domains = <&cpg>;
299 #address-cells = <1>;
300 #size-cells = <0>;
305 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
315 interrupt-names = "tei", "ri", "ti", "spi", "sti",
319 power-domains = <&cpg>;
320 #address-cells = <1>;
321 #size-cells = <0>;
326 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
336 interrupt-names = "tei", "ri", "ti", "spi", "sti",
340 power-domains = <&cpg>;
341 #address-cells = <1>;
342 #size-cells = <0>;
347 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
357 interrupt-names = "tei", "ri", "ti", "spi", "sti",
361 power-domains = <&cpg>;
362 #address-cells = <1>;
363 #size-cells = <0>;
367 gic: interrupt-controller@14900000 {
368 compatible = "arm,gic-v3";
371 #interrupt-cells = <3>;
372 #address-cells = <0>;
373 interrupt-controller;
379 compatible = "arm,armv8-timer";
380 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
385 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";