Lines Matching +full:- +full:cpg
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
10 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 audio_clk1: audio1-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
24 audio_clk2: audio2-clk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
28 clock-frequency = <0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
36 compatible = "arm,cortex-a55";
39 #cooling-cells = <2>;
40 next-level-cache = <&L3_CA55>;
41 enable-method = "psci";
42 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
45 L3_CA55: cache-controller-0 {
47 cache-level = <3>;
48 cache-unified;
49 cache-size = <0x40000>;
53 extal_clk: extal-clk {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
57 clock-frequency = <0>;
61 compatible = "arm,psci-1.0", "arm,psci-0.2";
66 compatible = "simple-bus";
67 interrupt-parent = <&gic>;
68 #address-cells = <2>;
69 #size-cells = <2>;
73 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
81 interrupt-names = "eri", "rxi", "txi",
83 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
84 clock-names = "fck";
85 power-domains = <&cpg>;
86 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
91 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
99 interrupt-names = "eri", "rxi", "txi",
101 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
102 clock-names = "fck";
103 power-domains = <&cpg>;
104 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
109 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
117 interrupt-names = "eri", "rxi", "txi",
119 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
120 clock-names = "fck";
121 power-domains = <&cpg>;
122 resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>;
127 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
135 interrupt-names = "eri", "rxi", "txi",
137 clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>;
138 clock-names = "fck";
139 power-domains = <&cpg>;
140 resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>;
145 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
153 interrupt-names = "eri", "rxi", "txi",
155 clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>;
156 clock-names = "fck";
157 power-domains = <&cpg>;
158 resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>;
163 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
171 interrupt-names = "eri", "rxi", "txi",
173 clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>;
174 clock-names = "fck";
175 power-domains = <&cpg>;
176 resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>;
181 compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
186 interrupt-names = "alarm", "period", "carry";
187 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
188 clock-names = "bus", "counter";
189 power-domains = <&cpg>;
190 resets = <&cpg R9A08G045_VBAT_BRESETN>;
195 compatible = "renesas,r9a08g045-adc";
198 clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>,
199 <&cpg CPG_MOD R9A08G045_ADC_PCLK>;
200 clock-names = "adclk", "pclk";
201 resets = <&cpg R9A08G045_ADC_PRESETN>,
202 <&cpg R9A08G045_ADC_ADRST_N>;
203 reset-names = "presetn", "adrst-n";
204 power-domains = <&cpg>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 #io-channel-cells = <1>;
247 vbattb: clock-controller@1005c000 {
248 compatible = "renesas,r9a08g045-vbattb";
251 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
252 clock-names = "bclk", "rtx";
253 #clock-cells = <1>;
254 power-domains = <&cpg>;
255 resets = <&cpg R9A08G045_VBAT_BRESETN>;
260 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
270 interrupt-names = "tei", "ri", "ti", "spi", "sti",
272 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
273 clock-frequency = <100000>;
274 resets = <&cpg R9A08G045_I2C0_MRST>;
275 power-domains = <&cpg>;
276 #address-cells = <1>;
277 #size-cells = <0>;
282 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
292 interrupt-names = "tei", "ri", "ti", "spi", "sti",
294 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
295 clock-frequency = <100000>;
296 resets = <&cpg R9A08G045_I2C1_MRST>;
297 power-domains = <&cpg>;
298 #address-cells = <1>;
299 #size-cells = <0>;
304 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
314 interrupt-names = "tei", "ri", "ti", "spi", "sti",
316 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
317 clock-frequency = <100000>;
318 resets = <&cpg R9A08G045_I2C2_MRST>;
319 power-domains = <&cpg>;
320 #address-cells = <1>;
321 #size-cells = <0>;
326 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
336 interrupt-names = "tei", "ri", "ti", "spi", "sti",
338 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
339 clock-frequency = <100000>;
340 resets = <&cpg R9A08G045_I2C3_MRST>;
341 power-domains = <&cpg>;
342 #address-cells = <1>;
343 #size-cells = <0>;
348 compatible = "renesas,r9a08g045-ssi",
349 "renesas,rz-ssi";
354 interrupt-names = "int_req", "dma_rx", "dma_tx";
355 clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>,
356 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>,
358 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
359 resets = <&cpg R9A08G045_SSI0_RST_M2_REG>;
361 dma-names = "tx", "rx";
362 power-domains = <&cpg>;
363 #sound-dai-cells = <0>;
368 compatible = "renesas,r9a08g045-ssi",
369 "renesas,rz-ssi";
374 interrupt-names = "int_req", "dma_rx", "dma_tx";
375 clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>,
376 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>,
378 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
379 resets = <&cpg R9A08G045_SSI1_RST_M2_REG>;
381 dma-names = "tx", "rx";
382 power-domains = <&cpg>;
383 #sound-dai-cells = <0>;
388 compatible = "renesas,r9a08g045-ssi",
389 "renesas,rz-ssi";
394 interrupt-names = "int_req", "dma_rx", "dma_tx";
395 clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>,
396 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>,
398 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
399 resets = <&cpg R9A08G045_SSI2_RST_M2_REG>;
401 dma-names = "tx", "rx";
402 power-domains = <&cpg>;
403 #sound-dai-cells = <0>;
408 compatible = "renesas,r9a08g045-ssi",
409 "renesas,rz-ssi";
414 interrupt-names = "int_req", "dma_rx", "dma_tx";
415 clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
416 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
418 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
419 resets = <&cpg R9A08G045_SSI3_RST_M2_REG>;
421 dma-names = "tx", "rx";
422 power-domains = <&cpg>;
423 #sound-dai-cells = <0>;
427 cpg: clock-controller@11010000 { label
428 compatible = "renesas,r9a08g045-cpg";
431 clock-names = "extal";
432 #clock-cells = <2>;
433 #reset-cells = <1>;
434 #power-domain-cells = <0>;
437 sysc: system-controller@11020000 {
438 compatible = "renesas,r9a08g045-sysc";
444 interrupt-names = "lpm_int", "ca55stbydone_int",
450 compatible = "renesas,r9a08g045-pinctrl";
452 gpio-controller;
453 #gpio-cells = <2>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 interrupt-parent = <&irqc>;
457 gpio-ranges = <&pinctrl 0 0 152>;
458 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
459 power-domains = <&cpg>;
460 resets = <&cpg R9A08G045_GPIO_RSTN>,
461 <&cpg R9A08G045_GPIO_PORT_RESETN>,
462 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
465 irqc: interrupt-controller@11050000 {
466 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
467 #interrupt-cells = <2>;
468 #address-cells = <0>;
469 interrupt-controller;
516 interrupt-names = "nmi",
527 "bus-err", "ec7tie1-0", "ec7tie2-0",
528 "ec7tiovf-0";
529 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
530 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
531 clock-names = "clk", "pclk";
532 power-domains = <&cpg>;
533 resets = <&cpg R9A08G045_IA55_RESETN>;
536 dmac: dma-controller@11820000 {
537 compatible = "renesas,r9a08g045-dmac",
538 "renesas,rz-dmac";
558 interrupt-names = "error",
563 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
564 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
565 clock-names = "main", "register";
566 power-domains = <&cpg>;
567 resets = <&cpg R9A08G045_DMAC_ARESETN>,
568 <&cpg R9A08G045_DMAC_RST_ASYNC>;
569 reset-names = "arst", "rst_async";
570 #dma-cells = <1>;
571 dma-channels = <16>;
575 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
579 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
580 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
581 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
582 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
583 clock-names = "core", "clkh", "cd", "aclk";
584 resets = <&cpg R9A08G045_SDHI0_IXRST>;
585 power-domains = <&cpg>;
590 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
594 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
595 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
596 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
597 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
598 clock-names = "core", "clkh", "cd", "aclk";
599 resets = <&cpg R9A08G045_SDHI1_IXRST>;
600 power-domains = <&cpg>;
605 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
609 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
610 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
611 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
612 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
613 clock-names = "core", "clkh", "cd", "aclk";
614 resets = <&cpg R9A08G045_SDHI2_IXRST>;
615 power-domains = <&cpg>;
620 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
625 interrupt-names = "mux", "fil", "arp_ns";
626 phy-mode = "rgmii";
627 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
628 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
629 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
630 clock-names = "axi", "chi", "refclk";
631 resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
632 power-domains = <&cpg>;
633 #address-cells = <1>;
634 #size-cells = <0>;
639 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
644 interrupt-names = "mux", "fil", "arp_ns";
645 phy-mode = "rgmii";
646 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
647 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
648 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
649 clock-names = "axi", "chi", "refclk";
650 resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
651 power-domains = <&cpg>;
652 #address-cells = <1>;
653 #size-cells = <0>;
657 gic: interrupt-controller@12400000 {
658 compatible = "arm,gic-v3";
659 #interrupt-cells = <3>;
660 #address-cells = <0>;
661 interrupt-controller;
668 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
670 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
671 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
672 clock-names = "pclk", "oscclk";
675 interrupt-names = "wdt", "perrout";
676 resets = <&cpg R9A08G045_WDT0_PRESETN>;
677 power-domains = <&cpg>;
683 compatible = "arm,armv8-timer";
684 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
689 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
690 "hyp-virt";
693 vbattb_xtal: vbattb-xtal {
694 compatible = "fixed-clock";
695 #clock-cells = <0>;
697 clock-frequency = <0>;