Lines Matching +full:0 +full:xe61a0000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
67 a76_0: cpu@0 {
69 reg = <0>;
81 reg = <0x100>;
93 reg = <0x200>;
105 reg = <0x300>;
118 CPU_SLEEP_0: cpu-sleep-0 {
120 arm,psci-suspend-param = <0x0010000>;
138 #clock-cells = <0>;
140 clock-frequency = <0>;
145 #clock-cells = <0>;
147 clock-frequency = <0>;
152 #clock-cells = <0>;
154 clock-frequency = <0>;
170 #clock-cells = <0>;
171 clock-frequency = <0>;
176 #clock-cells = <0>;
177 clock-frequency = <0>;
190 reg = <0 0xe6020000 0 0x0c>;
200 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
201 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
202 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
203 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
209 reg = <0 0xe6050180 0 0x54>;
213 gpio-ranges = <&pfc 0 0 19>;
224 reg = <0 0xe6050980 0 0x54>;
228 gpio-ranges = <&pfc 0 32 30>;
239 reg = <0 0xe6058180 0 0x54>;
243 gpio-ranges = <&pfc 0 64 20>;
254 reg = <0 0xe6058980 0 0x54>;
258 gpio-ranges = <&pfc 0 96 32>;
269 reg = <0 0xe6060180 0 0x54>;
273 gpio-ranges = <&pfc 0 128 25>;
284 reg = <0 0xe6060980 0 0x54>;
288 gpio-ranges = <&pfc 0 160 21>;
299 reg = <0 0xe6061180 0 0x54>;
303 gpio-ranges = <&pfc 0 192 21>;
314 reg = <0 0xe6061980 0 0x54>;
318 gpio-ranges = <&pfc 0 224 21>;
329 reg = <0 0xe60f0000 0 0x1004>;
342 reg = <0 0xe6130000 0 0x1004>;
361 reg = <0 0xe6140000 0 0x1004>;
380 reg = <0 0xe6148000 0 0x1004>;
398 reg = <0 0xe6150000 0 0x4000>;
402 #power-domain-cells = <0>;
408 reg = <0 0xe6160000 0 0x4000>;
413 reg = <0 0xe6180000 0 0x4000>;
419 reg = <0 0xe6198000 0 0x200>,
420 <0 0xe61a0000 0 0x200>;
429 reg = <0 0xe61be000 0 0x1000>, <0 0xe61bf000 0 0x1000>;
436 reg = <0 0xe61c0000 0 0x200>;
437 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
450 reg = <0 0xe61e0000 0 0x30>;
464 reg = <0 0xe6fc0000 0 0x30>;
479 reg = <0 0xe6fd0000 0 0x30>;
494 reg = <0 0xe6fe0000 0 0x30>;
509 reg = <0 0xffc00000 0 0x30>;
525 reg = <0 0xe6500000 0 0x40>;
530 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
531 <&dmac2 0x91>, <&dmac2 0x90>;
535 #size-cells = <0>;
542 reg = <0 0xe6508000 0 0x40>;
547 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
548 <&dmac2 0x93>, <&dmac2 0x92>;
552 #size-cells = <0>;
559 reg = <0 0xe6510000 0 0x40>;
564 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
565 <&dmac2 0x95>, <&dmac2 0x94>;
569 #size-cells = <0>;
576 reg = <0 0xe66d0000 0 0x40>;
581 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
582 <&dmac2 0x97>, <&dmac2 0x96>;
586 #size-cells = <0>;
593 reg = <0 0xe6540000 0 0x60>;
601 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
602 <&dmac2 0x31>, <&dmac2 0x30>;
610 reg = <0 0xe6550000 0 0x60>;
618 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
619 <&dmac2 0x33>, <&dmac2 0x32>;
627 reg = <0 0xe6560000 0 0x60>;
635 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
636 <&dmac2 0x35>, <&dmac2 0x34>;
644 reg = <0 0xe66a0000 0 0x60>;
652 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
653 <&dmac2 0x37>, <&dmac2 0x36>;
661 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
662 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
663 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
664 <0 0xfe000000 0 0x400000>;
680 bus-range = <0x00 0xff>;
682 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
683 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
684 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
686 interrupt-map-mask = <0 0 0 7>;
687 interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
688 <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
689 <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
690 <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
698 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
699 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
700 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
701 <0 0xfe000000 0 0x400000>;
721 reg = <0 0xe6660000 0 0x8500>;
755 reg = <0 0xe6800000 0 0x1000>;
793 rx-internal-delay-ps = <0>;
794 tx-internal-delay-ps = <0>;
795 iommus = <&ipmmu_hc 0>;
797 #size-cells = <0>;
804 reg = <0 0xe6810000 0 0x1000>;
842 rx-internal-delay-ps = <0>;
843 tx-internal-delay-ps = <0>;
846 #size-cells = <0>;
853 reg = <0 0xe6820000 0 0x1000>;
891 rx-internal-delay-ps = <0>;
892 tx-internal-delay-ps = <0>;
895 #size-cells = <0>;
901 reg = <0 0xe6e30000 0 0x10>;
911 reg = <0 0xe6e31000 0 0x10>;
921 reg = <0 0xe6e32000 0 0x10>;
931 reg = <0 0xe6e33000 0 0x10>;
941 reg = <0 0xe6e34000 0 0x10>;
952 reg = <0 0xe6e60000 0 64>;
960 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
961 <&dmac2 0x51>, <&dmac2 0x50>;
969 reg = <0 0xe6e68000 0 64>;
977 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
978 <&dmac2 0x53>, <&dmac2 0x52>;
986 reg = <0 0xe6c50000 0 64>;
994 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
995 <&dmac2 0x57>, <&dmac2 0x56>;
1003 reg = <0 0xe6c40000 0 64>;
1011 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
1012 <&dmac2 0x59>, <&dmac2 0x58>;
1020 reg = <0 0xe6e90000 0 0x0064>;
1023 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1024 <&dmac2 0x41>, <&dmac2 0x40>;
1029 #size-cells = <0>;
1036 reg = <0 0xe6ea0000 0 0x0064>;
1039 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1040 <&dmac2 0x43>, <&dmac2 0x42>;
1045 #size-cells = <0>;
1052 reg = <0 0xe6c00000 0 0x0064>;
1055 dmas = <&dmac1 0x45>, <&dmac1 0x44>,
1056 <&dmac2 0x45>, <&dmac2 0x44>;
1061 #size-cells = <0>;
1068 reg = <0 0xe6c10000 0 0x0064>;
1071 dmas = <&dmac1 0x47>, <&dmac1 0x46>,
1072 <&dmac2 0x47>, <&dmac2 0x46>;
1077 #size-cells = <0>;
1084 reg = <0 0xe6c20000 0 0x0064>;
1087 dmas = <&dmac1 0x49>, <&dmac1 0x48>,
1088 <&dmac2 0x49>, <&dmac2 0x48>;
1093 #size-cells = <0>;
1100 reg = <0 0xe6c28000 0 0x0064>;
1103 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>,
1104 <&dmac2 0x4b>, <&dmac2 0x4a>;
1109 #size-cells = <0>;
1116 reg = <0 0xe6ef0000 0 0x1000>;
1121 renesas,id = <0>;
1126 #size-cells = <0>;
1130 #size-cells = <0>;
1134 vin00isp0: endpoint@0 {
1135 reg = <0>;
1145 reg = <0 0xe6ef1000 0 0x1000>;
1155 #size-cells = <0>;
1159 #size-cells = <0>;
1163 vin01isp0: endpoint@0 {
1164 reg = <0>;
1174 reg = <0 0xe6ef2000 0 0x1000>;
1184 #size-cells = <0>;
1188 #size-cells = <0>;
1192 vin02isp0: endpoint@0 {
1193 reg = <0>;
1203 reg = <0 0xe6ef3000 0 0x1000>;
1213 #size-cells = <0>;
1217 #size-cells = <0>;
1221 vin03isp0: endpoint@0 {
1222 reg = <0>;
1232 reg = <0 0xe6ef4000 0 0x1000>;
1242 #size-cells = <0>;
1246 #size-cells = <0>;
1250 vin04isp0: endpoint@0 {
1251 reg = <0>;
1261 reg = <0 0xe6ef5000 0 0x1000>;
1271 #size-cells = <0>;
1275 #size-cells = <0>;
1279 vin05isp0: endpoint@0 {
1280 reg = <0>;
1290 reg = <0 0xe6ef6000 0 0x1000>;
1300 #size-cells = <0>;
1304 #size-cells = <0>;
1308 vin06isp0: endpoint@0 {
1309 reg = <0>;
1319 reg = <0 0xe6ef7000 0 0x1000>;
1329 #size-cells = <0>;
1333 #size-cells = <0>;
1337 vin07isp0: endpoint@0 {
1338 reg = <0>;
1348 reg = <0 0xe6ef8000 0 0x1000>;
1358 #size-cells = <0>;
1362 #size-cells = <0>;
1377 reg = <0 0xe6ef9000 0 0x1000>;
1387 #size-cells = <0>;
1391 #size-cells = <0>;
1406 reg = <0 0xe6efa000 0 0x1000>;
1416 #size-cells = <0>;
1420 #size-cells = <0>;
1435 reg = <0 0xe6efb000 0 0x1000>;
1445 #size-cells = <0>;
1449 #size-cells = <0>;
1464 reg = <0 0xe6efc000 0 0x1000>;
1474 #size-cells = <0>;
1478 #size-cells = <0>;
1493 reg = <0 0xe6efd000 0 0x1000>;
1503 #size-cells = <0>;
1507 #size-cells = <0>;
1522 reg = <0 0xe6efe000 0 0x1000>;
1532 #size-cells = <0>;
1536 #size-cells = <0>;
1551 reg = <0 0xe6eff000 0 0x1000>;
1561 #size-cells = <0>;
1565 #size-cells = <0>;
1580 reg = <0 0xe7350000 0 0x1000>,
1581 <0 0xe7300000 0 0x10000>;
1610 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1623 reg = <0 0xe7351000 0 0x1000>,
1624 <0 0xe7310000 0 0x10000>;
1651 reg = <0 0xec400000 0 0x40000>,
1652 <0 0xec540000 0 0x1000>,
1653 <0 0xec541000 0 0x050>,
1654 <0 0xec5a0000 0 0x020>;
1657 clock-names = "ssiu.0", "ssi.0", "clkin";
1659 #clock-cells = <0>;
1661 #sound-dai-cells = <0>;
1665 reset-names = "ssiu.0", "ssi.0";
1669 ssiu00: ssiu-0 {
1670 dmas = <&dmac1 0x6e>, <&dmac1 0x6f>;
1674 dmas = <&dmac1 0x6c>, <&dmac1 0x6d>;
1678 dmas = <&dmac1 0x6a>, <&dmac1 0x6b>;
1682 dmas = <&dmac1 0x68>, <&dmac1 0x69>;
1686 dmas = <&dmac1 0x66>, <&dmac1 0x67>;
1690 dmas = <&dmac1 0x64>, <&dmac1 0x65>;
1694 dmas = <&dmac1 0x62>, <&dmac1 0x63>;
1698 dmas = <&dmac1 0x60>, <&dmac1 0x61>;
1704 ssi0: ssi-0 {
1713 reg = <0 0xee140000 0 0x2000>;
1728 reg = <0 0xee200000 0 0x200>,
1729 <0 0x08000000 0 0x04000000>,
1730 <0 0xee208000 0 0x100>;
1737 #size-cells = <0>;
1744 reg = <0 0xee480000 0 0x20000>;
1753 reg = <0 0xee4c0000 0 0x20000>;
1762 reg = <0 0xeed00000 0 0x20000>;
1771 reg = <0 0xeed40000 0 0x20000>;
1780 reg = <0 0xeed80000 0 0x20000>;
1789 reg = <0 0xeedc0000 0 0x20000>;
1798 reg = <0 0xeee00000 0 0x20000>;
1807 reg = <0 0xeee80000 0 0x20000>;
1816 reg = <0 0xeeec0000 0 0x20000>;
1825 reg = <0 0xeef00000 0 0x20000>;
1834 reg = <0 0xeefc0000 0 0x20000>;
1844 #address-cells = <0>;
1846 reg = <0x0 0xf1000000 0 0x20000>,
1847 <0x0 0xf1060000 0 0x110000>;
1853 reg = <0 0xfe500000 0 0x40000>;
1862 #size-cells = <0>;
1864 port@0 {
1865 reg = <0>;
1879 reg = <0 0xfe540000 0 0x40000>;
1888 #size-cells = <0>;
1890 port@0 {
1891 reg = <0>;
1905 reg = <0 0xfea10000 0 0x200>;
1913 reg = <0 0xfea20000 0 0x8000>;
1923 reg = <0 0xfeb00000 0 0x40000>;
1926 clock-names = "du.0";
1929 reset-names = "du.0";
1930 renesas,vsps = <&vspd0 0>;
1936 #size-cells = <0>;
1938 port@0 {
1939 reg = <0>;
1950 reg = <0 0xfed00000 0 0x10000>;
1959 #size-cells = <0>;
1961 port@0 {
1963 #size-cells = <0>;
1965 reg = <0>;
1967 isp0csi40: endpoint@0 {
1968 reg = <0>;
2034 reg = <0 0xfed20000 0 0x10000>;
2043 #size-cells = <0>;
2045 port@0 {
2047 #size-cells = <0>;
2049 reg = <0>;
2117 reg = <0 0xfed80000 0 0x10000>;
2129 #size-cells = <0>;
2131 port@0 {
2132 reg = <0>;
2146 reg = <0 0xfff00044 0 4>;
2154 thermal-sensors = <&tsc 0>;