Lines Matching +full:opp +full:- +full:fuse +full:- +full:level
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
21 opp-500000000 {
22 opp-hz = /bits/ 64 <500000000>;
23 opp-microvolt = <880000>;
24 clock-latency-ns = <500000>;
26 opp-800000000 {
27 opp-hz = /bits/ 64 <800000000>;
28 opp-microvolt = <880000>;
29 clock-latency-ns = <500000>;
31 opp-1000000000 {
32 opp-hz = /bits/ 64 <1000000000>;
33 opp-microvolt = <880000>;
34 clock-latency-ns = <500000>;
36 opp-1200000000 {
37 opp-hz = /bits/ 64 <1200000000>;
38 opp-microvolt = <880000>;
39 clock-latency-ns = <500000>;
40 opp-suspend;
44 cluster23_opp: opp-table-1 {
45 compatible = "operating-points-v2";
46 opp-shared;
48 opp-500000000 {
49 opp-hz = /bits/ 64 <500000000>;
50 opp-microvolt = <880000>;
51 clock-latency-ns = <500000>;
53 opp-800000000 {
54 opp-hz = /bits/ 64 <800000000>;
55 opp-microvolt = <880000>;
56 clock-latency-ns = <500000>;
58 opp-1000000000 {
59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <880000>;
61 clock-latency-ns = <500000>;
63 opp-1200000000 {
64 opp-hz = /bits/ 64 <1200000000>;
65 opp-microvolt = <880000>;
66 clock-latency-ns = <500000>;
67 opp-suspend;
72 #address-cells = <1>;
73 #size-cells = <0>;
75 cpu-map {
114 compatible = "arm,cortex-a55";
117 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
118 next-level-cache = <&L3_CA55_0>;
119 enable-method = "psci";
120 cpu-idle-states = <&CPU_SLEEP_0>;
122 operating-points-v2 = <&cluster01_opp>;
126 compatible = "arm,cortex-a55";
129 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
130 next-level-cache = <&L3_CA55_0>;
131 enable-method = "psci";
132 cpu-idle-states = <&CPU_SLEEP_0>;
134 operating-points-v2 = <&cluster01_opp>;
138 compatible = "arm,cortex-a55";
141 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
142 next-level-cache = <&L3_CA55_1>;
143 enable-method = "psci";
144 cpu-idle-states = <&CPU_SLEEP_0>;
146 operating-points-v2 = <&cluster01_opp>;
150 compatible = "arm,cortex-a55";
153 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
154 next-level-cache = <&L3_CA55_1>;
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0>;
158 operating-points-v2 = <&cluster01_opp>;
162 compatible = "arm,cortex-a55";
165 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
166 next-level-cache = <&L3_CA55_2>;
167 enable-method = "psci";
168 cpu-idle-states = <&CPU_SLEEP_0>;
170 operating-points-v2 = <&cluster23_opp>;
174 compatible = "arm,cortex-a55";
177 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
178 next-level-cache = <&L3_CA55_2>;
179 enable-method = "psci";
180 cpu-idle-states = <&CPU_SLEEP_0>;
182 operating-points-v2 = <&cluster23_opp>;
186 compatible = "arm,cortex-a55";
189 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
190 next-level-cache = <&L3_CA55_3>;
191 enable-method = "psci";
192 cpu-idle-states = <&CPU_SLEEP_0>;
194 operating-points-v2 = <&cluster23_opp>;
198 compatible = "arm,cortex-a55";
201 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
202 next-level-cache = <&L3_CA55_3>;
203 enable-method = "psci";
204 cpu-idle-states = <&CPU_SLEEP_0>;
206 operating-points-v2 = <&cluster23_opp>;
209 L3_CA55_0: cache-controller-0 {
211 power-domains = <&sysc R8A779F0_PD_A2E0D0>;
212 cache-unified;
213 cache-level = <3>;
216 L3_CA55_1: cache-controller-1 {
218 power-domains = <&sysc R8A779F0_PD_A2E0D1>;
219 cache-unified;
220 cache-level = <3>;
223 L3_CA55_2: cache-controller-2 {
225 power-domains = <&sysc R8A779F0_PD_A2E1D0>;
226 cache-unified;
227 cache-level = <3>;
230 L3_CA55_3: cache-controller-3 {
232 power-domains = <&sysc R8A779F0_PD_A2E1D1>;
233 cache-unified;
234 cache-level = <3>;
237 idle-states {
238 entry-method = "psci";
240 CPU_SLEEP_0: cpu-sleep-0 {
241 compatible = "arm,idle-state";
242 arm,psci-suspend-param = <0x0010000>;
243 local-timer-stop;
244 entry-latency-us = <400>;
245 exit-latency-us = <500>;
246 min-residency-us = <4000>;
252 compatible = "fixed-clock";
253 #clock-cells = <0>;
255 clock-frequency = <0>;
259 compatible = "fixed-clock";
260 #clock-cells = <0>;
262 clock-frequency = <0>;
265 pcie0_clkref: pcie0-clkref {
266 compatible = "fixed-clock";
267 #clock-cells = <0>;
269 clock-frequency = <0>;
272 pcie1_clkref: pcie1-clkref {
273 compatible = "fixed-clock";
274 #clock-cells = <0>;
276 clock-frequency = <0>;
280 compatible = "arm,cortex-a55-pmu";
281 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
285 compatible = "arm,psci-1.0", "arm,psci-0.2";
289 /* External SCIF clock - to be overridden by boards that provide it */
291 compatible = "fixed-clock";
292 #clock-cells = <0>;
293 clock-frequency = <0>;
297 compatible = "simple-bus";
298 interrupt-parent = <&gic>;
299 #address-cells = <2>;
300 #size-cells = <2>;
304 compatible = "renesas,r8a779f0-wdt",
305 "renesas,rcar-gen4-wdt";
309 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
315 compatible = "renesas,pfc-r8a779f0";
321 compatible = "renesas,gpio-r8a779f0",
322 "renesas,rcar-gen4-gpio";
326 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 gpio-ranges = <&pfc 0 0 21>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
336 compatible = "renesas,gpio-r8a779f0",
337 "renesas,rcar-gen4-gpio";
341 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = <&pfc 0 32 25>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
351 compatible = "renesas,gpio-r8a779f0",
352 "renesas,rcar-gen4-gpio";
356 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-ranges = <&pfc 0 64 17>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
366 compatible = "renesas,gpio-r8a779f0",
367 "renesas,rcar-gen4-gpio";
371 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = <&pfc 0 96 19>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
380 fuse: fuse@e6078800 { label
381 compatible = "renesas,r8a779f0-efuse";
384 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
389 compatible = "renesas,r8a779f0-cmt0",
390 "renesas,rcar-gen4-cmt0";
395 clock-names = "fck";
396 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
402 compatible = "renesas,r8a779f0-cmt1",
403 "renesas,rcar-gen4-cmt1";
414 clock-names = "fck";
415 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
421 compatible = "renesas,r8a779f0-cmt1",
422 "renesas,rcar-gen4-cmt1";
433 clock-names = "fck";
434 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
440 compatible = "renesas,r8a779f0-cmt1",
441 "renesas,rcar-gen4-cmt1";
452 clock-names = "fck";
453 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
458 cpg: clock-controller@e6150000 {
459 compatible = "renesas,r8a779f0-cpg-mssr";
462 clock-names = "extal", "extalr";
463 #clock-cells = <2>;
464 #power-domain-cells = <0>;
465 #reset-cells = <1>;
468 rst: reset-controller@e6160000 {
469 compatible = "renesas,r8a779f0-rst";
473 sysc: system-controller@e6180000 {
474 compatible = "renesas,r8a779f0-sysc";
476 #power-domain-cells = <1>;
480 compatible = "renesas,r8a779f0-thermal";
486 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
488 #thermal-sensor-cells = <1>;
491 intc_ex: interrupt-controller@e61c0000 {
492 compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc";
493 #interrupt-cells = <2>;
494 interrupt-controller;
503 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
507 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
512 interrupt-names = "tuni0", "tuni1", "tuni2";
514 clock-names = "fck";
515 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
521 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
527 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
529 clock-names = "fck";
530 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
536 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
542 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
544 clock-names = "fck";
545 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
551 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
557 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
559 clock-names = "fck";
560 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
566 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
572 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
574 clock-names = "fck";
575 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
581 compatible = "renesas,r8a779f0-ether-serdes";
584 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
586 #phy-cells = <1>;
591 compatible = "renesas,i2c-r8a779f0",
592 "renesas,rcar-gen4-i2c";
596 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
600 dma-names = "tx", "rx", "tx", "rx";
601 i2c-scl-internal-delay-ns = <110>;
602 #address-cells = <1>;
603 #size-cells = <0>;
608 compatible = "renesas,i2c-r8a779f0",
609 "renesas,rcar-gen4-i2c";
613 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
617 dma-names = "tx", "rx", "tx", "rx";
618 i2c-scl-internal-delay-ns = <110>;
619 #address-cells = <1>;
620 #size-cells = <0>;
625 compatible = "renesas,i2c-r8a779f0",
626 "renesas,rcar-gen4-i2c";
630 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
634 dma-names = "tx", "rx", "tx", "rx";
635 i2c-scl-internal-delay-ns = <110>;
636 #address-cells = <1>;
637 #size-cells = <0>;
642 compatible = "renesas,i2c-r8a779f0",
643 "renesas,rcar-gen4-i2c";
647 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
651 dma-names = "tx", "rx", "tx", "rx";
652 i2c-scl-internal-delay-ns = <110>;
653 #address-cells = <1>;
654 #size-cells = <0>;
659 compatible = "renesas,i2c-r8a779f0",
660 "renesas,rcar-gen4-i2c";
664 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
668 dma-names = "tx", "rx", "tx", "rx";
669 i2c-scl-internal-delay-ns = <110>;
670 #address-cells = <1>;
671 #size-cells = <0>;
676 compatible = "renesas,i2c-r8a779f0",
677 "renesas,rcar-gen4-i2c";
681 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
685 dma-names = "tx", "rx", "tx", "rx";
686 i2c-scl-internal-delay-ns = <110>;
687 #address-cells = <1>;
688 #size-cells = <0>;
693 compatible = "renesas,hscif-r8a779f0",
694 "renesas,rcar-gen4-hscif", "renesas,hscif";
700 clock-names = "fck", "brg_int", "scif_clk";
703 dma-names = "tx", "rx", "tx", "rx";
704 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
710 compatible = "renesas,hscif-r8a779f0",
711 "renesas,rcar-gen4-hscif", "renesas,hscif";
717 clock-names = "fck", "brg_int", "scif_clk";
720 dma-names = "tx", "rx", "tx", "rx";
721 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
727 compatible = "renesas,hscif-r8a779f0",
728 "renesas,rcar-gen4-hscif", "renesas,hscif";
734 clock-names = "fck", "brg_int", "scif_clk";
737 dma-names = "tx", "rx", "tx", "rx";
738 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
744 compatible = "renesas,hscif-r8a779f0",
745 "renesas,rcar-gen4-hscif", "renesas,hscif";
751 clock-names = "fck", "brg_int", "scif_clk";
754 dma-names = "tx", "rx", "tx", "rx";
755 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
761 compatible = "renesas,r8a779f0-pcie",
762 "renesas,rcar-gen4-pcie";
767 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
772 interrupt-names = "msi", "dma", "sft_ce", "app";
774 clock-names = "core", "ref";
775 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
777 reset-names = "pwr";
778 max-link-speed = <4>;
779 num-lanes = <2>;
780 #address-cells = <3>;
781 #size-cells = <2>;
782 bus-range = <0x00 0xff>;
786 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
787 #interrupt-cells = <1>;
788 interrupt-map-mask = <0 0 0 7>;
789 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
793 snps,enable-cdm-check;
798 compatible = "renesas,r8a779f0-pcie",
799 "renesas,rcar-gen4-pcie";
804 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
809 interrupt-names = "msi", "dma", "sft_ce", "app";
811 clock-names = "core", "ref";
812 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
814 reset-names = "pwr";
815 max-link-speed = <4>;
816 num-lanes = <2>;
817 #address-cells = <3>;
818 #size-cells = <2>;
819 bus-range = <0x00 0xff>;
823 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
824 #interrupt-cells = <1>;
825 interrupt-map-mask = <0 0 0 7>;
826 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
830 snps,enable-cdm-check;
834 pciec0_ep: pcie-ep@e65d0000 {
835 compatible = "renesas,r8a779f0-pcie-ep",
836 "renesas,rcar-gen4-pcie-ep";
841 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
845 interrupt-names = "dma", "sft_ce", "app";
847 clock-names = "core", "ref";
848 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
850 reset-names = "pwr";
851 max-link-speed = <4>;
852 num-lanes = <2>;
853 max-functions = /bits/ 8 <2>;
857 pciec1_ep: pcie-ep@e65d8000 {
858 compatible = "renesas,r8a779f0-pcie-ep",
859 "renesas,rcar-gen4-pcie-ep";
864 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
868 interrupt-names = "dma", "sft_ce", "app";
870 clock-names = "core", "ref";
871 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
873 reset-names = "pwr";
874 max-link-speed = <4>;
875 num-lanes = <2>;
876 max-functions = /bits/ 8 <2>;
881 compatible = "renesas,r8a779f0-ufs";
885 clock-names = "fck", "ref_clk";
886 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
887 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
893 compatible = "renesas,r8a779f0-ether-switch";
895 reg-names = "base", "secure_base";
943 interrupt-names = "mfwd_error", "race_error",
969 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
973 ethernet-ports {
974 #address-cells = <1>;
975 #size-cells = <0>;
993 compatible = "renesas,scif-r8a779f0",
994 "renesas,rcar-gen4-scif", "renesas,scif";
1000 clock-names = "fck", "brg_int", "scif_clk";
1003 dma-names = "tx", "rx", "tx", "rx";
1004 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1010 compatible = "renesas,scif-r8a779f0",
1011 "renesas,rcar-gen4-scif", "renesas,scif";
1017 clock-names = "fck", "brg_int", "scif_clk";
1020 dma-names = "tx", "rx", "tx", "rx";
1021 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1027 compatible = "renesas,scif-r8a779f0",
1028 "renesas,rcar-gen4-scif", "renesas,scif";
1034 clock-names = "fck", "brg_int", "scif_clk";
1037 dma-names = "tx", "rx", "tx", "rx";
1038 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1044 compatible = "renesas,scif-r8a779f0",
1045 "renesas,rcar-gen4-scif", "renesas,scif";
1051 clock-names = "fck", "brg_int", "scif_clk";
1054 dma-names = "tx", "rx", "tx", "rx";
1055 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1061 compatible = "renesas,msiof-r8a779f0",
1062 "renesas,rcar-gen4-msiof";
1068 dma-names = "tx", "rx", "tx", "rx";
1069 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1077 compatible = "renesas,msiof-r8a779f0",
1078 "renesas,rcar-gen4-msiof";
1084 dma-names = "tx", "rx", "tx", "rx";
1085 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1093 compatible = "renesas,msiof-r8a779f0",
1094 "renesas,rcar-gen4-msiof";
1100 dma-names = "tx", "rx", "tx", "rx";
1101 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1109 compatible = "renesas,msiof-r8a779f0",
1110 "renesas,rcar-gen4-msiof";
1116 dma-names = "tx", "rx", "tx", "rx";
1117 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1124 dmac0: dma-controller@e7350000 {
1125 compatible = "renesas,dmac-r8a779f0",
1126 "renesas,rcar-gen4-dmac";
1146 interrupt-names = "error",
1152 clock-names = "fck";
1153 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1155 #dma-cells = <1>;
1156 dma-channels = <16>;
1167 dmac1: dma-controller@e7351000 {
1168 compatible = "renesas,dmac-r8a779f0",
1169 "renesas,rcar-gen4-dmac";
1189 interrupt-names = "error",
1195 clock-names = "fck";
1196 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1198 #dma-cells = <1>;
1199 dma-channels = <16>;
1211 compatible = "renesas,sdhi-r8a779f0",
1212 "renesas,rcar-gen4-sdhi";
1216 clock-names = "core", "clkh";
1217 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1219 max-frequency = <200000000>;
1225 compatible = "renesas,ipmmu-r8a779f0",
1226 "renesas,rcar-gen4-ipmmu-vmsa";
1228 renesas,ipmmu-main = <&ipmmu_mm>;
1229 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1230 #iommu-cells = <1>;
1234 compatible = "renesas,ipmmu-r8a779f0",
1235 "renesas,rcar-gen4-ipmmu-vmsa";
1237 renesas,ipmmu-main = <&ipmmu_mm>;
1238 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1239 #iommu-cells = <1>;
1243 compatible = "renesas,ipmmu-r8a779f0",
1244 "renesas,rcar-gen4-ipmmu-vmsa";
1246 renesas,ipmmu-main = <&ipmmu_mm>;
1247 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1248 #iommu-cells = <1>;
1252 compatible = "renesas,ipmmu-r8a779f0",
1253 "renesas,rcar-gen4-ipmmu-vmsa";
1255 renesas,ipmmu-main = <&ipmmu_mm>;
1256 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1257 #iommu-cells = <1>;
1261 compatible = "renesas,ipmmu-r8a779f0",
1262 "renesas,rcar-gen4-ipmmu-vmsa";
1266 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1267 #iommu-cells = <1>;
1270 gic: interrupt-controller@f1000000 {
1271 compatible = "arm,gic-v3";
1272 #interrupt-cells = <3>;
1273 #address-cells = <0>;
1274 interrupt-controller;
1286 thermal-zones {
1287 sensor_thermal_rtcore: sensor1-thermal {
1288 polling-delay-passive = <250>;
1289 polling-delay = <1000>;
1290 thermal-sensors = <&tsc 0>;
1293 sensor1_crit: sensor1-crit {
1301 sensor_thermal_apcore0: sensor2-thermal {
1302 polling-delay-passive = <250>;
1303 polling-delay = <1000>;
1304 thermal-sensors = <&tsc 1>;
1307 sensor2_crit: sensor2-crit {
1315 sensor_thermal_apcore4: sensor3-thermal {
1316 polling-delay-passive = <250>;
1317 polling-delay = <1000>;
1318 thermal-sensors = <&tsc 2>;
1321 sensor3_crit: sensor3-crit {
1331 compatible = "arm,armv8-timer";
1332 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1337 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
1338 "hyp-virt";
1341 ufs30_clk: ufs30-clk {
1342 compatible = "fixed-clock";
1343 #clock-cells = <0>;
1345 clock-frequency = <0>;