Lines Matching +full:0 +full:xe61b0000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
26 #size-cells = <0>;
28 a76_0: cpu@0 {
30 reg = <0>;
37 L3_CA76_0: cache-controller-0 {
47 #clock-cells = <0>;
49 clock-frequency = <0>;
54 #clock-cells = <0>;
56 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
81 reg = <0 0xe6020000 0 0x0c>;
91 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
92 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
93 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
94 <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
95 <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
101 reg = <0 0xe6058180 0 0x54>;
108 gpio-ranges = <&pfc 0 0 28>;
116 reg = <0 0xe6050180 0 0x54>;
123 gpio-ranges = <&pfc 0 32 31>;
131 reg = <0 0xe6050980 0 0x54>;
138 gpio-ranges = <&pfc 0 64 25>;
146 reg = <0 0xe6058980 0 0x54>;
153 gpio-ranges = <&pfc 0 96 17>;
161 reg = <0 0xe6060180 0 0x54>;
168 gpio-ranges = <&pfc 0 128 27>;
176 reg = <0 0xe6060980 0 0x54>;
183 gpio-ranges = <&pfc 0 160 21>;
191 reg = <0 0xe6068180 0 0x54>;
198 gpio-ranges = <&pfc 0 192 21>;
206 reg = <0 0xe6068980 0 0x54>;
213 gpio-ranges = <&pfc 0 224 21>;
221 reg = <0 0xe6069180 0 0x54>;
228 gpio-ranges = <&pfc 0 256 21>;
236 reg = <0 0xe6069980 0 0x54>;
243 gpio-ranges = <&pfc 0 288 21>;
250 reg = <0 0xe6078800 0 0x100>;
259 reg = <0 0xe60f0000 0 0x1004>;
272 reg = <0 0xe6130000 0 0x1004>;
291 reg = <0 0xe6140000 0 0x1004>;
310 reg = <0 0xe6148000 0 0x1004>;
328 reg = <0 0xe6150000 0 0x4000>;
332 #power-domain-cells = <0>;
338 reg = <0 0xe6160000 0 0x4000>;
343 reg = <0 0xe6180000 0 0x4000>;
349 reg = <0 0xe6190000 0 0x200>,
350 <0 0xe6198000 0 0x200>,
351 <0 0xe61a0000 0 0x200>,
352 <0 0xe61a8000 0 0x200>,
353 <0 0xe61b0000 0 0x200>;
364 reg = <0 0xe61c0000 0 0x200>;
365 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
377 reg = <0 0xe61e0000 0 0x30>;
391 reg = <0 0xe6fc0000 0 0x30>;
406 reg = <0 0xe6fd0000 0 0x30>;
421 reg = <0 0xe6fe0000 0 0x30>;
436 reg = <0 0xffc00000 0 0x30>;
452 reg = <0 0xe6500000 0 0x40>;
457 dmas = <&dmac1 0x91>, <&dmac1 0x90>;
461 #size-cells = <0>;
468 reg = <0 0xe6508000 0 0x40>;
473 dmas = <&dmac1 0x93>, <&dmac1 0x92>;
477 #size-cells = <0>;
484 reg = <0 0xe6510000 0 0x40>;
489 dmas = <&dmac1 0x95>, <&dmac1 0x94>;
493 #size-cells = <0>;
500 reg = <0 0xe66d0000 0 0x40>;
505 dmas = <&dmac1 0x97>, <&dmac1 0x96>;
509 #size-cells = <0>;
516 reg = <0 0xe66d8000 0 0x40>;
521 dmas = <&dmac1 0x99>, <&dmac1 0x98>;
525 #size-cells = <0>;
532 reg = <0 0xe66e0000 0 0x40>;
537 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
541 #size-cells = <0>;
548 reg = <0 0xe66e8000 0 0x40>;
553 dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
557 #size-cells = <0>;
564 reg = <0 0xe6540000 0 0x60>;
570 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
580 reg = <0 0xe6550000 0 0x60>;
586 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
596 reg = <0 0xe6560000 0 0x60>;
602 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
612 reg = <0 0xe66a0000 0 0x60>;
618 dmas = <&dmac1 0x37>, <&dmac1 0x36>;
628 reg = <0 0xe6660000 0 0x8000>;
678 reg = <0 0xe6800000 0 0x1000>;
716 rx-internal-delay-ps = <0>;
717 tx-internal-delay-ps = <0>;
718 iommus = <&ipmmu_ds1 0>;
720 #size-cells = <0>;
727 reg = <0 0xe6810000 0 0x1000>;
765 rx-internal-delay-ps = <0>;
766 tx-internal-delay-ps = <0>;
774 reg = <0 0xe6820000 0 0x1000>;
812 rx-internal-delay-ps = <0>;
813 tx-internal-delay-ps = <0>;
821 reg = <0 0xe6830000 0 0x1000>;
859 rx-internal-delay-ps = <0>;
860 tx-internal-delay-ps = <0>;
868 reg = <0 0xe6840000 0 0x1000>;
906 rx-internal-delay-ps = <0>;
907 tx-internal-delay-ps = <0>;
915 reg = <0 0xe6850000 0 0x1000>;
953 rx-internal-delay-ps = <0>;
954 tx-internal-delay-ps = <0>;
961 reg = <0 0xe6e30000 0 0x10>;
971 reg = <0 0xe6e31000 0 0x10>;
981 reg = <0 0xe6e32000 0 0x10>;
991 reg = <0 0xe6e33000 0 0x10>;
1001 reg = <0 0xe6e34000 0 0x10>;
1012 reg = <0 0xe6e60000 0 64>;
1018 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
1028 reg = <0 0xe6e68000 0 64>;
1034 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
1044 reg = <0 0xe6c50000 0 64>;
1050 dmas = <&dmac1 0x57>, <&dmac1 0x56>;
1060 reg = <0 0xe6c40000 0 64>;
1066 dmas = <&dmac1 0x59>, <&dmac1 0x58>;
1075 reg = <0 0xe6e80000 0 0x148>;
1087 reg = <0 0xe6e90000 0 0x0064>;
1092 dmas = <&dmac1 0x41>, <&dmac1 0x40>;
1095 #size-cells = <0>;
1102 reg = <0 0xe6ea0000 0 0x0064>;
1107 dmas = <&dmac1 0x43>, <&dmac1 0x42>;
1110 #size-cells = <0>;
1117 reg = <0 0xe6c00000 0 0x0064>;
1122 dmas = <&dmac1 0x45>, <&dmac1 0x44>;
1125 #size-cells = <0>;
1132 reg = <0 0xe6c10000 0 0x0064>;
1137 dmas = <&dmac1 0x47>, <&dmac1 0x46>;
1140 #size-cells = <0>;
1147 reg = <0 0xe6c20000 0 0x0064>;
1152 dmas = <&dmac1 0x49>, <&dmac1 0x48>;
1155 #size-cells = <0>;
1162 reg = <0 0xe6c28000 0 0x0064>;
1167 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
1170 #size-cells = <0>;
1177 reg = <0 0xe6ef0000 0 0x1000>;
1182 renesas,id = <0>;
1187 #size-cells = <0>;
1191 #size-cells = <0>;
1195 vin00isp0: endpoint@0 {
1196 reg = <0>;
1206 reg = <0 0xe6ef1000 0 0x1000>;
1216 #size-cells = <0>;
1220 #size-cells = <0>;
1224 vin01isp0: endpoint@0 {
1225 reg = <0>;
1235 reg = <0 0xe6ef2000 0 0x1000>;
1245 #size-cells = <0>;
1249 #size-cells = <0>;
1253 vin02isp0: endpoint@0 {
1254 reg = <0>;
1264 reg = <0 0xe6ef3000 0 0x1000>;
1274 #size-cells = <0>;
1278 #size-cells = <0>;
1282 vin03isp0: endpoint@0 {
1283 reg = <0>;
1293 reg = <0 0xe6ef4000 0 0x1000>;
1303 #size-cells = <0>;
1307 #size-cells = <0>;
1311 vin04isp0: endpoint@0 {
1312 reg = <0>;
1322 reg = <0 0xe6ef5000 0 0x1000>;
1332 #size-cells = <0>;
1336 #size-cells = <0>;
1340 vin05isp0: endpoint@0 {
1341 reg = <0>;
1351 reg = <0 0xe6ef6000 0 0x1000>;
1361 #size-cells = <0>;
1365 #size-cells = <0>;
1369 vin06isp0: endpoint@0 {
1370 reg = <0>;
1380 reg = <0 0xe6ef7000 0 0x1000>;
1390 #size-cells = <0>;
1394 #size-cells = <0>;
1398 vin07isp0: endpoint@0 {
1399 reg = <0>;
1409 reg = <0 0xe6ef8000 0 0x1000>;
1419 #size-cells = <0>;
1423 #size-cells = <0>;
1438 reg = <0 0xe6ef9000 0 0x1000>;
1448 #size-cells = <0>;
1452 #size-cells = <0>;
1467 reg = <0 0xe6efa000 0 0x1000>;
1477 #size-cells = <0>;
1481 #size-cells = <0>;
1496 reg = <0 0xe6efb000 0 0x1000>;
1506 #size-cells = <0>;
1510 #size-cells = <0>;
1525 reg = <0 0xe6efc000 0 0x1000>;
1535 #size-cells = <0>;
1539 #size-cells = <0>;
1554 reg = <0 0xe6efd000 0 0x1000>;
1564 #size-cells = <0>;
1568 #size-cells = <0>;
1583 reg = <0 0xe6efe000 0 0x1000>;
1593 #size-cells = <0>;
1597 #size-cells = <0>;
1612 reg = <0 0xe6eff000 0 0x1000>;
1622 #size-cells = <0>;
1626 #size-cells = <0>;
1641 reg = <0 0xe6ed0000 0 0x1000>;
1651 #size-cells = <0>;
1655 #size-cells = <0>;
1670 reg = <0 0xe6ed1000 0 0x1000>;
1680 #size-cells = <0>;
1684 #size-cells = <0>;
1699 reg = <0 0xe6ed2000 0 0x1000>;
1709 #size-cells = <0>;
1713 #size-cells = <0>;
1728 reg = <0 0xe6ed3000 0 0x1000>;
1738 #size-cells = <0>;
1742 #size-cells = <0>;
1757 reg = <0 0xe6ed4000 0 0x1000>;
1767 #size-cells = <0>;
1771 #size-cells = <0>;
1786 reg = <0 0xe6ed5000 0 0x1000>;
1796 #size-cells = <0>;
1800 #size-cells = <0>;
1815 reg = <0 0xe6ed6000 0 0x1000>;
1825 #size-cells = <0>;
1829 #size-cells = <0>;
1844 reg = <0 0xe6ed7000 0 0x1000>;
1854 #size-cells = <0>;
1858 #size-cells = <0>;
1873 reg = <0 0xe6ed8000 0 0x1000>;
1883 #size-cells = <0>;
1887 #size-cells = <0>;
1902 reg = <0 0xe6ed9000 0 0x1000>;
1912 #size-cells = <0>;
1916 #size-cells = <0>;
1931 reg = <0 0xe6eda000 0 0x1000>;
1941 #size-cells = <0>;
1945 #size-cells = <0>;
1960 reg = <0 0xe6edb000 0 0x1000>;
1970 #size-cells = <0>;
1974 #size-cells = <0>;
1989 reg = <0 0xe6edc000 0 0x1000>;
1999 #size-cells = <0>;
2003 #size-cells = <0>;
2018 reg = <0 0xe6edd000 0 0x1000>;
2028 #size-cells = <0>;
2032 #size-cells = <0>;
2047 reg = <0 0xe6ede000 0 0x1000>;
2057 #size-cells = <0>;
2061 #size-cells = <0>;
2076 reg = <0 0xe6edf000 0 0x1000>;
2086 #size-cells = <0>;
2090 #size-cells = <0>;
2105 reg = <0 0xe7350000 0 0x1000>,
2106 <0 0xe7300000 0 0x10000>;
2135 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
2148 reg = <0 0xe7351000 0 0x1000>,
2149 <0 0xe7310000 0 0x10000>;
2177 reg = <0 0xee140000 0 0x2000>;
2191 reg = <0 0xee200000 0 0x200>,
2192 <0 0x08000000 0 0x04000000>,
2193 <0 0xee208000 0 0x100>;
2200 #size-cells = <0>;
2207 reg = <0 0xee480000 0 0x20000>;
2216 reg = <0 0xee4c0000 0 0x20000>;
2225 reg = <0 0xeed00000 0 0x20000>;
2234 reg = <0 0xeed40000 0 0x20000>;
2243 reg = <0 0xeed80000 0 0x20000>;
2252 reg = <0 0xeedc0000 0 0x20000>;
2261 reg = <0 0xeee80000 0 0x20000>;
2270 reg = <0 0xeeec0000 0 0x20000>;
2279 reg = <0 0xeee00000 0 0x20000>;
2288 reg = <0 0xeef00000 0 0x20000>;
2297 reg = <0 0xeef40000 0 0x20000>;
2306 reg = <0 0xeefc0000 0 0x20000>;
2316 #address-cells = <0>;
2318 reg = <0x0 0xf1000000 0 0x20000>,
2319 <0x0 0xf1060000 0 0x110000>;
2325 reg = <0 0xfea10000 0 0x200>;
2334 reg = <0 0xfea11000 0 0x200>;
2343 reg = <0 0xfea20000 0 0x5000>;
2354 reg = <0 0xfea28000 0 0x5000>;
2365 reg = <0 0xfeaa0000 0 0x10000>;
2374 #size-cells = <0>;
2376 port@0 {
2377 reg = <0>;
2391 reg = <0 0xfeab0000 0 0x10000>;
2400 #size-cells = <0>;
2402 port@0 {
2403 reg = <0>;
2417 reg = <0 0xfed60000 0 0x10000>;
2426 #size-cells = <0>;
2428 port@0 {
2429 reg = <0>;
2443 reg = <0 0xfed70000 0 0x10000>;
2452 #size-cells = <0>;
2454 port@0 {
2455 reg = <0>;
2469 reg = <0 0xfeb00000 0 0x40000>;
2473 clock-names = "du.0";
2476 reset-names = "du.0";
2477 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2483 #size-cells = <0>;
2485 port@0 {
2486 reg = <0>;
2504 reg = <0 0xfed00000 0 0x10000>;
2513 #size-cells = <0>;
2515 port@0 {
2517 #size-cells = <0>;
2519 reg = <0>;
2521 isp0csi40: endpoint@0 {
2522 reg = <0>;
2588 reg = <0 0xfed20000 0 0x10000>;
2597 #size-cells = <0>;
2599 port@0 {
2601 #size-cells = <0>;
2603 reg = <0>;
2672 reg = <0 0xfed30000 0 0x10000>;
2681 #size-cells = <0>;
2683 port@0 {
2685 #size-cells = <0>;
2687 reg = <0>;
2689 isp2csi42: endpoint@0 {
2690 reg = <0>;
2756 reg = <0 0xfed40000 0 0x10000>;
2765 #size-cells = <0>;
2767 port@0 {
2769 #size-cells = <0>;
2771 reg = <0>;
2839 reg = <0 0xfed80000 0 0x10000>;
2850 #size-cells = <0>;
2852 port@0 {
2853 reg = <0>;
2867 reg = <0 0xfed90000 0 0x10000>;
2878 #size-cells = <0>;
2880 port@0 {
2881 reg = <0>;
2895 reg = <0 0xfff00044 0 4>;
2903 thermal-sensors = <&tsc 0>;