Lines Matching +full:0 +full:x080000

36 	d3_3v: regulator-0 {
62 			#size-cells = <0>;
64 			port@0 {
65 				reg = <0>;
83 		reg = <0 0x48000000 0 0x78000000>;
97 		#clock-cells = <0>;
103 	pinctrl-0 = <&canfd0_pins>;
116 		port@0 {
118 				clock-lanes = <0>;
130 		port@0 {
132 				clock-lanes = <0>;
143 	clock-names = "du.0", "dclkin.0";
156 	pinctrl-0 = <&gether_pins>;
164 	phy0: ethernet-phy@0 {
168 		reg = <0>;
175 	pinctrl-0 = <&i2c0_pins>;
183 		reg = <0x20>;
190 		reg = <0x21>;
197 		reg = <0x39>;
211 			#size-cells = <0>;
213 			port@0 {
214 				reg = <0>;
231 		reg = <0x50>;
237 	pinctrl-0 = <&i2c1_pins>;
245 		reg = <0x48>;
247 		maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
248 		enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
252 			#size-cells = <0>;
254 			port@0 {
255 				reg = <0>;
273 					clock-lanes = <0>;
282 			#size-cells = <0>;
284 			i2c@0 {
286 				#size-cells = <0>;
287 				reg = <0>;
294 				#size-cells = <0>;
302 				#size-cells = <0>;
310 				#size-cells = <0>;
320 		reg = <0x4a>;
322 		maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
323 		enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
327 			#size-cells = <0>;
329 			port@0 {
330 				reg = <0>;
348 					clock-lanes = <0>;
357 			#size-cells = <0>;
359 			i2c@0 {
361 				#size-cells = <0>;
362 				reg = <0>;
369 				#size-cells = <0>;
377 				#size-cells = <0>;
385 				#size-cells = <0>;
407 	pinctrl-0 = <&mmc_pins>;
478 	pinctrl-0 = <&qspi0_pins>;
483 	flash@0 {
485 		reg = <0>;
494 			bootparam@0 {
495 				reg = <0x00000000 0x040000>;
499 				reg = <0x00040000 0x080000>;
503 				reg = <0x000c0000 0x080000>;
507 				reg = <0x00140000 0x040000>;
511 				reg = <0x00180000 0x040000>;
515 				reg = <0x001c0000 0x460000>;
519 				reg = <0x00640000 0x0c0000>;
523 				reg = <0x00700000 0x040000>;
527 				reg = <0x00740000 0x080000>;
530 				reg = <0x007c0000 0x1400000>;
533 				reg = <0x01bc0000 0x2440000>;
545 	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;