Lines Matching +full:1 +full:c08000
50 clock-mult = <1>;
59 clock-mult = <1>;
296 cluster_cl5: cluster-sleep-1 {
333 mc_virt: interconnect-1 {
736 #qcom,smem-state-cells = <1>;
762 #qcom,smem-state-cells = <1>;
796 #clock-cells = <1>;
797 #reset-cells = <1>;
798 #power-domain-cells = <1>;
878 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
885 #address-cells = <1>;
914 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
921 #address-cells = <1>;
949 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
950 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
957 #address-cells = <1>;
985 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
986 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
993 #address-cells = <1>;
1022 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1029 #address-cells = <1>;
1058 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1065 #address-cells = <1>;
1094 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1101 #address-cells = <1>;
1130 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1137 #address-cells = <1>;
1166 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1173 #address-cells = <1>;
1202 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1209 #address-cells = <1>;
1238 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1245 #address-cells = <1>;
1274 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1281 #address-cells = <1>;
1335 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1342 #address-cells = <1>;
1371 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1378 #address-cells = <1>;
1407 <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1414 #address-cells = <1>;
1443 <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1450 #address-cells = <1>;
1523 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1530 #address-cells = <1>;
1559 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1566 #address-cells = <1>;
1594 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1595 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1602 #address-cells = <1>;
1630 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1631 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1638 #address-cells = <1>;
1667 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1674 #address-cells = <1>;
1703 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1710 #address-cells = <1>;
1739 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1746 #address-cells = <1>;
1775 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1782 #address-cells = <1>;
1811 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1818 #address-cells = <1>;
1847 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1854 #address-cells = <1>;
1883 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1890 #address-cells = <1>;
1919 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1926 #address-cells = <1>;
1955 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1962 #address-cells = <1>;
1991 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1998 #address-cells = <1>;
2052 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2059 #address-cells = <1>;
2088 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2095 #address-cells = <1>;
2167 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2174 #address-cells = <1>;
2203 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2210 #address-cells = <1>;
2238 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2239 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
2246 #address-cells = <1>;
2274 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2275 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
2282 #address-cells = <1>;
2311 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
2318 #address-cells = <1>;
2372 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
2379 #address-cells = <1>;
2408 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
2415 #address-cells = <1>;
2444 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
2451 #address-cells = <1>;
2480 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
2487 #address-cells = <1>;
2516 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
2523 #address-cells = <1>;
2552 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
2559 #address-cells = <1>;
2588 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
2595 #address-cells = <1>;
2624 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
2631 #address-cells = <1>;
2660 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
2667 #address-cells = <1>;
2696 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
2703 #address-cells = <1>;
2732 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
2739 #address-cells = <1>;
2758 #thermal-sensor-cells = <1>;
2773 #thermal-sensor-cells = <1>;
2788 #thermal-sensor-cells = <1>;
2803 #thermal-sensor-cells = <1>;
2840 #clock-cells = <1>;
2841 #phy-cells = <1>;
2848 #address-cells = <1>;
2858 port@1 {
2859 reg = <1>;
2910 #clock-cells = <1>;
2911 #phy-cells = <1>;
2918 #address-cells = <1>;
2928 port@1 {
2929 reg = <1>;
2980 #clock-cells = <1>;
2981 #phy-cells = <1>;
2988 #address-cells = <1>;
2998 port@1 {
2999 reg = <1>;
3124 pcie3: pcie@1bd0000 {
3170 #interrupt-cells = <1>;
3172 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
3219 /* GEN 1 x1 */
3223 opp-peak-kBps = <250000 1>;
3226 /* GEN 1 x2 and GEN 2 x1 */
3230 opp-peak-kBps = <500000 1>;
3233 /* GEN 1 x4 and GEN 2 x2 */
3237 opp-peak-kBps = <1000000 1>;
3240 /* GEN 1 x8 and GEN 2 x4 */
3244 opp-peak-kBps = <2000000 1>;
3251 opp-peak-kBps = <4000000 1>;
3258 opp-peak-kBps = <984500 1>;
3265 opp-peak-kBps = <1969000 1>;
3272 opp-peak-kBps = <3938000 1>;
3279 opp-peak-kBps = <7876000 1>;
3286 opp-peak-kBps = <15753000 1>;
3291 pcie3_phy: phy@1be0000 {
3326 pcie6a: pci@1bf8000 {
3371 #interrupt-cells = <1>;
3373 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
3417 pcie6a_phy: phy@1bfc000 {
3455 pcie5: pci@1c00000 {
3498 #interrupt-cells = <1>;
3500 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3544 pcie5_phy: phy@1c06000 {
3577 pcie4: pci@1c08000 {
3622 #interrupt-cells = <1>;
3624 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3678 pcie4_phy: phy@1c0e000 {
3711 tcsr_mutex: hwlock@1f40000 {
3714 #hwlock-cells = <1>;
3717 tcsr: clock-controller@1fc0000 {
3721 #clock-cells = <1>;
3722 #reset-cells = <1>;
3738 <&adreno_smmu 1 0x0>;
3814 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3871 #clock-cells = <1>;
3872 #reset-cells = <1>;
3873 #power-domain-cells = <1>;
3881 #global-interrupts = <1>;
3944 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3989 #address-cells = <1>;
4038 #address-cells = <1>;
4041 q6apm: service@1 {
4050 #sound-dai-cells = <1>;
4089 #sound-dai-cells = <1>;
4121 #sound-dai-cells = <1>;
4139 #sound-dai-cells = <1>;
4155 qcom,din-ports = <1>;
4170 #sound-dai-cells = <1>;
4188 #sound-dai-cells = <1>;
4205 #sound-dai-cells = <1>;
4237 #sound-dai-cells = <1>;
4244 #clock-cells = <1>;
4245 #reset-cells = <1>;
4264 qcom,dout-ports = <1>;
4278 #sound-dai-cells = <1>;
4294 #sound-dai-cells = <1>;
4315 slew-rate = <1>;
4323 slew-rate = <1>;
4333 slew-rate = <1>;
4341 slew-rate = <1>;
4383 slew-rate = <1>;
4391 slew-rate = <1>;
4401 slew-rate = <1>;
4409 slew-rate = <1>;
4418 #clock-cells = <1>;
4419 #reset-cells = <1>;
4732 #address-cells = <1>;
4742 port@1 {
4743 reg = <1>;
4818 #address-cells = <1>;
4906 "usb2-1", "usb3-1";
4991 #address-cells = <1>;
5001 port@1 {
5002 reg = <1>;
5091 #address-cells = <1>;
5101 port@1 {
5102 reg = <1>;
5140 #interrupt-cells = <1>;
5173 #address-cells = <1>;
5277 #address-cells = <1>;
5288 port@1 {
5289 reg = <1>;
5360 #address-cells = <1>;
5371 port@1 {
5372 reg = <1>;
5443 #address-cells = <1>;
5453 port@1 {
5454 reg = <1>;
5511 <&mdss_dp3_phy 1>;
5525 #address-cells = <1>;
5536 port@1 {
5537 reg = <1>;
5582 #clock-cells = <1>;
5602 #clock-cells = <1>;
5626 <&mdss_dp3_phy 1>;
5629 #clock-cells = <1>;
5630 #reset-cells = <1>;
5631 #power-domain-cells = <1>;
5682 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
6434 #address-cells = <1>;
6445 port@1 {
6446 reg = <1>;
6490 #address-cells = <1>;
6527 #address-cells = <1>;
6572 #address-cells = <1>;
6583 port@1 {
6584 reg = <1>;
6776 #address-cells = <1>;
6837 #address-cells = <1>;
6930 #address-cells = <1>;
6941 port@1 {
6942 reg = <1>;
7148 tpdm@10c08000 {
7175 #address-cells = <1>;
7242 #address-cells = <1>;
7277 port@1a {
7285 port@1b {
7311 #address-cells = <1>;
7394 #address-cells = <1>;
7493 #address-cells = <1>;
7546 #address-cells = <1>;
7727 #address-cells = <1>;
7738 port@1 {
7739 reg = <1>;
7931 #global-interrupts = <1>;
7946 #redistributor-regions = <1>;
7958 #msi-cells = <1>;
7967 reg-names = "drv-0", "drv-1", "drv-2";
7990 #clock-cells = <1>;
7998 #power-domain-cells = <1>;
8071 #size-cells = <1>;
8089 frame-number = <1>;
8163 opp-1 {
8220 opp-1 {
8299 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
8346 #address-cells = <1>;
8349 compute-cb@1 {
8351 reg = <1>;
8470 thermal-sensors = <&tsens0 1>;
8519 cpu0-1-top-thermal {
8545 cpu0-1-btm-thermal {
8764 thermal-sensors = <&tsens1 1>;
8813 cpu1-1-top-thermal {
8839 cpu1-1-btm-thermal {
9026 thermal-sensors = <&tsens2 1>;
9075 cpu2-1-top-thermal {
9101 cpu2-1-btm-thermal {
9286 thermal-sensors = <&tsens3 1>;
9383 gpuss-1-thermal {