Lines Matching +full:domain +full:- +full:idle +full:- +full:state
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8750-gcc.h>
8 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 interrupt-parent = <&intc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 #address-cells = <2>;
25 #size-cells = <0>;
31 enable-method = "psci";
32 next-level-cache = <&l2_0>;
33 power-domains = <&cpu_pd0>;
34 power-domain-names = "psci";
36 l2_0: l2-cache {
38 cache-level = <2>;
39 cache-unified;
47 enable-method = "psci";
48 next-level-cache = <&l2_0>;
49 power-domains = <&cpu_pd1>;
50 power-domain-names = "psci";
57 enable-method = "psci";
58 next-level-cache = <&l2_0>;
59 power-domains = <&cpu_pd2>;
60 power-domain-names = "psci";
67 enable-method = "psci";
68 next-level-cache = <&l2_0>;
69 power-domains = <&cpu_pd3>;
70 power-domain-names = "psci";
77 enable-method = "psci";
78 next-level-cache = <&l2_0>;
79 power-domains = <&cpu_pd4>;
80 power-domain-names = "psci";
87 enable-method = "psci";
88 next-level-cache = <&l2_0>;
89 power-domains = <&cpu_pd5>;
90 power-domain-names = "psci";
97 enable-method = "psci";
98 next-level-cache = <&L2_1>;
99 power-domains = <&cpu_pd6>;
100 power-domain-names = "psci";
102 L2_1: l2-cache {
104 cache-level = <2>;
105 cache-unified;
113 enable-method = "psci";
114 next-level-cache = <&L2_1>;
115 power-domains = <&cpu_pd7>;
116 power-domain-names = "psci";
119 cpu-map {
157 idle-states {
158 entry-method = "psci";
160 cluster0_c4: cpu-sleep-0 {
161 compatible = "arm,idle-state";
162 idle-state-name = "ret";
163 arm,psci-suspend-param = <0x00000004>;
164 entry-latency-us = <93>;
165 exit-latency-us = <129>;
166 min-residency-us = <560>;
169 cluster1_c4: cpu-sleep-1 {
170 compatible = "arm,idle-state";
171 idle-state-name = "ret";
172 arm,psci-suspend-param = <0x00000004>;
173 entry-latency-us = <172>;
174 exit-latency-us = <130>;
175 min-residency-us = <686>;
180 domain-idle-states {
181 cluster_cl5: cluster-sleep-0 {
182 compatible = "domain-idle-state";
183 arm,psci-suspend-param = <0x01000054>;
184 entry-latency-us = <2150>;
185 exit-latency-us = <1983>;
186 min-residency-us = <9144>;
189 domain_ss3: domain-sleep-0 {
190 compatible = "domain-idle-state";
191 arm,psci-suspend-param = <0x0200c354>;
192 entry-latency-us = <2800>;
193 exit-latency-us = <4400>;
194 min-residency-us = <10150>;
201 compatible = "qcom,scm-sm8750", "qcom,scm";
207 clk_virt: interconnect-0 {
208 compatible = "qcom,sm8750-clk-virt";
209 #interconnect-cells = <2>;
210 qcom,bcm-voters = <&apps_bcm_voter>;
213 mc_virt: interconnect-1 {
214 compatible = "qcom,sm8750-mc-virt";
215 #interconnect-cells = <2>;
216 qcom,bcm-voters = <&apps_bcm_voter>;
226 compatible = "arm,armv8-pmuv3";
231 compatible = "arm,psci-1.0";
234 cpu_pd0: power-domain-cpu0 {
235 #power-domain-cells = <0>;
236 power-domains = <&cluster_pd>;
237 domain-idle-states = <&cluster0_c4>;
240 cpu_pd1: power-domain-cpu1 {
241 #power-domain-cells = <0>;
242 power-domains = <&cluster_pd>;
243 domain-idle-states = <&cluster0_c4>;
246 cpu_pd2: power-domain-cpu2 {
247 #power-domain-cells = <0>;
248 power-domains = <&cluster_pd>;
249 domain-idle-states = <&cluster0_c4>;
252 cpu_pd3: power-domain-cpu3 {
253 #power-domain-cells = <0>;
254 power-domains = <&cluster_pd>;
255 domain-idle-states = <&cluster0_c4>;
258 cpu_pd4: power-domain-cpu4 {
259 #power-domain-cells = <0>;
260 power-domains = <&cluster_pd>;
261 domain-idle-states = <&cluster0_c4>;
264 cpu_pd5: power-domain-cpu5 {
265 #power-domain-cells = <0>;
266 power-domains = <&cluster_pd>;
267 domain-idle-states = <&cluster0_c4>;
270 cpu_pd6: power-domain-cpu6 {
271 #power-domain-cells = <0>;
272 power-domains = <&cluster_pd>;
273 domain-idle-states = <&cluster1_c4>;
276 cpu_pd7: power-domain-cpu7 {
277 #power-domain-cells = <0>;
278 power-domains = <&cluster_pd>;
279 domain-idle-states = <&cluster1_c4>;
282 cluster_pd: power-domain-cluster {
283 #power-domain-cells = <0>;
284 domain-idle-states = <&cluster_cl5>;
285 power-domains = <&system_pd>;
288 system_pd: power-domain-system {
289 #power-domain-cells = <0>;
290 domain-idle-states = <&domain_ss3>;
294 reserved-memory {
295 #address-cells = <2>;
296 #size-cells = <2>;
299 gunyah_hyp_mem: gunyah-hyp@80000000 {
301 no-map;
304 cpusys_vm_mem: cpusys-vm-mem@80e00000 {
306 no-map;
311 no-map;
314 xbl_dtlog_mem: xbl-dtlog@81a00000 {
316 no-map;
319 aop_image_mem: aop-image@81c00000 {
321 no-map;
324 aop_cmd_db_mem: aop-cmd-db@81c60000 {
325 compatible = "qcom,cmd-db";
327 no-map;
331 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
333 no-map;
342 no-map;
345 pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
347 no-map;
350 cpucp_scandump_mem: cpucp-scandump@82000000 {
352 no-map;
355 adsp_mhi_mem: adsp-mhi@82380000 {
357 no-map;
360 soccp_sdi_mem: soccp-sdi@823a0000 {
362 no-map;
365 pmic_minii_dump_mem: pmic-minii-dump@823e0000 {
367 no-map;
372 no-map;
375 global_sync_mem: global-sync@82600000 {
377 no-map;
380 tz_stat_mem: tz-stat@82700000 {
382 no-map;
387 no-map;
390 dsm_partition_1_mem: dsm-partition-1@84a00000 {
392 no-map;
395 dsm_partition_2_mem: dsm-partition-2@89300000 {
397 no-map;
402 no-map;
405 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
407 no-map;
410 ipa_fw_mem: ipa-fw@9b080000 {
412 no-map;
415 ipa_gsi_mem: ipa-gsi@9b090000 {
417 no-map;
420 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
422 no-map;
427 no-map;
431 spu_tz_shared_mem: spu-tz-shared@9b280000 {
433 no-map;
437 spu_modem_shared_mem: spu-modem-shared@9b2c0000 {
439 no-map;
444 no-map;
447 camera_2_mem: camera-2@9bb00000 {
449 no-map;
454 no-map;
459 no-map;
464 no-map;
467 q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 {
469 no-map;
474 no-map;
477 q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 {
479 no-map;
484 no-map;
487 xbl_ramdump_mem: xbl-ramdump@b8000000 {
489 no-map;
492 hwfence_shbuf: hwfence-shbuf@d4e23000 {
493 no-map;
498 tz_merged_mem: tz-merged@d8000000 {
500 no-map;
503 trust_ui_vm_mem: trust-ui-vm@f3800000 {
505 no-map;
508 oem_vm_mem: oem-vm@f7c00000 {
510 no-map;
513 llcc_lpi_mem: llcc-lpi@ff800000 {
515 no-map;
520 compatible = "simple-bus";
522 #address-cells = <2>;
523 #size-cells = <2>;
524 dma-ranges = <0 0 0 0 0x10 0>;
527 gcc: clock-controller@100000 {
528 compatible = "qcom,sm8750-gcc";
540 #clock-cells = <1>;
541 #reset-cells = <1>;
542 #power-domain-cells = <1>;
545 gpi_dma2: dma-controller@800000 {
546 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
562 dma-channels = <12>;
563 dma-channel-mask = <0x1e>;
564 #dma-cells = <3>;
572 compatible = "qcom,geni-se-qup";
577 clock-names = "m-ahb",
578 "s-ahb";
582 #address-cells = <2>;
583 #size-cells = <2>;
589 compatible = "qcom,geni-i2c";
595 clock-names = "se";
603 interconnect-names = "qup-core",
604 "qup-config",
605 "qup-memory";
609 dma-names = "tx",
612 pinctrl-0 = <&qup_i2c8_data_clk>;
613 pinctrl-names = "default";
615 #address-cells = <1>;
616 #size-cells = <0>;
622 compatible = "qcom,geni-spi";
628 clock-names = "se";
636 interconnect-names = "qup-core",
637 "qup-config",
638 "qup-memory";
642 dma-names = "tx",
645 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
646 pinctrl-names = "default";
648 #address-cells = <1>;
649 #size-cells = <0>;
655 compatible = "qcom,geni-i2c";
661 clock-names = "se";
669 interconnect-names = "qup-core",
670 "qup-config",
671 "qup-memory";
675 dma-names = "tx",
678 pinctrl-0 = <&qup_i2c9_data_clk>;
679 pinctrl-names = "default";
681 #address-cells = <1>;
682 #size-cells = <0>;
688 compatible = "qcom,geni-spi";
694 clock-names = "se";
702 interconnect-names = "qup-core",
703 "qup-config",
704 "qup-memory";
708 dma-names = "tx",
711 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
712 pinctrl-names = "default";
714 #address-cells = <1>;
715 #size-cells = <0>;
721 compatible = "qcom,geni-i2c";
727 clock-names = "se";
735 interconnect-names = "qup-core",
736 "qup-config",
737 "qup-memory";
741 dma-names = "tx",
744 pinctrl-0 = <&qup_i2c10_data_clk>;
745 pinctrl-names = "default";
747 #address-cells = <1>;
748 #size-cells = <0>;
754 compatible = "qcom,geni-spi";
760 clock-names = "se";
768 interconnect-names = "qup-core",
769 "qup-config",
770 "qup-memory";
774 dma-names = "tx",
777 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
778 pinctrl-names = "default";
780 #address-cells = <1>;
781 #size-cells = <0>;
787 compatible = "qcom,geni-i2c";
793 clock-names = "se";
801 interconnect-names = "qup-core",
802 "qup-config",
803 "qup-memory";
807 dma-names = "tx",
810 pinctrl-0 = <&qup_i2c11_data_clk>;
811 pinctrl-names = "default";
813 #address-cells = <1>;
814 #size-cells = <0>;
820 compatible = "qcom,geni-spi";
826 clock-names = "se";
834 interconnect-names = "qup-core",
835 "qup-config",
836 "qup-memory";
840 dma-names = "tx",
843 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
844 pinctrl-names = "default";
846 #address-cells = <1>;
847 #size-cells = <0>;
853 compatible = "qcom,geni-i2c";
859 clock-names = "se";
867 interconnect-names = "qup-core",
868 "qup-config",
869 "qup-memory";
873 dma-names = "tx",
876 pinctrl-0 = <&qup_i2c12_data_clk>;
877 pinctrl-names = "default";
879 #address-cells = <1>;
880 #size-cells = <0>;
886 compatible = "qcom,geni-spi";
892 clock-names = "se";
900 interconnect-names = "qup-core",
901 "qup-config",
902 "qup-memory";
906 dma-names = "tx",
909 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
910 pinctrl-names = "default";
912 #address-cells = <1>;
913 #size-cells = <0>;
919 compatible = "qcom,geni-i2c";
925 clock-names = "se";
933 interconnect-names = "qup-core",
934 "qup-config",
935 "qup-memory";
939 dma-names = "tx",
942 pinctrl-0 = <&qup_i2c13_data_clk>;
943 pinctrl-names = "default";
945 #address-cells = <1>;
946 #size-cells = <0>;
952 compatible = "qcom,geni-spi";
958 clock-names = "se";
966 interconnect-names = "qup-core",
967 "qup-config",
968 "qup-memory";
972 dma-names = "tx",
975 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
976 pinctrl-names = "default";
978 #address-cells = <1>;
979 #size-cells = <0>;
985 compatible = "qcom,geni-uart";
991 clock-names = "se";
997 interconnect-names = "qup-core",
998 "qup-config";
1000 pinctrl-0 = <&qup_uart14_default>;
1001 pinctrl-names = "default";
1007 compatible = "qcom,geni-i2c";
1013 clock-names = "se";
1021 interconnect-names = "qup-core",
1022 "qup-config",
1023 "qup-memory";
1027 dma-names = "tx",
1030 pinctrl-0 = <&qup_i2c15_data_clk>;
1031 pinctrl-names = "default";
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1040 compatible = "qcom,geni-spi";
1046 clock-names = "se";
1054 interconnect-names = "qup-core",
1055 "qup-config",
1056 "qup-memory";
1060 dma-names = "tx",
1063 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1064 pinctrl-names = "default";
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1074 compatible = "qcom,geni-se-i2c-master-hub";
1078 clock-names = "s-ahb";
1080 #address-cells = <2>;
1081 #size-cells = <2>;
1087 compatible = "qcom,geni-i2c-master-hub";
1094 clock-names = "se",
1101 interconnect-names = "qup-core",
1102 "qup-config";
1104 pinctrl-0 = <&hub_i2c0_data_clk>;
1105 pinctrl-names = "default";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1114 compatible = "qcom,geni-i2c-master-hub";
1121 clock-names = "se",
1128 interconnect-names = "qup-core",
1129 "qup-config";
1131 pinctrl-0 = <&hub_i2c1_data_clk>;
1132 pinctrl-names = "default";
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1141 compatible = "qcom,geni-i2c-master-hub";
1148 clock-names = "se",
1155 interconnect-names = "qup-core",
1156 "qup-config";
1158 pinctrl-0 = <&hub_i2c2_data_clk>;
1159 pinctrl-names = "default";
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1168 compatible = "qcom,geni-i2c-master-hub";
1175 clock-names = "se",
1182 interconnect-names = "qup-core",
1183 "qup-config";
1185 pinctrl-0 = <&hub_i2c3_data_clk>;
1186 pinctrl-names = "default";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1195 compatible = "qcom,geni-i2c-master-hub";
1202 clock-names = "se",
1209 interconnect-names = "qup-core",
1210 "qup-config";
1212 pinctrl-0 = <&hub_i2c4_data_clk>;
1213 pinctrl-names = "default";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1222 compatible = "qcom,geni-i2c-master-hub";
1229 clock-names = "se",
1236 interconnect-names = "qup-core",
1237 "qup-config";
1239 pinctrl-0 = <&hub_i2c5_data_clk>;
1240 pinctrl-names = "default";
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1249 compatible = "qcom,geni-i2c-master-hub";
1256 clock-names = "se",
1263 interconnect-names = "qup-core",
1264 "qup-config";
1266 pinctrl-0 = <&hub_i2c6_data_clk>;
1267 pinctrl-names = "default";
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1276 compatible = "qcom,geni-i2c-master-hub";
1283 clock-names = "se",
1290 interconnect-names = "qup-core",
1291 "qup-config";
1293 pinctrl-0 = <&hub_i2c7_data_clk>;
1294 pinctrl-names = "default";
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1303 compatible = "qcom,geni-i2c-master-hub";
1310 clock-names = "se",
1317 interconnect-names = "qup-core",
1318 "qup-config";
1320 pinctrl-0 = <&hub_i2c8_data_clk>;
1321 pinctrl-names = "default";
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1330 compatible = "qcom,geni-i2c-master-hub";
1337 clock-names = "se",
1344 interconnect-names = "qup-core",
1345 "qup-config";
1347 pinctrl-0 = <&hub_i2c9_data_clk>;
1348 pinctrl-names = "default";
1350 #address-cells = <1>;
1351 #size-cells = <0>;
1357 gpi_dma1: dma-controller@a00000 {
1358 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
1374 dma-channels = <12>;
1375 dma-channel-mask = <0x1e>;
1376 #dma-cells = <3>;
1384 compatible = "qcom,geni-se-qup";
1389 clock-names = "m-ahb",
1390 "s-ahb";
1394 #address-cells = <2>;
1395 #size-cells = <2>;
1401 compatible = "qcom,geni-i2c";
1407 clock-names = "se";
1415 interconnect-names = "qup-core",
1416 "qup-config",
1417 "qup-memory";
1421 dma-names = "tx",
1424 pinctrl-0 = <&qup_i2c0_data_clk>;
1425 pinctrl-names = "default";
1427 #address-cells = <1>;
1428 #size-cells = <0>;
1434 compatible = "qcom,geni-spi";
1440 clock-names = "se";
1448 interconnect-names = "qup-core",
1449 "qup-config",
1450 "qup-memory";
1454 dma-names = "tx",
1457 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1458 pinctrl-names = "default";
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1467 compatible = "qcom,geni-i2c";
1473 clock-names = "se";
1481 interconnect-names = "qup-core",
1482 "qup-config",
1483 "qup-memory";
1487 dma-names = "tx",
1490 pinctrl-0 = <&qup_i2c1_data_clk>;
1491 pinctrl-names = "default";
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1500 compatible = "qcom,geni-spi";
1506 clock-names = "se";
1514 interconnect-names = "qup-core",
1515 "qup-config",
1516 "qup-memory";
1520 dma-names = "tx",
1523 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1524 pinctrl-names = "default";
1526 #address-cells = <1>;
1527 #size-cells = <0>;
1533 compatible = "qcom,geni-i2c";
1539 clock-names = "se";
1547 interconnect-names = "qup-core",
1548 "qup-config",
1549 "qup-memory";
1553 dma-names = "tx",
1556 pinctrl-0 = <&qup_i2c2_data_clk>;
1557 pinctrl-names = "default";
1559 #address-cells = <1>;
1560 #size-cells = <0>;
1566 compatible = "qcom,geni-spi";
1572 clock-names = "se";
1580 interconnect-names = "qup-core",
1581 "qup-config",
1582 "qup-memory";
1586 dma-names = "tx",
1589 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1590 pinctrl-names = "default";
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1599 compatible = "qcom,geni-i2c";
1605 clock-names = "se";
1613 interconnect-names = "qup-core",
1614 "qup-config",
1615 "qup-memory";
1619 dma-names = "tx",
1622 pinctrl-0 = <&qup_i2c3_data_clk>;
1623 pinctrl-names = "default";
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1632 compatible = "qcom,geni-spi";
1638 clock-names = "se";
1646 interconnect-names = "qup-core",
1647 "qup-config",
1648 "qup-memory";
1652 dma-names = "tx",
1655 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1656 pinctrl-names = "default";
1658 #address-cells = <1>;
1659 #size-cells = <0>;
1665 compatible = "qcom,geni-i2c";
1671 clock-names = "se";
1679 interconnect-names = "qup-core",
1680 "qup-config",
1681 "qup-memory";
1685 dma-names = "tx",
1688 pinctrl-0 = <&qup_i2c4_data_clk>;
1689 pinctrl-names = "default";
1691 #address-cells = <1>;
1692 #size-cells = <0>;
1698 compatible = "qcom,geni-spi";
1704 clock-names = "se";
1712 interconnect-names = "qup-core",
1713 "qup-config",
1714 "qup-memory";
1718 dma-names = "tx",
1721 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1722 pinctrl-names = "default";
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1731 compatible = "qcom,geni-i2c";
1737 clock-names = "se";
1745 interconnect-names = "qup-core",
1746 "qup-config",
1747 "qup-memory";
1751 dma-names = "tx",
1754 pinctrl-0 = <&qup_i2c5_data_clk>;
1755 pinctrl-names = "default";
1757 #address-cells = <1>;
1758 #size-cells = <0>;
1764 compatible = "qcom,geni-spi";
1770 clock-names = "se";
1778 interconnect-names = "qup-core",
1779 "qup-config",
1780 "qup-memory";
1784 dma-names = "tx",
1787 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1788 pinctrl-names = "default";
1790 #address-cells = <1>;
1791 #size-cells = <0>;
1797 compatible = "qcom,geni-i2c";
1803 clock-names = "se";
1811 interconnect-names = "qup-core",
1812 "qup-config",
1813 "qup-memory";
1817 dma-names = "tx",
1820 pinctrl-0 = <&qup_i2c6_data_clk>;
1821 pinctrl-names = "default";
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1830 compatible = "qcom,geni-spi";
1836 clock-names = "se";
1844 interconnect-names = "qup-core",
1845 "qup-config",
1846 "qup-memory";
1850 dma-names = "tx",
1853 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1854 pinctrl-names = "default";
1856 #address-cells = <1>;
1857 #size-cells = <0>;
1863 compatible = "qcom,geni-debug-uart";
1869 clock-names = "se";
1875 interconnect-names = "qup-core",
1876 "qup-config";
1879 pinctrl-0 = <&qup_uart7_default>;
1880 pinctrl-names = "default";
1887 compatible = "qcom,sm8750-cnoc-main";
1889 qcom,bcm-voters = <&apps_bcm_voter>;
1890 #interconnect-cells = <2>;
1894 compatible = "qcom,sm8750-config-noc";
1896 qcom,bcm-voters = <&apps_bcm_voter>;
1897 #interconnect-cells = <2>;
1901 compatible = "qcom,sm8750-system-noc";
1903 qcom,bcm-voters = <&apps_bcm_voter>;
1904 #interconnect-cells = <2>;
1908 compatible = "qcom,sm8750-pcie-anoc";
1910 qcom,bcm-voters = <&apps_bcm_voter>;
1911 #interconnect-cells = <2>;
1918 compatible = "qcom,sm8750-aggre1-noc";
1920 qcom,bcm-voters = <&apps_bcm_voter>;
1921 #interconnect-cells = <2>;
1928 compatible = "qcom,sm8750-aggre2-noc";
1930 qcom,bcm-voters = <&apps_bcm_voter>;
1931 #interconnect-cells = <2>;
1936 compatible = "qcom,sm8750-mmss-noc";
1938 qcom,bcm-voters = <&apps_bcm_voter>;
1939 #interconnect-cells = <2>;
1943 compatible = "qcom,tcsr-mutex";
1945 #hwlock-cells = <1>;
1949 compatible = "qcom,sm8750-lpass-ag-noc";
1951 qcom,bcm-voters = <&apps_bcm_voter>;
1952 #interconnect-cells = <2>;
1956 compatible = "qcom,sm8750-lpass-lpiaon-noc";
1958 qcom,bcm-voters = <&apps_bcm_voter>;
1959 #interconnect-cells = <2>;
1963 compatible = "qcom,sm8750-lpass-lpicx-noc";
1965 qcom,bcm-voters = <&apps_bcm_voter>;
1966 #interconnect-cells = <2>;
1969 pdc: interrupt-controller@b220000 {
1970 compatible = "qcom,sm8750-pdc", "qcom,pdc";
1973 qcom,pdc-ranges = <0 745 51>, <51 527 47>,
1976 #interrupt-cells = <2>;
1977 interrupt-parent = <&intc>;
1978 interrupt-controller;
1982 compatible = "qcom,spmi-pmic-arb";
1988 reg-names = "core",
1994 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1995 interrupt-names = "periph_irq";
1999 qcom,bus-id = <0>;
2001 interrupt-controller;
2002 #interrupt-cells = <4>;
2004 #address-cells = <2>;
2005 #size-cells = <0>;
2009 compatible = "qcom,sm8750-tlmm";
2014 gpio-controller;
2015 #gpio-cells = <2>;
2017 interrupt-controller;
2018 #interrupt-cells = <2>;
2020 gpio-ranges = <&tlmm 0 0 216>;
2021 wakeup-parent = <&pdc>;
2023 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
2027 drive-strength = <2>;
2028 bias-pull-up;
2031 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
2035 drive-strength = <2>;
2036 bias-pull-up;
2039 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
2043 drive-strength = <2>;
2044 bias-pull-up;
2047 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
2051 drive-strength = <2>;
2052 bias-pull-up;
2055 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
2059 drive-strength = <2>;
2060 bias-pull-up;
2063 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
2067 drive-strength = <2>;
2068 bias-pull-up;
2071 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
2075 drive-strength = <2>;
2076 bias-pull-up;
2079 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
2083 drive-strength = <2>;
2084 bias-pull-up;
2087 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
2091 drive-strength = <2>;
2092 bias-pull-up;
2095 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
2099 drive-strength = <2>;
2100 bias-pull-up;
2103 pcie0_default_state: pcie0-default-state {
2104 perst-pins {
2107 drive-strength = <2>;
2108 bias-pull-down;
2111 clkreq-pins {
2114 drive-strength = <2>;
2115 bias-pull-up;
2118 wake-pins {
2121 drive-strength = <2>;
2122 bias-pull-up;
2126 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
2130 drive-strength = <2>;
2131 bias-pull-up;
2134 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
2138 drive-strength = <2>;
2139 bias-pull-up;
2142 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
2146 drive-strength = <2>;
2147 bias-pull-up;
2150 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
2154 drive-strength = <2>;
2155 bias-pull-up;
2158 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
2162 drive-strength = <2>;
2163 bias-pull-up;
2166 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
2170 drive-strength = <2>;
2171 bias-pull-up;
2174 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
2178 drive-strength = <2>;
2179 bias-pull-up;
2182 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
2186 drive-strength = <2>;
2187 bias-pull-up;
2190 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
2194 drive-strength = <2>;
2195 bias-pull-up;
2198 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
2202 drive-strength = <2>;
2203 bias-pull-up;
2206 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
2210 drive-strength = <2>;
2211 bias-pull-up;
2214 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
2218 drive-strength = <2>;
2219 bias-pull-up;
2222 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
2226 drive-strength = <2>;
2227 bias-pull-up;
2230 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
2234 drive-strength = <2>;
2235 bias-pull-up;
2238 qup_spi0_cs: qup-spi0-cs-state {
2241 drive-strength = <6>;
2242 bias-disable;
2245 qup_spi0_data_clk: qup-spi0-data-clk-state {
2249 drive-strength = <6>;
2250 bias-disable;
2253 qup_spi1_cs: qup-spi1-cs-state {
2256 drive-strength = <6>;
2257 bias-disable;
2260 qup_spi1_data_clk: qup-spi1-data-clk-state {
2264 drive-strength = <6>;
2265 bias-disable;
2268 qup_spi2_cs: qup-spi2-cs-state {
2271 drive-strength = <6>;
2272 bias-disable;
2275 qup_spi2_data_clk: qup-spi2-data-clk-state {
2279 drive-strength = <6>;
2280 bias-disable;
2283 qup_spi3_cs: qup-spi3-cs-state {
2286 drive-strength = <6>;
2287 bias-disable;
2290 qup_spi3_data_clk: qup-spi3-data-clk-state {
2294 drive-strength = <6>;
2295 bias-disable;
2298 qup_spi4_cs: qup-spi4-cs-state {
2301 drive-strength = <6>;
2302 bias-disable;
2305 qup_spi4_data_clk: qup-spi4-data-clk-state {
2309 drive-strength = <6>;
2310 bias-disable;
2313 qup_spi5_cs: qup-spi5-cs-state {
2316 drive-strength = <6>;
2317 bias-disable;
2320 qup_spi5_data_clk: qup-spi5-data-clk-state {
2324 drive-strength = <6>;
2325 bias-disable;
2328 qup_spi6_cs: qup-spi6-cs-state {
2331 drive-strength = <6>;
2332 bias-disable;
2335 qup_spi6_data_clk: qup-spi6-data-clk-state {
2339 drive-strength = <6>;
2340 bias-disable;
2343 qup_spi8_cs: qup-spi8-cs-state {
2346 drive-strength = <6>;
2347 bias-disable;
2350 qup_spi8_data_clk: qup-spi8-data-clk-state {
2354 drive-strength = <6>;
2355 bias-disable;
2358 qup_spi9_cs: qup-spi9-cs-state {
2361 drive-strength = <6>;
2362 bias-disable;
2365 qup_spi9_data_clk: qup-spi9-data-clk-state {
2369 drive-strength = <6>;
2370 bias-disable;
2373 qup_spi10_cs: qup-spi10-cs-state {
2376 drive-strength = <6>;
2377 bias-disable;
2380 qup_spi10_data_clk: qup-spi10-data-clk-state {
2384 drive-strength = <6>;
2385 bias-disable;
2388 qup_spi11_cs: qup-spi11-cs-state {
2391 drive-strength = <6>;
2392 bias-disable;
2395 qup_spi11_data_clk: qup-spi11-data-clk-state {
2399 drive-strength = <6>;
2400 bias-disable;
2403 qup_spi12_cs: qup-spi12-cs-state {
2406 drive-strength = <6>;
2407 bias-disable;
2410 qup_spi12_data_clk: qup-spi12-data-clk-state {
2414 drive-strength = <6>;
2415 bias-disable;
2418 qup_spi13_cs: qup-spi13-cs-state {
2421 drive-strength = <6>;
2422 bias-pull-up;
2425 qup_spi13_data_clk: qup-spi13-data-clk-state {
2429 drive-strength = <6>;
2430 bias-disable;
2433 qup_spi15_cs: qup-spi15-cs-state {
2436 drive-strength = <6>;
2437 bias-disable;
2440 qup_spi15_data_clk: qup-spi15-data-clk-state {
2444 drive-strength = <6>;
2445 bias-disable;
2448 qup_uart7_default: qup-uart7-default-state {
2452 drive-strength = <2>;
2453 bias-disable;
2456 qup_uart14_default: qup-uart14-default-state {
2460 drive-strength = <2>;
2461 bias-pull-up;
2464 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
2468 drive-strength = <2>;
2469 bias-pull-down;
2472 sdc2_sleep: sdc2-sleep-state {
2473 clk-pins {
2475 drive-strength = <2>;
2476 bias-disable;
2479 cmd-pins {
2481 drive-strength = <2>;
2482 bias-pull-up;
2485 data-pins {
2487 drive-strength = <2>;
2488 bias-pull-up;
2492 sdc2_default: sdc2-default-state {
2493 clk-pins {
2495 drive-strength = <16>;
2496 bias-disable;
2499 cmd-pins {
2501 drive-strength = <10>;
2502 bias-pull-up;
2505 data-pins {
2507 drive-strength = <10>;
2508 bias-pull-up;
2513 tcsrcc: clock-controller@f204008 {
2514 compatible = "qcom,sm8750-tcsr", "syscon";
2519 #clock-cells = <1>;
2520 #reset-cells = <1>;
2524 compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2641 #iommu-cells = <2>;
2642 #global-interrupts = <1>;
2644 dma-coherent;
2647 intc: interrupt-controller@16000000 {
2648 compatible = "arm,gic-v3";
2654 #interrupt-cells = <3>;
2655 interrupt-controller;
2657 #redistributor-regions = <1>;
2658 redistributor-stride = <0x0 0x40000>;
2660 #address-cells = <2>;
2661 #size-cells = <2>;
2664 gic_its: msi-controller@16040000 {
2665 compatible = "arm,gic-v3-its";
2668 msi-controller;
2669 #msi-cells = <1>;
2674 compatible = "qcom,rpmh-rsc";
2678 reg-names = "drv-0",
2679 "drv-1",
2680 "drv-2";
2685 qcom,tcs-offset = <0xd00>;
2686 qcom,drv-id = <2>;
2687 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
2692 power-domains = <&system_pd>;
2694 apps_bcm_voter: bcm-voter {
2695 compatible = "qcom,bcm-voter";
2698 rpmhcc: clock-controller {
2699 compatible = "qcom,sm8750-rpmh-clk";
2702 clock-names = "xo";
2704 #clock-cells = <1>;
2707 rpmhpd: power-controller {
2708 compatible = "qcom,sm8750-rpmhpd";
2710 operating-points-v2 = <&rpmhpd_opp_table>;
2712 #power-domain-cells = <1>;
2714 rpmhpd_opp_table: opp-table {
2715 compatible = "operating-points-v2";
2717 rpmhpd_opp_ret: opp-16 {
2718 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2721 rpmhpd_opp_min_svs: opp-48 {
2722 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2725 rpmhpd_opp_low_svs_d3: opp-50 {
2726 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
2729 rpmhpd_opp_low_svs_d2: opp-52 {
2730 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2733 rpmhpd_opp_low_svs_d1: opp-56 {
2734 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2737 rpmhpd_opp_low_svs_d0: opp-60 {
2738 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2741 rpmhpd_opp_low_svs: opp-64 {
2742 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2745 rpmhpd_opp_low_svs_l1: opp-80 {
2746 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2749 rpmhpd_opp_svs: opp-128 {
2750 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2753 rpmhpd_opp_svs_l0: opp-144 {
2754 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2757 rpmhpd_opp_svs_l1: opp-192 {
2758 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2761 rpmhpd_opp_svs_l2: opp-224 {
2762 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2765 rpmhpd_opp_nom: opp-256 {
2766 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2769 rpmhpd_opp_nom_l1: opp-320 {
2770 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2773 rpmhpd_opp_nom_l2: opp-336 {
2774 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2777 rpmhpd_opp_turbo: opp-384 {
2778 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2781 rpmhpd_opp_turbo_l1: opp-416 {
2782 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2785 rpmhpd_opp_turbo_l2: opp-432 {
2786 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
2789 rpmhpd_opp_turbo_l3: opp-448 {
2790 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
2793 rpmhpd_opp_turbo_l4: opp-452 {
2794 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
2797 rpmhpd_opp_super_turbo_no_cpr: opp-480 {
2798 opp-level =
2806 compatible = "arm,armv7-timer-mem";
2809 #address-cells = <2>;
2810 #size-cells = <1>;
2820 frame-number = <0>;
2828 frame-number = <1>;
2838 frame-number = <2>;
2848 frame-number = <3>;
2858 frame-number = <4>;
2868 frame-number = <5>;
2878 frame-number = <6>;
2885 compatible = "qcom,sm8750-gem-noc";
2887 qcom,bcm-voters = <&apps_bcm_voter>;
2888 #interconnect-cells = <2>;
2892 compatible = "qcom,sm8750-nsp-noc";
2894 qcom,bcm-voters = <&apps_bcm_voter>;
2895 #interconnect-cells = <2>;
2900 compatible = "arm,armv8-timer";