Lines Matching +full:0 +full:x0c440000
25 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0 0x0>;
46 reg = <0x0 0x100>;
56 reg = <0x0 0x200>;
66 reg = <0x0 0x300>;
76 reg = <0x0 0x400>;
86 reg = <0x0 0x500>;
96 reg = <0x0 0x10000>;
112 reg = <0x0 0x10100>;
160 cluster0_c4: cpu-sleep-0 {
163 arm,psci-suspend-param = <0x00000004>;
172 arm,psci-suspend-param = <0x00000004>;
181 cluster_cl5: cluster-sleep-0 {
183 arm,psci-suspend-param = <0x01000054>;
189 domain_ss3: domain-sleep-0 {
191 arm,psci-suspend-param = <0x0200c354>;
207 clk_virt: interconnect-0 {
222 reg = <0x0 0xa0000000 0x0 0x0>;
235 #power-domain-cells = <0>;
241 #power-domain-cells = <0>;
247 #power-domain-cells = <0>;
253 #power-domain-cells = <0>;
259 #power-domain-cells = <0>;
265 #power-domain-cells = <0>;
271 #power-domain-cells = <0>;
277 #power-domain-cells = <0>;
283 #power-domain-cells = <0>;
289 #power-domain-cells = <0>;
300 reg = <0x0 0x80000000 0x0 0xe00000>;
305 reg = <0x0 0x80e00000 0x0 0x40000>;
310 reg = <0x0 0x81200000 0x0 0x200000>;
315 reg = <0x0 0x81a00000 0x0 0x40000>;
320 reg = <0x0 0x81c00000 0x0 0x60000>;
326 reg = <0x0 0x81c60000 0x0 0x20000>;
332 reg = <0x0 0x81c80000 0x0 0x74000>;
340 reg = <0x0 0x81d00000 0x0 0x200000>;
346 reg = <0x0 0x81f00000 0x0 0x100000>;
351 reg = <0x0 0x82000000 0x0 0x380000>;
356 reg = <0x0 0x82380000 0x0 0x20000>;
361 reg = <0x0 0x823a0000 0x0 0x40000>;
366 reg = <0x0 0x823e0000 0x0 0x80000>;
371 reg = <0x0 0x824a0000 0x0 0x100000>;
376 reg = <0x0 0x82600000 0x0 0x100000>;
381 reg = <0x0 0x82700000 0x0 0x100000>;
386 reg = <0x0 0x82800000 0x0 0x2000000>;
391 reg = <0x0 0x84a00000 0x0 0x4900000>;
396 reg = <0x0 0x89300000 0x0 0xa80000>;
401 reg = <0x0 0x8ba00000 0x0 0xf600000>;
406 reg = <0x0 0x9b000000 0x0 0x80000>;
411 reg = <0x0 0x9b080000 0x0 0x10000>;
416 reg = <0x0 0x9b090000 0x0 0xa000>;
421 reg = <0x0 0x9b09a000 0x0 0x2000>;
426 reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
432 reg = <0x0 0x9b280000 0x0 0x40000>;
438 reg = <0x0 0x9b2c0000 0x0 0x40000>;
443 reg = <0x0 0x9b300000 0x0 0x800000>;
448 reg = <0x0 0x9bb00000 0x0 0x800000>;
453 reg = <0x0 0x9c300000 0x0 0x800000>;
458 reg = <0x0 0x9cb00000 0x0 0x700000>;
463 reg = <0x0 0x9d200000 0x0 0x1900000>;
468 reg = <0x0 0x9eb00000 0x0 0x80000>;
473 reg = <0x0 0x9ec00000 0x0 0x180000>;
478 reg = <0x0 0x9ed80000 0x0 0x80000>;
483 reg = <0x0 0x9ee00000 0x0 0x3a80000>;
488 reg = <0x0 0xb8000000 0x0 0x1c0000>;
494 reg = <0x0 0xd4e23000 0x0 0x2dd000>;
499 reg = <0x0 0xd8000000 0x0 0x600000>;
504 reg = <0x0 0xf3800000 0x0 0x4400000>;
509 reg = <0x0 0xf7c00000 0x0 0x4c00000>;
514 reg = <0x0 0xff800000 0x0 0x800000>;
519 soc: soc@0 {
524 dma-ranges = <0 0 0 0 0x10 0>;
525 ranges = <0 0 0 0 0x10 0>;
529 reg = <0x0 0x00100000 0x0 0x1f4200>;
532 <0>,
534 <0>,
535 <0>,
536 <0>,
537 <0>,
538 <0>;
547 reg = <0x0 0x00800000 0x0 0x60000>;
563 dma-channel-mask = <0x1e>;
566 iommus = <&apps_smmu 0x436 0x0>;
573 reg = <0x0 0x008c0000 0x0 0x2000>;
580 iommus = <&apps_smmu 0x423 0x0>;
590 reg = <0x0 0x00880000 0x0 0x4000>;
607 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
608 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
612 pinctrl-0 = <&qup_i2c8_data_clk>;
616 #size-cells = <0>;
623 reg = <0x0 0x00880000 0x0 0x4000>;
640 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
641 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
645 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
649 #size-cells = <0>;
656 reg = <0x0 0x00884000 0x0 0x4000>;
673 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
678 pinctrl-0 = <&qup_i2c9_data_clk>;
682 #size-cells = <0>;
689 reg = <0x0 0x00884000 0x0 0x4000>;
706 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
711 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
715 #size-cells = <0>;
722 reg = <0x0 0x00888000 0x0 0x4000>;
739 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
744 pinctrl-0 = <&qup_i2c10_data_clk>;
748 #size-cells = <0>;
755 reg = <0x0 0x00888000 0x0 0x4000>;
772 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
777 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
781 #size-cells = <0>;
788 reg = <0x0 0x0088c000 0x0 0x4000>;
805 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
810 pinctrl-0 = <&qup_i2c11_data_clk>;
814 #size-cells = <0>;
821 reg = <0x0 0x0088c000 0x0 0x4000>;
838 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
843 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
847 #size-cells = <0>;
854 reg = <0x0 0x00890000 0x0 0x4000>;
871 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
876 pinctrl-0 = <&qup_i2c12_data_clk>;
880 #size-cells = <0>;
887 reg = <0x0 0x00890000 0x0 0x4000>;
904 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
909 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
913 #size-cells = <0>;
920 reg = <0x0 0x00894000 0x0 0x4000>;
937 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
942 pinctrl-0 = <&qup_i2c13_data_clk>;
946 #size-cells = <0>;
953 reg = <0x0 0x00894000 0x0 0x4000>;
970 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
975 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
979 #size-cells = <0>;
986 reg = <0x0 0x00898000 0x0 0x4000>;
1000 pinctrl-0 = <&qup_uart14_default>;
1008 reg = <0x0 0x0089c000 0x0 0x4000>;
1025 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1030 pinctrl-0 = <&qup_i2c15_data_clk>;
1034 #size-cells = <0>;
1041 reg = <0x0 0x0089c000 0x0 0x4000>;
1058 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1063 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1067 #size-cells = <0>;
1075 reg = <0x0 0x009c0000 0x0 0x2000>;
1088 reg = <0x0 0x00980000 0x0 0x4000>;
1104 pinctrl-0 = <&hub_i2c0_data_clk>;
1108 #size-cells = <0>;
1115 reg = <0x0 0x00984000 0x0 0x4000>;
1131 pinctrl-0 = <&hub_i2c1_data_clk>;
1135 #size-cells = <0>;
1142 reg = <0x0 0x00988000 0x0 0x4000>;
1158 pinctrl-0 = <&hub_i2c2_data_clk>;
1162 #size-cells = <0>;
1169 reg = <0x0 0x0098c000 0x0 0x4000>;
1185 pinctrl-0 = <&hub_i2c3_data_clk>;
1189 #size-cells = <0>;
1196 reg = <0x0 0x00990000 0x0 0x4000>;
1212 pinctrl-0 = <&hub_i2c4_data_clk>;
1216 #size-cells = <0>;
1223 reg = <0x0 0x00994000 0x0 0x4000>;
1239 pinctrl-0 = <&hub_i2c5_data_clk>;
1243 #size-cells = <0>;
1250 reg = <0x0 0x00998000 0x0 0x4000>;
1266 pinctrl-0 = <&hub_i2c6_data_clk>;
1270 #size-cells = <0>;
1277 reg = <0x0 0x0099c000 0x0 0x4000>;
1293 pinctrl-0 = <&hub_i2c7_data_clk>;
1297 #size-cells = <0>;
1304 reg = <0x0 0x009a0000 0x0 0x4000>;
1320 pinctrl-0 = <&hub_i2c8_data_clk>;
1324 #size-cells = <0>;
1331 reg = <0x0 0x009a4000 0x0 0x4000>;
1347 pinctrl-0 = <&hub_i2c9_data_clk>;
1351 #size-cells = <0>;
1359 reg = <0x0 0x00a00000 0x0 0x60000>;
1375 dma-channel-mask = <0x1e>;
1378 iommus = <&apps_smmu 0xb6 0x0>;
1385 reg = <0x0 0x00ac0000 0x0 0x2000>;
1392 iommus = <&apps_smmu 0xa3 0x0>;
1402 reg = <0x0 0x00a80000 0x0 0x4000>;
1419 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1420 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1424 pinctrl-0 = <&qup_i2c0_data_clk>;
1428 #size-cells = <0>;
1435 reg = <0x0 0x00a80000 0x0 0x4000>;
1452 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1453 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1457 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1461 #size-cells = <0>;
1468 reg = <0x0 0x00a84000 0x0 0x4000>;
1485 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1490 pinctrl-0 = <&qup_i2c1_data_clk>;
1494 #size-cells = <0>;
1501 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1523 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1527 #size-cells = <0>;
1534 reg = <0x0 0x00a88000 0x0 0x4000>;
1551 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1556 pinctrl-0 = <&qup_i2c2_data_clk>;
1560 #size-cells = <0>;
1567 reg = <0x0 0x00a88000 0x0 0x4000>;
1584 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1589 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1593 #size-cells = <0>;
1600 reg = <0x0 0x00a8c000 0x0 0x4000>;
1617 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1622 pinctrl-0 = <&qup_i2c3_data_clk>;
1626 #size-cells = <0>;
1633 reg = <0x0 0x00a8c000 0x0 0x4000>;
1650 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1655 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1659 #size-cells = <0>;
1666 reg = <0x0 0x00a90000 0x0 0x4000>;
1683 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1688 pinctrl-0 = <&qup_i2c4_data_clk>;
1692 #size-cells = <0>;
1699 reg = <0x0 0x00a90000 0x0 0x4000>;
1716 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1721 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1725 #size-cells = <0>;
1732 reg = <0x0 0x00a94000 0x0 0x4000>;
1749 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1754 pinctrl-0 = <&qup_i2c5_data_clk>;
1758 #size-cells = <0>;
1765 reg = <0x0 0x00a94000 0x0 0x4000>;
1782 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1787 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1791 #size-cells = <0>;
1798 reg = <0x0 0x00a98000 0x0 0x4000>;
1815 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1820 pinctrl-0 = <&qup_i2c6_data_clk>;
1824 #size-cells = <0>;
1831 reg = <0x0 0x00a98000 0x0 0x4000>;
1848 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1853 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1857 #size-cells = <0>;
1864 reg = <0x0 0x00a9c000 0x0 0x4000>;
1879 pinctrl-0 = <&qup_uart7_default>;
1888 reg = <0x0 0x01500000 0x0 0x16080>;
1895 reg = <0x0 0x01600000 0x0 0x6200>;
1902 reg = <0x0 0x01680000 0x0 0x1d080>;
1909 reg = <0x0 0x016c0000 0x0 0x11400>;
1919 reg = <0x0 0x016e0000 0x0 0x16400>;
1929 reg = <0x0 0x01700000 0x0 0x1f400>;
1937 reg = <0x0 0x01780000 0x0 0x5b800>;
1944 reg = <0x0 0x01f40000 0x0 0x20000>;
1950 reg = <0x0 0x07e40000 0x0 0xe080>;
1957 reg = <0x0 0x07400000 0x0 0x19080>;
1964 reg = <0x0 0x07420000 0x0 0x44080>;
1971 reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
1973 qcom,pdc-ranges = <0 745 51>, <51 527 47>,
1983 reg = <0x0 0x0c400000 0x0 0x3000>,
1984 <0x0 0x0c500000 0x0 0x400000>,
1985 <0x0 0x0c440000 0x0 0x80000>,
1986 <0x0 0x0c4c0000 0x0 0x10000>,
1987 <0x0 0x0c42d000 0x0 0x4000>;
1997 qcom,ee = <0>;
1998 qcom,channel = <0>;
1999 qcom,bus-id = <0>;
2005 #size-cells = <0>;
2010 reg = <0x0 0x0f100000 0x0 0x102000>;
2020 gpio-ranges = <&tlmm 0 0 216>;
2515 reg = <0x0 0x0f204008 0x0 0x3004>;
2525 reg = <0x0 0x15000000 0x0 0x100000>;
2649 reg = <0x0 0x16000000 0x0 0x10000>,
2650 <0x0 0x16080000 0x0 0x200000>;
2658 redistributor-stride = <0x0 0x40000>;
2666 reg = <0x0 0x16040000 0x0 0x20000>;
2675 reg = <0x0 0x16500000 0x0 0x10000>,
2676 <0x0 0x16510000 0x0 0x10000>,
2677 <0x0 0x16520000 0x0 0x10000>;
2678 reg-names = "drv-0",
2685 qcom,tcs-offset = <0xd00>;
2688 <WAKE_TCS 2>, <CONTROL_TCS 0>;
2807 reg = <0x0 0x16800000 0x0 0x1000>;
2811 ranges = <0 0 0 0 0x20000000>;
2814 reg = <0x0 0x16801000 0x1000>,
2815 <0x0 0x16802000 0x1000>;
2820 frame-number = <0>;
2824 reg = <0x0 0x16803000 0x1000>;
2834 reg = <0x0 0x16805000 0x1000>;
2844 reg = <0x0 0x16807000 0x1000>;
2854 reg = <0x0 0x16809000 0x1000>;
2864 reg = <0x0 0x1680b000 0x1000>;
2874 reg = <0x0 0x1680d000 0x1000>;
2886 reg = <0x0 0x24100000 0x0 0x14b080>;
2893 reg = <0x0 0x320c0000 0x0 0x13080>;