Lines Matching +full:ete +full:- +full:0
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
23 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
31 #address-cells = <2>;
32 #size-cells = <2>;
37 xo_board: xo-board {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <76800000>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <32764>;
51 #address-cells = <2>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0 0x0>;
58 enable-method = "psci";
59 next-level-cache = <&l2_0>;
60 power-domains = <&cpu_pd0>;
61 power-domain-names = "psci";
62 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw 0>;
65 l2_0: l2-cache {
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&l3_0>;
70 l3_0: l3-cache {
72 cache-level = <3>;
73 cache-unified;
81 reg = <0x0 0x100>;
82 enable-method = "psci";
83 next-level-cache = <&l2_100>;
84 power-domains = <&cpu_pd1>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw 0>;
89 l2_100: l2-cache {
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&l3_0>;
100 reg = <0x0 0x200>;
101 enable-method = "psci";
102 next-level-cache = <&l2_200>;
103 power-domains = <&cpu_pd2>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 0>;
108 l2_200: l2-cache {
110 cache-level = <2>;
111 cache-unified;
112 next-level-cache = <&l3_0>;
119 reg = <0x0 0x300>;
120 enable-method = "psci";
121 next-level-cache = <&l2_300>;
122 power-domains = <&cpu_pd3>;
123 power-domain-names = "psci";
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 0>;
127 l2_300: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&l3_0>;
138 reg = <0x0 0x400>;
139 enable-method = "psci";
140 next-level-cache = <&l2_400>;
141 power-domains = <&cpu_pd4>;
142 power-domain-names = "psci";
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>;
146 l2_400: l2-cache {
148 cache-level = <2>;
149 cache-unified;
150 next-level-cache = <&l3_0>;
157 reg = <0x0 0x500>;
158 enable-method = "psci";
159 next-level-cache = <&l2_500>;
160 power-domains = <&cpu_pd5>;
161 power-domain-names = "psci";
162 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>;
165 l2_500: l2-cache {
167 cache-level = <2>;
168 cache-unified;
169 next-level-cache = <&l3_0>;
176 reg = <0x0 0x600>;
177 enable-method = "psci";
178 next-level-cache = <&l2_600>;
179 power-domains = <&cpu_pd6>;
180 power-domain-names = "psci";
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>;
184 l2_600: l2-cache {
186 cache-level = <2>;
187 cache-unified;
188 next-level-cache = <&l3_0>;
195 reg = <0x0 0x700>;
196 enable-method = "psci";
197 next-level-cache = <&l2_700>;
198 power-domains = <&cpu_pd7>;
199 power-domain-names = "psci";
200 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>;
203 l2_700: l2-cache {
205 cache-level = <2>;
206 cache-unified;
207 next-level-cache = <&l3_0>;
211 cpu-map {
247 idle-states {
248 entry-method = "psci";
250 little_cpu_sleep_0: cpu-sleep-0-0 {
251 compatible = "arm,idle-state";
252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency-us = <800>;
255 exit-latency-us = <750>;
256 min-residency-us = <4090>;
257 local-timer-stop;
260 big_cpu_sleep_0: cpu-sleep-1-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency-us = <600>;
265 exit-latency-us = <1550>;
266 min-residency-us = <4791>;
267 local-timer-stop;
271 domain-idle-states {
272 cluster_sleep_0: cluster-sleep-0 {
273 compatible = "domain-idle-state";
274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency-us = <1050>;
276 exit-latency-us = <2500>;
277 min-residency-us = <5309>;
280 cluster_sleep_1: cluster-sleep-1 {
281 compatible = "domain-idle-state";
282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency-us = <2700>;
284 exit-latency-us = <3500>;
285 min-residency-us = <13959>;
290 ete-0 {
291 compatible = "arm,embedded-trace-extension";
294 out-ports {
297 remote-endpoint = <&funnel_ete_in_ete0>;
303 ete-1 {
304 compatible = "arm,embedded-trace-extension";
307 out-ports {
310 remote-endpoint = <&funnel_ete_in_ete1>;
316 ete-2 {
317 compatible = "arm,embedded-trace-extension";
320 out-ports {
323 remote-endpoint = <&funnel_ete_in_ete2>;
329 ete-3 {
330 compatible = "arm,embedded-trace-extension";
333 out-ports {
336 remote-endpoint = <&funnel_ete_in_ete3>;
342 ete-4 {
343 compatible = "arm,embedded-trace-extension";
346 out-ports {
349 remote-endpoint = <&funnel_ete_in_ete4>;
355 ete-5 {
356 compatible = "arm,embedded-trace-extension";
359 out-ports {
362 remote-endpoint = <&funnel_ete_in_ete5>;
368 ete-6 {
369 compatible = "arm,embedded-trace-extension";
372 out-ports {
375 remote-endpoint = <&funnel_ete_in_ete6>;
381 ete-7 {
382 compatible = "arm,embedded-trace-extension";
385 out-ports {
388 remote-endpoint = <&funnel_ete_in_ete7>;
394 funnel-ete {
395 compatible = "arm,coresight-static-funnel";
397 out-ports {
400 remote-endpoint =
406 in-ports {
407 #address-cells = <1>;
408 #size-cells = <0>;
410 port@0 {
411 reg = <0>;
413 remote-endpoint =
421 remote-endpoint =
429 remote-endpoint =
437 remote-endpoint =
445 remote-endpoint =
453 remote-endpoint =
461 remote-endpoint =
469 remote-endpoint =
478 compatible = "qcom,scm-sm8450", "qcom,scm";
479 qcom,dload-mode = <&tcsr 0x13000>;
480 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
481 #reset-cells = <1>;
485 clk_virt: interconnect-0 {
486 compatible = "qcom,sm8450-clk-virt";
487 #interconnect-cells = <2>;
488 qcom,bcm-voters = <&apps_bcm_voter>;
491 mc_virt: interconnect-1 {
492 compatible = "qcom,sm8450-mc-virt";
493 #interconnect-cells = <2>;
494 qcom,bcm-voters = <&apps_bcm_voter>;
500 reg = <0x0 0xa0000000 0x0 0x0>;
504 compatible = "arm,armv8-pmuv3";
509 compatible = "arm,psci-1.0";
512 cpu_pd0: power-domain-cpu0 {
513 #power-domain-cells = <0>;
514 power-domains = <&cluster_pd>;
515 domain-idle-states = <&little_cpu_sleep_0>;
518 cpu_pd1: power-domain-cpu1 {
519 #power-domain-cells = <0>;
520 power-domains = <&cluster_pd>;
521 domain-idle-states = <&little_cpu_sleep_0>;
524 cpu_pd2: power-domain-cpu2 {
525 #power-domain-cells = <0>;
526 power-domains = <&cluster_pd>;
527 domain-idle-states = <&little_cpu_sleep_0>;
530 cpu_pd3: power-domain-cpu3 {
531 #power-domain-cells = <0>;
532 power-domains = <&cluster_pd>;
533 domain-idle-states = <&little_cpu_sleep_0>;
536 cpu_pd4: power-domain-cpu4 {
537 #power-domain-cells = <0>;
538 power-domains = <&cluster_pd>;
539 domain-idle-states = <&big_cpu_sleep_0>;
542 cpu_pd5: power-domain-cpu5 {
543 #power-domain-cells = <0>;
544 power-domains = <&cluster_pd>;
545 domain-idle-states = <&big_cpu_sleep_0>;
548 cpu_pd6: power-domain-cpu6 {
549 #power-domain-cells = <0>;
550 power-domains = <&cluster_pd>;
551 domain-idle-states = <&big_cpu_sleep_0>;
554 cpu_pd7: power-domain-cpu7 {
555 #power-domain-cells = <0>;
556 power-domains = <&cluster_pd>;
557 domain-idle-states = <&big_cpu_sleep_0>;
560 cluster_pd: power-domain-cpu-cluster0 {
561 #power-domain-cells = <0>;
562 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
566 qup_opp_table_100mhz: opp-table-qup {
567 compatible = "operating-points-v2";
569 opp-50000000 {
570 opp-hz = /bits/ 64 <50000000>;
571 required-opps = <&rpmhpd_opp_min_svs>;
574 opp-75000000 {
575 opp-hz = /bits/ 64 <75000000>;
576 required-opps = <&rpmhpd_opp_low_svs>;
579 opp-100000000 {
580 opp-hz = /bits/ 64 <100000000>;
581 required-opps = <&rpmhpd_opp_svs>;
585 reserved_memory: reserved-memory {
586 #address-cells = <2>;
587 #size-cells = <2>;
591 reg = <0x0 0x80000000 0x0 0x600000>;
592 no-map;
596 reg = <0x0 0x80600000 0x0 0x40000>;
597 no-map;
601 reg = <0x0 0x80640000 0x0 0x180000>;
602 no-map;
606 reg = <0x0 0x807c0000 0x0 0x40000>;
607 no-map;
611 reg = <0x0 0x80800000 0x0 0x60000>;
612 no-map;
616 compatible = "qcom,cmd-db";
617 reg = <0x0 0x80860000 0x0 0x20000>;
618 no-map;
622 reg = <0x0 0x80880000 0x0 0x20000>;
623 no-map;
627 reg = <0x0 0x808a0000 0x0 0x40000>;
628 no-map;
632 reg = <0x0 0x808e0000 0x0 0x4000>;
633 no-map;
637 reg = <0x0 0x808e4000 0x0 0x10000>;
638 no-map;
644 reg = <0x0 0x80900000 0x0 0x200000>;
646 no-map;
650 reg = <0x0 0x80b00000 0x0 0x100000>;
651 no-map;
655 reg = <0x0 0x80c00000 0x0 0x4600000>;
656 no-map;
660 reg = <0x0 0x85700000 0x0 0x700000>;
661 no-map;
665 reg = <0x0 0x85e00000 0x0 0x2100000>;
666 no-map;
670 reg = <0x0 0x88000000 0x0 0x1900000>;
671 no-map;
675 reg = <0x0 0x89900000 0x0 0x2000000>;
676 no-map;
680 reg = <0x0 0x8b900000 0x0 0x10000>;
681 no-map;
685 reg = <0x0 0x8b910000 0x0 0xa000>;
686 no-map;
690 reg = <0x0 0x8b91a000 0x0 0x2000>;
691 no-map;
695 reg = <0x0 0x8ba00000 0x0 0x180000>;
696 no-map;
701 reg = <0x0 0x8bb80000 0x0 0x60000>;
702 no-map;
707 reg = <0x0 0x8bbe0000 0x0 0x20000>;
708 no-map;
712 reg = <0x0 0x8bc00000 0x0 0x13200000>;
713 no-map;
717 reg = <0x0 0x9ee00000 0x0 0x700000>;
718 no-map;
722 reg = <0x0 0x9f500000 0x0 0x800000>;
723 no-map;
727 compatible = "qcom,rmtfs-mem";
728 reg = <0x0 0x9fd00000 0x0 0x280000>;
729 no-map;
731 qcom,client-id = <1>;
736 reg = <0x0 0xa6e00000 0x0 0x40000>;
737 no-map;
741 reg = <0x0 0xa6f00000 0x0 0x100000>;
742 no-map;
747 /* Linux kernel image is loaded at 0xa0000000 */
750 reg = <0x0 0xbb000000 0x0 0x5000000>;
751 no-map;
755 reg = <0x0 0xc0000000 0x0 0x20000000>;
756 no-map;
760 reg = <0x0 0xe0000000 0x0 0x600000>;
761 no-map;
765 reg = <0x0 0xe0600000 0x0 0x400000>;
766 no-map;
770 reg = <0x0 0xe0a00000 0x0 0x100000>;
771 no-map;
775 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
776 no-map;
780 reg = <0x0 0xe55f3000 0x0 0x9000>;
781 no-map;
785 reg = <0x0 0xe55fc000 0x0 0x4000>;
786 no-map;
790 reg = <0x0 0xe5600000 0x0 0x100000>;
791 no-map;
795 reg = <0x0 0xe8800000 0x0 0x100000>;
796 no-map;
800 reg = <0x0 0xe8900000 0x0 0x1200000>;
801 no-map;
805 reg = <0x0 0xe9b00000 0x0 0x500000>;
806 no-map;
810 reg = <0x0 0xea000000 0x0 0x3900000>;
811 no-map;
815 reg = <0x0 0xed900000 0x0 0x3b00000>;
816 no-map;
820 smp2p-adsp {
823 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
829 qcom,local-pid = <0>;
830 qcom,remote-pid = <2>;
832 smp2p_adsp_out: master-kernel {
833 qcom,entry-name = "master-kernel";
834 #qcom,smem-state-cells = <1>;
837 smp2p_adsp_in: slave-kernel {
838 qcom,entry-name = "slave-kernel";
839 interrupt-controller;
840 #interrupt-cells = <2>;
844 smp2p-cdsp {
847 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
853 qcom,local-pid = <0>;
854 qcom,remote-pid = <5>;
856 smp2p_cdsp_out: master-kernel {
857 qcom,entry-name = "master-kernel";
858 #qcom,smem-state-cells = <1>;
861 smp2p_cdsp_in: slave-kernel {
862 qcom,entry-name = "slave-kernel";
863 interrupt-controller;
864 #interrupt-cells = <2>;
868 smp2p-modem {
871 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
877 qcom,local-pid = <0>;
878 qcom,remote-pid = <1>;
880 smp2p_modem_out: master-kernel {
881 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells = <1>;
885 smp2p_modem_in: slave-kernel {
886 qcom,entry-name = "slave-kernel";
887 interrupt-controller;
888 #interrupt-cells = <2>;
891 ipa_smp2p_out: ipa-ap-to-modem {
892 qcom,entry-name = "ipa";
893 #qcom,smem-state-cells = <1>;
896 ipa_smp2p_in: ipa-modem-to-ap {
897 qcom,entry-name = "ipa";
898 interrupt-controller;
899 #interrupt-cells = <2>;
903 smp2p-slpi {
906 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
912 qcom,local-pid = <0>;
913 qcom,remote-pid = <3>;
915 smp2p_slpi_out: master-kernel {
916 qcom,entry-name = "master-kernel";
917 #qcom,smem-state-cells = <1>;
920 smp2p_slpi_in: slave-kernel {
921 qcom,entry-name = "slave-kernel";
922 interrupt-controller;
923 #interrupt-cells = <2>;
927 soc: soc@0 {
928 #address-cells = <2>;
929 #size-cells = <2>;
930 ranges = <0 0 0 0 0x10 0>;
931 dma-ranges = <0 0 0 0 0x10 0>;
932 compatible = "simple-bus";
934 gcc: clock-controller@100000 {
935 compatible = "qcom,gcc-sm8450";
936 reg = <0x0 0x00100000 0x0 0x1f4200>;
937 #clock-cells = <1>;
938 #reset-cells = <1>;
939 #power-domain-cells = <1>;
945 <&ufs_mem_phy 0>,
949 clock-names = "bi_tcxo",
960 gpi_dma2: dma-controller@800000 {
961 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
962 #dma-cells = <3>;
963 reg = <0 0x00800000 0 0x60000>;
976 dma-channels = <12>;
977 dma-channel-mask = <0x7e>;
978 iommus = <&apps_smmu 0x496 0x0>;
983 compatible = "qcom,geni-se-qup";
984 reg = <0x0 0x008c0000 0x0 0x2000>;
985 clock-names = "m-ahb", "s-ahb";
988 iommus = <&apps_smmu 0x483 0x0>;
989 #address-cells = <2>;
990 #size-cells = <2>;
995 compatible = "qcom,geni-i2c";
996 reg = <0x0 0x00880000 0x0 0x4000>;
997 clock-names = "se";
999 pinctrl-names = "default";
1000 pinctrl-0 = <&qup_i2c15_data_clk>;
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1005 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1006 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1007 interconnect-names = "qup-core", "qup-config", "qup-memory";
1008 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1009 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1010 dma-names = "tx", "rx";
1015 compatible = "qcom,geni-spi";
1016 reg = <0x0 0x00880000 0x0 0x4000>;
1017 clock-names = "se";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1022 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1023 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1024 interconnect-names = "qup-core", "qup-config";
1025 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1026 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1027 dma-names = "tx", "rx";
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1034 compatible = "qcom,geni-i2c";
1035 reg = <0x0 0x00884000 0x0 0x4000>;
1036 clock-names = "se";
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&qup_i2c16_data_clk>;
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1044 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1045 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect-names = "qup-core", "qup-config", "qup-memory";
1047 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1049 dma-names = "tx", "rx";
1054 compatible = "qcom,geni-spi";
1055 reg = <0x0 0x00884000 0x0 0x4000>;
1056 clock-names = "se";
1059 pinctrl-names = "default";
1060 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1062 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1063 interconnect-names = "qup-core", "qup-config";
1064 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1066 dma-names = "tx", "rx";
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1073 compatible = "qcom,geni-i2c";
1074 reg = <0x0 0x00888000 0x0 0x4000>;
1075 clock-names = "se";
1077 pinctrl-names = "default";
1078 pinctrl-0 = <&qup_i2c17_data_clk>;
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1083 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1084 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1085 interconnect-names = "qup-core", "qup-config", "qup-memory";
1086 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1088 dma-names = "tx", "rx";
1093 compatible = "qcom,geni-spi";
1094 reg = <0x0 0x00888000 0x0 0x4000>;
1095 clock-names = "se";
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
1100 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1101 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1102 interconnect-names = "qup-core", "qup-config";
1103 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1105 dma-names = "tx", "rx";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1112 compatible = "qcom,geni-i2c";
1113 reg = <0x0 0x0088c000 0x0 0x4000>;
1114 clock-names = "se";
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&qup_i2c18_data_clk>;
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1122 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1123 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1124 interconnect-names = "qup-core", "qup-config", "qup-memory";
1125 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1127 dma-names = "tx", "rx";
1132 compatible = "qcom,geni-spi";
1133 reg = <0 0x0088c000 0 0x4000>;
1134 clock-names = "se";
1137 pinctrl-names = "default";
1138 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1139 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1140 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1141 interconnect-names = "qup-core", "qup-config";
1142 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1144 dma-names = "tx", "rx";
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1151 compatible = "qcom,geni-i2c";
1152 reg = <0x0 0x00890000 0x0 0x4000>;
1153 clock-names = "se";
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&qup_i2c19_data_clk>;
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1160 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1161 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1162 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1163 interconnect-names = "qup-core", "qup-config", "qup-memory";
1164 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1166 dma-names = "tx", "rx";
1171 compatible = "qcom,geni-spi";
1172 reg = <0 0x00890000 0 0x4000>;
1173 clock-names = "se";
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1178 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1179 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1180 interconnect-names = "qup-core", "qup-config";
1181 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1183 dma-names = "tx", "rx";
1184 #address-cells = <1>;
1185 #size-cells = <0>;
1190 compatible = "qcom,geni-i2c";
1191 reg = <0x0 0x00894000 0x0 0x4000>;
1192 clock-names = "se";
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&qup_i2c20_data_clk>;
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1200 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1201 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1202 interconnect-names = "qup-core", "qup-config", "qup-memory";
1203 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1205 dma-names = "tx", "rx";
1210 compatible = "qcom,geni-uart";
1211 reg = <0 0x00894000 0 0x4000>;
1212 clock-names = "se";
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&qup_uart20_default>;
1221 interconnect-names = "qup-core",
1222 "qup-config";
1227 compatible = "qcom,geni-spi";
1228 reg = <0 0x00894000 0 0x4000>;
1229 clock-names = "se";
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1234 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1235 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1236 interconnect-names = "qup-core", "qup-config";
1237 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1239 dma-names = "tx", "rx";
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1246 compatible = "qcom,geni-i2c";
1247 reg = <0x0 0x00898000 0x0 0x4000>;
1248 clock-names = "se";
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&qup_i2c21_data_clk>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1255 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1256 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1257 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1258 interconnect-names = "qup-core", "qup-config", "qup-memory";
1259 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1261 dma-names = "tx", "rx";
1266 compatible = "qcom,geni-spi";
1267 reg = <0 0x00898000 0 0x4000>;
1268 clock-names = "se";
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1273 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1274 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1275 interconnect-names = "qup-core", "qup-config";
1276 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1278 dma-names = "tx", "rx";
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1285 gpi_dma0: dma-controller@900000 {
1286 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1287 #dma-cells = <3>;
1288 reg = <0 0x00900000 0 0x60000>;
1301 dma-channels = <12>;
1302 dma-channel-mask = <0x7e>;
1303 iommus = <&apps_smmu 0x5b6 0x0>;
1308 compatible = "qcom,geni-se-qup";
1309 reg = <0x0 0x009c0000 0x0 0x2000>;
1310 clock-names = "m-ahb", "s-ahb";
1313 iommus = <&apps_smmu 0x5a3 0x0>;
1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1315 interconnect-names = "qup-core";
1316 #address-cells = <2>;
1317 #size-cells = <2>;
1322 compatible = "qcom,geni-i2c";
1323 reg = <0x0 0x00980000 0x0 0x4000>;
1324 clock-names = "se";
1326 pinctrl-names = "default";
1327 pinctrl-0 = <&qup_i2c0_data_clk>;
1329 #address-cells = <1>;
1330 #size-cells = <0>;
1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1332 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1333 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1334 interconnect-names = "qup-core", "qup-config", "qup-memory";
1335 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1336 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1337 dma-names = "tx", "rx";
1342 compatible = "qcom,geni-spi";
1343 reg = <0x0 0x00980000 0x0 0x4000>;
1344 clock-names = "se";
1347 pinctrl-names = "default";
1348 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1349 power-domains = <&rpmhpd RPMHPD_CX>;
1350 operating-points-v2 = <&qup_opp_table_100mhz>;
1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1352 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1353 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1354 interconnect-names = "qup-core", "qup-config", "qup-memory";
1355 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1356 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1357 dma-names = "tx", "rx";
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1364 compatible = "qcom,geni-i2c";
1365 reg = <0x0 0x00984000 0x0 0x4000>;
1366 clock-names = "se";
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&qup_i2c1_data_clk>;
1371 #address-cells = <1>;
1372 #size-cells = <0>;
1373 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1374 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1375 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1376 interconnect-names = "qup-core", "qup-config", "qup-memory";
1377 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1379 dma-names = "tx", "rx";
1384 compatible = "qcom,geni-spi";
1385 reg = <0x0 0x00984000 0x0 0x4000>;
1386 clock-names = "se";
1389 pinctrl-names = "default";
1390 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1397 dma-names = "tx", "rx";
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1404 compatible = "qcom,geni-i2c";
1405 reg = <0x0 0x00988000 0x0 0x4000>;
1406 clock-names = "se";
1408 pinctrl-names = "default";
1409 pinctrl-0 = <&qup_i2c2_data_clk>;
1411 #address-cells = <1>;
1412 #size-cells = <0>;
1413 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1414 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1415 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1416 interconnect-names = "qup-core", "qup-config", "qup-memory";
1417 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1419 dma-names = "tx", "rx";
1424 compatible = "qcom,geni-spi";
1425 reg = <0x0 0x00988000 0x0 0x4000>;
1426 clock-names = "se";
1429 pinctrl-names = "default";
1430 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1431 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1432 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1433 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1434 interconnect-names = "qup-core", "qup-config", "qup-memory";
1435 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1437 dma-names = "tx", "rx";
1438 #address-cells = <1>;
1439 #size-cells = <0>;
1445 compatible = "qcom,geni-i2c";
1446 reg = <0x0 0x0098c000 0x0 0x4000>;
1447 clock-names = "se";
1449 pinctrl-names = "default";
1450 pinctrl-0 = <&qup_i2c3_data_clk>;
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1454 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1455 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1456 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1457 interconnect-names = "qup-core", "qup-config", "qup-memory";
1458 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1460 dma-names = "tx", "rx";
1465 compatible = "qcom,geni-spi";
1466 reg = <0x0 0x0098c000 0x0 0x4000>;
1467 clock-names = "se";
1470 pinctrl-names = "default";
1471 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1472 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1473 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1474 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1475 interconnect-names = "qup-core", "qup-config", "qup-memory";
1476 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1478 dma-names = "tx", "rx";
1479 #address-cells = <1>;
1480 #size-cells = <0>;
1485 compatible = "qcom,geni-i2c";
1486 reg = <0x0 0x00990000 0x0 0x4000>;
1487 clock-names = "se";
1489 pinctrl-names = "default";
1490 pinctrl-0 = <&qup_i2c4_data_clk>;
1492 #address-cells = <1>;
1493 #size-cells = <0>;
1494 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1495 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1496 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1497 interconnect-names = "qup-core", "qup-config", "qup-memory";
1498 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1500 dma-names = "tx", "rx";
1505 compatible = "qcom,geni-spi";
1506 reg = <0x0 0x00990000 0x0 0x4000>;
1507 clock-names = "se";
1510 pinctrl-names = "default";
1511 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1512 power-domains = <&rpmhpd RPMHPD_CX>;
1513 operating-points-v2 = <&qup_opp_table_100mhz>;
1514 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1515 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1516 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1517 interconnect-names = "qup-core", "qup-config", "qup-memory";
1518 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1520 dma-names = "tx", "rx";
1521 #address-cells = <1>;
1522 #size-cells = <0>;
1527 compatible = "qcom,geni-i2c";
1528 reg = <0x0 0x00994000 0x0 0x4000>;
1529 clock-names = "se";
1531 pinctrl-names = "default";
1532 pinctrl-0 = <&qup_i2c5_data_clk>;
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1536 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1537 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1538 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1539 interconnect-names = "qup-core", "qup-config", "qup-memory";
1540 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1542 dma-names = "tx", "rx";
1547 compatible = "qcom,geni-spi";
1548 reg = <0x0 0x00994000 0x0 0x4000>;
1549 clock-names = "se";
1552 pinctrl-names = "default";
1553 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1554 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1555 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1556 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1557 interconnect-names = "qup-core", "qup-config", "qup-memory";
1558 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1560 dma-names = "tx", "rx";
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1568 compatible = "qcom,geni-i2c";
1569 reg = <0x0 0x00998000 0x0 0x4000>;
1570 clock-names = "se";
1572 pinctrl-names = "default";
1573 pinctrl-0 = <&qup_i2c6_data_clk>;
1575 #address-cells = <1>;
1576 #size-cells = <0>;
1577 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1578 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1579 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1580 interconnect-names = "qup-core", "qup-config", "qup-memory";
1581 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1583 dma-names = "tx", "rx";
1588 compatible = "qcom,geni-spi";
1589 reg = <0x0 0x00998000 0x0 0x4000>;
1590 clock-names = "se";
1593 pinctrl-names = "default";
1594 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1595 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1596 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1597 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1598 interconnect-names = "qup-core", "qup-config", "qup-memory";
1599 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1601 dma-names = "tx", "rx";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1608 compatible = "qcom,geni-debug-uart";
1609 reg = <0 0x0099c000 0 0x4000>;
1610 clock-names = "se";
1612 pinctrl-names = "default";
1613 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1619 interconnect-names = "qup-core",
1620 "qup-config";
1625 gpi_dma1: dma-controller@a00000 {
1626 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1627 #dma-cells = <3>;
1628 reg = <0 0x00a00000 0 0x60000>;
1641 dma-channels = <12>;
1642 dma-channel-mask = <0x7e>;
1643 iommus = <&apps_smmu 0x56 0x0>;
1648 compatible = "qcom,geni-se-qup";
1649 reg = <0x0 0x00ac0000 0x0 0x6000>;
1650 clock-names = "m-ahb", "s-ahb";
1653 iommus = <&apps_smmu 0x43 0x0>;
1654 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1655 interconnect-names = "qup-core";
1656 #address-cells = <2>;
1657 #size-cells = <2>;
1662 compatible = "qcom,geni-i2c";
1663 reg = <0x0 0x00a80000 0x0 0x4000>;
1664 clock-names = "se";
1666 pinctrl-names = "default";
1667 pinctrl-0 = <&qup_i2c8_data_clk>;
1669 #address-cells = <1>;
1670 #size-cells = <0>;
1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1672 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1673 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1674 interconnect-names = "qup-core", "qup-config", "qup-memory";
1675 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1676 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1677 dma-names = "tx", "rx";
1682 compatible = "qcom,geni-spi";
1683 reg = <0x0 0x00a80000 0x0 0x4000>;
1684 clock-names = "se";
1687 pinctrl-names = "default";
1688 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1689 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1690 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1691 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1692 interconnect-names = "qup-core", "qup-config", "qup-memory";
1693 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1694 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1695 dma-names = "tx", "rx";
1696 #address-cells = <1>;
1697 #size-cells = <0>;
1702 compatible = "qcom,geni-i2c";
1703 reg = <0x0 0x00a84000 0x0 0x4000>;
1704 clock-names = "se";
1706 pinctrl-names = "default";
1707 pinctrl-0 = <&qup_i2c9_data_clk>;
1709 #address-cells = <1>;
1710 #size-cells = <0>;
1711 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1712 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1713 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1714 interconnect-names = "qup-core", "qup-config", "qup-memory";
1715 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1717 dma-names = "tx", "rx";
1722 compatible = "qcom,geni-spi";
1723 reg = <0x0 0x00a84000 0x0 0x4000>;
1724 clock-names = "se";
1727 pinctrl-names = "default";
1728 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1729 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1730 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1731 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1732 interconnect-names = "qup-core", "qup-config", "qup-memory";
1733 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1735 dma-names = "tx", "rx";
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1742 compatible = "qcom,geni-i2c";
1743 reg = <0x0 0x00a88000 0x0 0x4000>;
1744 clock-names = "se";
1746 pinctrl-names = "default";
1747 pinctrl-0 = <&qup_i2c10_data_clk>;
1749 #address-cells = <1>;
1750 #size-cells = <0>;
1751 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1752 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1753 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1754 interconnect-names = "qup-core", "qup-config", "qup-memory";
1755 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1757 dma-names = "tx", "rx";
1762 compatible = "qcom,geni-spi";
1763 reg = <0x0 0x00a88000 0x0 0x4000>;
1764 clock-names = "se";
1767 pinctrl-names = "default";
1768 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1769 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1770 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1771 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1772 interconnect-names = "qup-core", "qup-config", "qup-memory";
1773 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1775 dma-names = "tx", "rx";
1776 #address-cells = <1>;
1777 #size-cells = <0>;
1782 compatible = "qcom,geni-i2c";
1783 reg = <0x0 0x00a8c000 0x0 0x4000>;
1784 clock-names = "se";
1786 pinctrl-names = "default";
1787 pinctrl-0 = <&qup_i2c11_data_clk>;
1789 #address-cells = <1>;
1790 #size-cells = <0>;
1791 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1792 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1793 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1794 interconnect-names = "qup-core", "qup-config", "qup-memory";
1795 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1797 dma-names = "tx", "rx";
1802 compatible = "qcom,geni-spi";
1803 reg = <0x0 0x00a8c000 0x0 0x4000>;
1804 clock-names = "se";
1807 pinctrl-names = "default";
1808 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1809 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1810 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1811 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1812 interconnect-names = "qup-core", "qup-config", "qup-memory";
1813 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1815 dma-names = "tx", "rx";
1816 #address-cells = <1>;
1817 #size-cells = <0>;
1822 compatible = "qcom,geni-i2c";
1823 reg = <0x0 0x00a90000 0x0 0x4000>;
1824 clock-names = "se";
1826 pinctrl-names = "default";
1827 pinctrl-0 = <&qup_i2c12_data_clk>;
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1831 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1832 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1833 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1834 interconnect-names = "qup-core", "qup-config", "qup-memory";
1835 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1837 dma-names = "tx", "rx";
1842 compatible = "qcom,geni-spi";
1843 reg = <0x0 0x00a90000 0x0 0x4000>;
1844 clock-names = "se";
1847 pinctrl-names = "default";
1848 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1850 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1851 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1852 interconnect-names = "qup-core", "qup-config", "qup-memory";
1853 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1855 dma-names = "tx", "rx";
1856 #address-cells = <1>;
1857 #size-cells = <0>;
1862 compatible = "qcom,geni-i2c";
1863 reg = <0 0x00a94000 0 0x4000>;
1864 clock-names = "se";
1866 pinctrl-names = "default";
1867 pinctrl-0 = <&qup_i2c13_data_clk>;
1869 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1870 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1871 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1872 interconnect-names = "qup-core", "qup-config", "qup-memory";
1873 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1875 dma-names = "tx", "rx";
1876 #address-cells = <1>;
1877 #size-cells = <0>;
1882 compatible = "qcom,geni-spi";
1883 reg = <0x0 0x00a94000 0x0 0x4000>;
1884 clock-names = "se";
1887 pinctrl-names = "default";
1888 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1889 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1890 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1891 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1892 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1895 dma-names = "tx", "rx";
1896 #address-cells = <1>;
1897 #size-cells = <0>;
1902 compatible = "qcom,geni-i2c";
1903 reg = <0 0x00a98000 0 0x4000>;
1904 clock-names = "se";
1906 pinctrl-names = "default";
1907 pinctrl-0 = <&qup_i2c14_data_clk>;
1909 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1910 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1911 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1912 interconnect-names = "qup-core", "qup-config", "qup-memory";
1913 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1915 dma-names = "tx", "rx";
1916 #address-cells = <1>;
1917 #size-cells = <0>;
1922 compatible = "qcom,geni-spi";
1923 reg = <0x0 0x00a98000 0x0 0x4000>;
1924 clock-names = "se";
1927 pinctrl-names = "default";
1928 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1929 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1930 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1931 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1932 interconnect-names = "qup-core", "qup-config", "qup-memory";
1933 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1935 dma-names = "tx", "rx";
1936 #address-cells = <1>;
1937 #size-cells = <0>;
1943 compatible = "qcom,sm8450-trng", "qcom,trng";
1944 reg = <0 0x010c3000 0 0x1000>;
1948 compatible = "qcom,pcie-sm8450-pcie0";
1949 reg = <0 0x01c00000 0 0x3000>,
1950 <0 0x60000000 0 0xf1d>,
1951 <0 0x60000f20 0 0xa8>,
1952 <0 0x60001000 0 0x1000>,
1953 <0 0x60100000 0 0x100000>;
1954 reg-names = "parf", "dbi", "elbi", "atu", "config";
1956 linux,pci-domain = <0>;
1957 bus-range = <0x00 0xff>;
1958 num-lanes = <1>;
1960 #address-cells = <3>;
1961 #size-cells = <2>;
1963 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1964 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1966 msi-map = <0x0 &gic_its 0x5980 0x1>,
1967 <0x100 &gic_its 0x5981 0x1>;
1968 msi-map-mask = <0xff00>;
1978 interrupt-names = "msi0",
1987 #interrupt-cells = <1>;
1988 interrupt-map-mask = <0 0 0 0x7>;
1989 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1990 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1991 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1992 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1998 interconnect-names = "pcie-mem", "cpu-pcie";
2012 clock-names = "pipe",
2025 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2026 <0x100 &apps_smmu 0x1c01 0x1>;
2029 reset-names = "pci";
2031 power-domains = <&gcc PCIE_0_GDSC>;
2034 phy-names = "pciephy";
2036 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
2037 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
2039 pinctrl-names = "default";
2040 pinctrl-0 = <&pcie0_default_state>;
2042 operating-points-v2 = <&pcie0_opp_table>;
2046 pcie0_opp_table: opp-table {
2047 compatible = "operating-points-v2";
2050 opp-2500000 {
2051 opp-hz = /bits/ 64 <2500000>;
2052 required-opps = <&rpmhpd_opp_low_svs>;
2053 opp-peak-kBps = <250000 1>;
2057 opp-5000000 {
2058 opp-hz = /bits/ 64 <5000000>;
2059 required-opps = <&rpmhpd_opp_low_svs>;
2060 opp-peak-kBps = <500000 1>;
2064 opp-8000000 {
2065 opp-hz = /bits/ 64 <8000000>;
2066 required-opps = <&rpmhpd_opp_nom>;
2067 opp-peak-kBps = <984500 1>;
2071 pcieport0: pcie@0 {
2073 reg = <0x0 0x0 0x0 0x0 0x0>;
2074 bus-range = <0x01 0xff>;
2076 #address-cells = <3>;
2077 #size-cells = <2>;
2083 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
2084 reg = <0 0x01c06000 0 0x2000>;
2091 clock-names = "aux",
2097 clock-output-names = "pcie_0_pipe_clk";
2098 #clock-cells = <0>;
2100 #phy-cells = <0>;
2103 reset-names = "phy";
2105 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2106 assigned-clock-rates = <100000000>;
2112 compatible = "qcom,pcie-sm8450-pcie1";
2113 reg = <0 0x01c08000 0 0x3000>,
2114 <0 0x40000000 0 0xf1d>,
2115 <0 0x40000f20 0 0xa8>,
2116 <0 0x40001000 0 0x1000>,
2117 <0 0x40100000 0 0x100000>;
2118 reg-names = "parf", "dbi", "elbi", "atu", "config";
2120 linux,pci-domain = <1>;
2121 bus-range = <0x00 0xff>;
2122 num-lanes = <2>;
2124 #address-cells = <3>;
2125 #size-cells = <2>;
2127 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2128 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2130 msi-map = <0x0 &gic_its 0x5a00 0x1>,
2131 <0x100 &gic_its 0x5a01 0x1>;
2132 msi-map-mask = <0xff00>;
2142 interrupt-names = "msi0",
2151 #interrupt-cells = <1>;
2152 interrupt-map-mask = <0 0 0 0x7>;
2153 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2154 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2155 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2156 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2162 interconnect-names = "pcie-mem", "cpu-pcie";
2175 clock-names = "pipe",
2187 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2188 <0x100 &apps_smmu 0x1c81 0x1>;
2191 reset-names = "pci";
2193 power-domains = <&gcc PCIE_1_GDSC>;
2196 phy-names = "pciephy";
2198 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2199 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2201 pinctrl-names = "default";
2202 pinctrl-0 = <&pcie1_default_state>;
2204 operating-points-v2 = <&pcie1_opp_table>;
2208 pcie1_opp_table: opp-table {
2209 compatible = "operating-points-v2";
2212 opp-2500000 {
2213 opp-hz = /bits/ 64 <2500000>;
2214 required-opps = <&rpmhpd_opp_low_svs>;
2215 opp-peak-kBps = <250000 1>;
2219 opp-5000000 {
2220 opp-hz = /bits/ 64 <5000000>;
2221 required-opps = <&rpmhpd_opp_low_svs>;
2222 opp-peak-kBps = <500000 1>;
2226 opp-10000000 {
2227 opp-hz = /bits/ 64 <10000000>;
2228 required-opps = <&rpmhpd_opp_low_svs>;
2229 opp-peak-kBps = <1000000 1>;
2233 opp-8000000 {
2234 opp-hz = /bits/ 64 <8000000>;
2235 required-opps = <&rpmhpd_opp_nom>;
2236 opp-peak-kBps = <984500 1>;
2240 opp-16000000 {
2241 opp-hz = /bits/ 64 <16000000>;
2242 required-opps = <&rpmhpd_opp_nom>;
2243 opp-peak-kBps = <1969000 1>;
2247 opp-32000000 {
2248 opp-hz = /bits/ 64 <32000000>;
2249 required-opps = <&rpmhpd_opp_nom>;
2250 opp-peak-kBps = <3938000 1>;
2254 pcie@0 {
2256 reg = <0x0 0x0 0x0 0x0 0x0>;
2257 bus-range = <0x01 0xff>;
2259 #address-cells = <3>;
2260 #size-cells = <2>;
2266 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2267 reg = <0 0x01c0e000 0 0x2000>;
2274 clock-names = "aux",
2280 clock-output-names = "pcie_1_pipe_clk";
2281 #clock-cells = <1>;
2283 #phy-cells = <0>;
2286 reset-names = "phy";
2288 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2289 assigned-clock-rates = <100000000>;
2295 compatible = "qcom,sm8450-config-noc";
2296 reg = <0 0x01500000 0 0x1c000>;
2297 #interconnect-cells = <2>;
2298 qcom,bcm-voters = <&apps_bcm_voter>;
2302 compatible = "qcom,sm8450-system-noc";
2303 reg = <0 0x01680000 0 0x1e200>;
2304 #interconnect-cells = <2>;
2305 qcom,bcm-voters = <&apps_bcm_voter>;
2309 compatible = "qcom,sm8450-pcie-anoc";
2310 reg = <0 0x016c0000 0 0xe280>;
2311 #interconnect-cells = <2>;
2312 qcom,bcm-voters = <&apps_bcm_voter>;
2316 compatible = "qcom,sm8450-aggre1-noc";
2317 reg = <0 0x016e0000 0 0x1c080>;
2318 #interconnect-cells = <2>;
2321 qcom,bcm-voters = <&apps_bcm_voter>;
2325 compatible = "qcom,sm8450-aggre2-noc";
2326 reg = <0 0x01700000 0 0x31080>;
2327 #interconnect-cells = <2>;
2328 qcom,bcm-voters = <&apps_bcm_voter>;
2336 compatible = "qcom,sm8450-mmss-noc";
2337 reg = <0 0x01740000 0 0x1f080>;
2338 #interconnect-cells = <2>;
2339 qcom,bcm-voters = <&apps_bcm_voter>;
2343 compatible = "qcom,tcsr-mutex";
2344 reg = <0x0 0x01f40000 0x0 0x40000>;
2345 #hwlock-cells = <1>;
2349 compatible = "qcom,sm8450-tcsr", "syscon";
2350 reg = <0x0 0x1fc0000 0x0 0x30000>;
2354 compatible = "qcom,adreno-730.1", "qcom,adreno";
2355 reg = <0x0 0x03d00000 0x0 0x40000>,
2356 <0x0 0x03d9e000 0x0 0x1000>,
2357 <0x0 0x03d61000 0x0 0x800>;
2358 reg-names = "kgsl_3d0_reg_memory",
2364 iommus = <&adreno_smmu 0 0x400>,
2365 <&adreno_smmu 1 0x400>;
2367 operating-points-v2 = <&gpu_opp_table>;
2370 #cooling-cells = <2>;
2374 zap-shader {
2375 memory-region = <&gpu_micro_code_mem>;
2378 gpu_opp_table: opp-table {
2379 compatible = "operating-points-v2";
2381 opp-818000000 {
2382 opp-hz = /bits/ 64 <818000000>;
2383 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2386 opp-791000000 {
2387 opp-hz = /bits/ 64 <791000000>;
2388 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2391 opp-734000000 {
2392 opp-hz = /bits/ 64 <734000000>;
2393 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2396 opp-640000000 {
2397 opp-hz = /bits/ 64 <640000000>;
2398 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2401 opp-599000000 {
2402 opp-hz = /bits/ 64 <599000000>;
2403 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2406 opp-545000000 {
2407 opp-hz = /bits/ 64 <545000000>;
2408 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2411 opp-492000000 {
2412 opp-hz = /bits/ 64 <492000000>;
2413 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2416 opp-421000000 {
2417 opp-hz = /bits/ 64 <421000000>;
2418 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2421 opp-350000000 {
2422 opp-hz = /bits/ 64 <350000000>;
2423 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2426 opp-317000000 {
2427 opp-hz = /bits/ 64 <317000000>;
2428 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2431 opp-285000000 {
2432 opp-hz = /bits/ 64 <285000000>;
2433 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2436 opp-220000000 {
2437 opp-hz = /bits/ 64 <220000000>;
2438 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2444 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2445 reg = <0x0 0x03d6a000 0x0 0x35000>,
2446 <0x0 0x03d50000 0x0 0x10000>,
2447 <0x0 0x0b290000 0x0 0x10000>;
2448 reg-names = "gmu", "rscc", "gmu_pdc";
2452 interrupt-names = "hfi", "gmu";
2461 clock-names = "ahb",
2469 power-domains = <&gpucc GPU_CX_GDSC>,
2471 power-domain-names = "cx",
2474 iommus = <&adreno_smmu 5 0x400>;
2478 operating-points-v2 = <&gmu_opp_table>;
2480 gmu_opp_table: opp-table {
2481 compatible = "operating-points-v2";
2483 opp-500000000 {
2484 opp-hz = /bits/ 64 <500000000>;
2485 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2488 opp-200000000 {
2489 opp-hz = /bits/ 64 <200000000>;
2490 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2495 gpucc: clock-controller@3d90000 {
2496 compatible = "qcom,sm8450-gpucc";
2497 reg = <0x0 0x03d90000 0x0 0xa000>;
2501 #clock-cells = <1>;
2502 #reset-cells = <1>;
2503 #power-domain-cells = <1>;
2507 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2508 "qcom,smmu-500", "arm,mmu-500";
2509 reg = <0x0 0x03da0000 0x0 0x40000>;
2510 #iommu-cells = <2>;
2511 #global-interrupts = <1>;
2544 clock-names = "gmu",
2550 power-domains = <&gpucc GPU_CX_GDSC>;
2551 dma-coherent;
2555 compatible = "qcom,sm8450-usb-hs-phy",
2556 "qcom,usb-snps-hs-7nm-phy";
2557 reg = <0 0x088e3000 0 0x400>;
2559 #phy-cells = <0>;
2562 clock-names = "ref";
2568 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2569 reg = <0 0x088e8000 0 0x3000>;
2575 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2579 reset-names = "phy", "common";
2581 #clock-cells = <1>;
2582 #phy-cells = <1>;
2584 orientation-switch;
2589 #address-cells = <1>;
2590 #size-cells = <0>;
2592 port@0 {
2593 reg = <0>;
2603 remote-endpoint = <&usb_1_dwc3_ss>;
2611 remote-endpoint = <&mdss_dp0_out>;
2618 compatible = "qcom,sm8450-slpi-pas";
2619 reg = <0 0x02400000 0 0x4000>;
2621 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2622 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2626 interrupt-names = "wdog", "fatal", "ready",
2627 "handover", "stop-ack";
2630 clock-names = "xo";
2632 power-domains = <&rpmhpd RPMHPD_LCX>,
2634 power-domain-names = "lcx", "lmx";
2636 memory-region = <&slpi_mem>;
2640 qcom,smem-states = <&smp2p_slpi_out 0>;
2641 qcom,smem-state-names = "stop";
2645 glink-edge {
2646 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2653 qcom,remote-pid = <3>;
2657 qcom,glink-channels = "fastrpcglink-apps-dsp";
2659 qcom,non-secure-domain;
2660 #address-cells = <1>;
2661 #size-cells = <0>;
2663 compute-cb@1 {
2664 compatible = "qcom,fastrpc-compute-cb";
2666 iommus = <&apps_smmu 0x0541 0x0>;
2669 compute-cb@2 {
2670 compatible = "qcom,fastrpc-compute-cb";
2672 iommus = <&apps_smmu 0x0542 0x0>;
2675 compute-cb@3 {
2676 compatible = "qcom,fastrpc-compute-cb";
2678 iommus = <&apps_smmu 0x0543 0x0>;
2679 /* note: shared-cb = <4> in downstream */
2686 compatible = "qcom,sm8450-adsp-pas";
2687 reg = <0x0 0x03000000 0x0 0x10000>;
2689 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2690 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2694 interrupt-names = "wdog", "fatal", "ready",
2695 "handover", "stop-ack";
2698 clock-names = "xo";
2700 power-domains = <&rpmhpd RPMHPD_LCX>,
2702 power-domain-names = "lcx", "lmx";
2704 memory-region = <&adsp_mem>;
2708 qcom,smem-states = <&smp2p_adsp_out 0>;
2709 qcom,smem-state-names = "stop";
2713 remoteproc_adsp_glink: glink-edge {
2714 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 qcom,remote-pid = <2>;
2725 qcom,glink-channels = "adsp_apps";
2728 #address-cells = <1>;
2729 #size-cells = <0>;
2734 #sound-dai-cells = <0>;
2735 qcom,protection-domain = "avs/audio",
2739 compatible = "qcom,q6apm-dais";
2740 iommus = <&apps_smmu 0x1801 0x0>;
2744 compatible = "qcom,q6apm-lpass-dais";
2745 #sound-dai-cells = <1>;
2752 qcom,protection-domain = "avs/audio",
2755 q6prmcc: clock-controller {
2756 compatible = "qcom,q6prm-lpass-clocks";
2757 #clock-cells = <2>;
2764 qcom,glink-channels = "fastrpcglink-apps-dsp";
2766 qcom,non-secure-domain;
2767 #address-cells = <1>;
2768 #size-cells = <0>;
2770 compute-cb@3 {
2771 compatible = "qcom,fastrpc-compute-cb";
2773 iommus = <&apps_smmu 0x1803 0x0>;
2776 compute-cb@4 {
2777 compatible = "qcom,fastrpc-compute-cb";
2779 iommus = <&apps_smmu 0x1804 0x0>;
2782 compute-cb@5 {
2783 compatible = "qcom,fastrpc-compute-cb";
2785 iommus = <&apps_smmu 0x1805 0x0>;
2792 compatible = "qcom,sm8450-lpass-wsa-macro";
2793 reg = <0 0x031e0000 0 0x1000>;
2799 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2801 #clock-cells = <0>;
2802 clock-output-names = "wsa2-mclk";
2803 #sound-dai-cells = <1>;
2807 compatible = "qcom,soundwire-v1.7.0";
2808 reg = <0 0x031f0000 0 0x2000>;
2811 clock-names = "iface";
2814 pinctrl-0 = <&wsa2_swr_active>;
2815 pinctrl-names = "default";
2817 qcom,din-ports = <2>;
2818 qcom,dout-ports = <6>;
2820 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2821 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2822 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2823 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2824 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2825 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2826 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2827 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2828 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2830 #address-cells = <2>;
2831 #size-cells = <0>;
2832 #sound-dai-cells = <1>;
2837 compatible = "qcom,sm8450-lpass-rx-macro";
2838 reg = <0 0x03200000 0 0x1000>;
2844 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2846 #clock-cells = <0>;
2847 clock-output-names = "mclk";
2848 #sound-dai-cells = <1>;
2852 compatible = "qcom,soundwire-v1.7.0";
2853 reg = <0 0x03210000 0 0x2000>;
2856 clock-names = "iface";
2858 qcom,din-ports = <0>;
2859 qcom,dout-ports = <5>;
2861 pinctrl-0 = <&rx_swr_active>;
2862 pinctrl-names = "default";
2864 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2865 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2866 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2867 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2868 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2869 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2870 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2871 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2872 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2874 #address-cells = <2>;
2875 #size-cells = <0>;
2876 #sound-dai-cells = <1>;
2881 compatible = "qcom,sm8450-lpass-tx-macro";
2882 reg = <0 0x03220000 0 0x1000>;
2888 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2890 #clock-cells = <0>;
2891 clock-output-names = "mclk";
2892 #sound-dai-cells = <1>;
2896 compatible = "qcom,sm8450-lpass-wsa-macro";
2897 reg = <0 0x03240000 0 0x1000>;
2903 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2905 #clock-cells = <0>;
2906 clock-output-names = "mclk";
2907 #sound-dai-cells = <1>;
2911 compatible = "qcom,soundwire-v1.7.0";
2912 reg = <0 0x03250000 0 0x2000>;
2915 clock-names = "iface";
2918 pinctrl-0 = <&wsa_swr_active>;
2919 pinctrl-names = "default";
2921 qcom,din-ports = <2>;
2922 qcom,dout-ports = <6>;
2924 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2925 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2926 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2927 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2928 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2929 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2930 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2931 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2932 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2934 #address-cells = <2>;
2935 #size-cells = <0>;
2936 #sound-dai-cells = <1>;
2941 compatible = "qcom,soundwire-v1.7.0";
2942 reg = <0 0x033b0000 0 0x2000>;
2945 interrupt-names = "core", "wakeup";
2948 clock-names = "iface";
2951 pinctrl-0 = <&tx_swr_active>;
2952 pinctrl-names = "default";
2954 qcom,din-ports = <4>;
2955 qcom,dout-ports = <0>;
2956 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2957 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2958 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2959 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2960 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2961 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2962 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2963 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2964 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2966 #address-cells = <2>;
2967 #size-cells = <0>;
2968 #sound-dai-cells = <1>;
2973 compatible = "qcom,sm8450-lpass-va-macro";
2974 reg = <0 0x033f0000 0 0x1000>;
2979 clock-names = "mclk", "macro", "dcodec", "npl";
2981 #clock-cells = <0>;
2982 clock-output-names = "fsgen";
2983 #sound-dai-cells = <1>;
2988 compatible = "qcom,sm8450-cdsp-pas";
2989 reg = <0 0x32300000 0 0x10000>;
2991 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2992 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2996 interrupt-names = "wdog", "fatal", "ready",
2997 "handover", "stop-ack";
3000 clock-names = "xo";
3002 power-domains = <&rpmhpd RPMHPD_CX>,
3004 power-domain-names = "cx", "mxc";
3006 memory-region = <&cdsp_mem>;
3010 qcom,smem-states = <&smp2p_cdsp_out 0>;
3011 qcom,smem-state-names = "stop";
3015 glink-edge {
3016 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3023 qcom,remote-pid = <5>;
3027 qcom,glink-channels = "fastrpcglink-apps-dsp";
3029 qcom,non-secure-domain;
3030 #address-cells = <1>;
3031 #size-cells = <0>;
3033 compute-cb@1 {
3034 compatible = "qcom,fastrpc-compute-cb";
3036 iommus = <&apps_smmu 0x2161 0x0400>,
3037 <&apps_smmu 0x1021 0x1420>;
3040 compute-cb@2 {
3041 compatible = "qcom,fastrpc-compute-cb";
3043 iommus = <&apps_smmu 0x2162 0x0400>,
3044 <&apps_smmu 0x1022 0x1420>;
3047 compute-cb@3 {
3048 compatible = "qcom,fastrpc-compute-cb";
3050 iommus = <&apps_smmu 0x2163 0x0400>,
3051 <&apps_smmu 0x1023 0x1420>;
3054 compute-cb@4 {
3055 compatible = "qcom,fastrpc-compute-cb";
3057 iommus = <&apps_smmu 0x2164 0x0400>,
3058 <&apps_smmu 0x1024 0x1420>;
3061 compute-cb@5 {
3062 compatible = "qcom,fastrpc-compute-cb";
3064 iommus = <&apps_smmu 0x2165 0x0400>,
3065 <&apps_smmu 0x1025 0x1420>;
3068 compute-cb@6 {
3069 compatible = "qcom,fastrpc-compute-cb";
3071 iommus = <&apps_smmu 0x2166 0x0400>,
3072 <&apps_smmu 0x1026 0x1420>;
3075 compute-cb@7 {
3076 compatible = "qcom,fastrpc-compute-cb";
3078 iommus = <&apps_smmu 0x2167 0x0400>,
3079 <&apps_smmu 0x1027 0x1420>;
3082 compute-cb@8 {
3083 compatible = "qcom,fastrpc-compute-cb";
3085 iommus = <&apps_smmu 0x2168 0x0400>,
3086 <&apps_smmu 0x1028 0x1420>;
3095 compatible = "qcom,sm8450-mpss-pas";
3096 reg = <0x0 0x04080000 0x0 0x10000>;
3098 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
3099 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
3104 interrupt-names = "wdog", "fatal", "ready", "handover",
3105 "stop-ack", "shutdown-ack";
3108 clock-names = "xo";
3110 power-domains = <&rpmhpd RPMHPD_CX>,
3112 power-domain-names = "cx", "mss";
3114 memory-region = <&mpss_mem>;
3118 qcom,smem-states = <&smp2p_modem_out 0>;
3119 qcom,smem-state-names = "stop";
3123 glink-edge {
3124 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
3130 qcom,remote-pid = <1>;
3134 videocc: clock-controller@aaf0000 {
3135 compatible = "qcom,sm8450-videocc";
3136 reg = <0 0x0aaf0000 0 0x10000>;
3139 power-domains = <&rpmhpd RPMHPD_MMCX>;
3140 required-opps = <&rpmhpd_opp_low_svs>;
3141 #clock-cells = <1>;
3142 #reset-cells = <1>;
3143 #power-domain-cells = <1>;
3147 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
3148 reg = <0 0x0ac15000 0 0x1000>;
3150 power-domains = <&camcc TITAN_TOP_GDSC>;
3157 clock-names = "camnoc_axi",
3162 pinctrl-0 = <&cci0_default &cci1_default>;
3163 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
3164 pinctrl-names = "default", "sleep";
3167 #address-cells = <1>;
3168 #size-cells = <0>;
3170 cci0_i2c0: i2c-bus@0 {
3171 reg = <0>;
3172 clock-frequency = <1000000>;
3173 #address-cells = <1>;
3174 #size-cells = <0>;
3177 cci0_i2c1: i2c-bus@1 {
3179 clock-frequency = <1000000>;
3180 #address-cells = <1>;
3181 #size-cells = <0>;
3186 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
3187 reg = <0 0x0ac16000 0 0x1000>;
3189 power-domains = <&camcc TITAN_TOP_GDSC>;
3196 clock-names = "camnoc_axi",
3201 pinctrl-0 = <&cci2_default &cci3_default>;
3202 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3203 pinctrl-names = "default", "sleep";
3206 #address-cells = <1>;
3207 #size-cells = <0>;
3209 cci1_i2c0: i2c-bus@0 {
3210 reg = <0>;
3211 clock-frequency = <1000000>;
3212 #address-cells = <1>;
3213 #size-cells = <0>;
3216 cci1_i2c1: i2c-bus@1 {
3218 clock-frequency = <1000000>;
3219 #address-cells = <1>;
3220 #size-cells = <0>;
3224 camcc: clock-controller@ade0000 {
3225 compatible = "qcom,sm8450-camcc";
3226 reg = <0 0x0ade0000 0 0x20000>;
3231 power-domains = <&rpmhpd RPMHPD_MMCX>;
3232 required-opps = <&rpmhpd_opp_low_svs>;
3233 #clock-cells = <1>;
3234 #reset-cells = <1>;
3235 #power-domain-cells = <1>;
3239 mdss: display-subsystem@ae00000 {
3240 compatible = "qcom,sm8450-mdss";
3241 reg = <0 0x0ae00000 0 0x1000>;
3242 reg-names = "mdss";
3245 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3246 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3249 interconnect-names = "mdp0-mem",
3250 "mdp1-mem",
3251 "cpu-cfg";
3255 power-domains = <&dispcc MDSS_GDSC>;
3263 interrupt-controller;
3264 #interrupt-cells = <1>;
3266 iommus = <&apps_smmu 0x2800 0x402>;
3268 #address-cells = <2>;
3269 #size-cells = <2>;
3274 mdss_mdp: display-controller@ae01000 {
3275 compatible = "qcom,sm8450-dpu";
3276 reg = <0 0x0ae01000 0 0x8f000>,
3277 <0 0x0aeb0000 0 0x2008>;
3278 reg-names = "mdp", "vbif";
3286 clock-names = "bus",
3293 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3294 assigned-clock-rates = <19200000>;
3296 operating-points-v2 = <&mdp_opp_table>;
3297 power-domains = <&rpmhpd RPMHPD_MMCX>;
3299 interrupt-parent = <&mdss>;
3300 interrupts = <0>;
3303 #address-cells = <1>;
3304 #size-cells = <0>;
3306 port@0 {
3307 reg = <0>;
3309 remote-endpoint = <&mdss_dsi0_in>;
3316 remote-endpoint = <&mdss_dsi1_in>;
3323 remote-endpoint = <&mdss_dp0_in>;
3328 mdp_opp_table: opp-table {
3329 compatible = "operating-points-v2";
3331 opp-172000000 {
3332 opp-hz = /bits/ 64 <172000000>;
3333 required-opps = <&rpmhpd_opp_low_svs_d1>;
3336 opp-200000000 {
3337 opp-hz = /bits/ 64 <200000000>;
3338 required-opps = <&rpmhpd_opp_low_svs>;
3341 opp-325000000 {
3342 opp-hz = /bits/ 64 <325000000>;
3343 required-opps = <&rpmhpd_opp_svs>;
3346 opp-375000000 {
3347 opp-hz = /bits/ 64 <375000000>;
3348 required-opps = <&rpmhpd_opp_svs_l1>;
3351 opp-500000000 {
3352 opp-hz = /bits/ 64 <500000000>;
3353 required-opps = <&rpmhpd_opp_nom>;
3358 mdss_dp0: displayport-controller@ae90000 {
3359 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3360 reg = <0 0xae90000 0 0x200>,
3361 <0 0xae90200 0 0x200>,
3362 <0 0xae90400 0 0xc00>,
3363 <0 0xae91000 0 0x400>,
3364 <0 0xae91400 0 0x400>;
3365 interrupt-parent = <&mdss>;
3372 clock-names = "core_iface",
3378 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3380 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3384 phy-names = "dp";
3386 #sound-dai-cells = <0>;
3388 operating-points-v2 = <&dp_opp_table>;
3389 power-domains = <&rpmhpd RPMHPD_MMCX>;
3394 #address-cells = <1>;
3395 #size-cells = <0>;
3397 port@0 {
3398 reg = <0>;
3400 remote-endpoint = <&dpu_intf0_out>;
3408 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3413 dp_opp_table: opp-table {
3414 compatible = "operating-points-v2";
3416 opp-160000000 {
3417 opp-hz = /bits/ 64 <160000000>;
3418 required-opps = <&rpmhpd_opp_low_svs>;
3421 opp-270000000 {
3422 opp-hz = /bits/ 64 <270000000>;
3423 required-opps = <&rpmhpd_opp_svs>;
3426 opp-540000000 {
3427 opp-hz = /bits/ 64 <540000000>;
3428 required-opps = <&rpmhpd_opp_svs_l1>;
3431 opp-810000000 {
3432 opp-hz = /bits/ 64 <810000000>;
3433 required-opps = <&rpmhpd_opp_nom>;
3439 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3440 reg = <0 0x0ae94000 0 0x400>;
3441 reg-names = "dsi_ctrl";
3443 interrupt-parent = <&mdss>;
3452 clock-names = "byte",
3459 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3460 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3462 operating-points-v2 = <&mdss_dsi_opp_table>;
3463 power-domains = <&rpmhpd RPMHPD_MMCX>;
3466 phy-names = "dsi";
3468 #address-cells = <1>;
3469 #size-cells = <0>;
3474 #address-cells = <1>;
3475 #size-cells = <0>;
3477 port@0 {
3478 reg = <0>;
3480 remote-endpoint = <&dpu_intf1_out>;
3491 mdss_dsi_opp_table: opp-table {
3492 compatible = "operating-points-v2";
3494 opp-187500000 {
3495 opp-hz = /bits/ 64 <187500000>;
3496 required-opps = <&rpmhpd_opp_low_svs>;
3499 opp-300000000 {
3500 opp-hz = /bits/ 64 <300000000>;
3501 required-opps = <&rpmhpd_opp_svs>;
3504 opp-358000000 {
3505 opp-hz = /bits/ 64 <358000000>;
3506 required-opps = <&rpmhpd_opp_svs_l1>;
3512 compatible = "qcom,sm8450-dsi-phy-5nm";
3513 reg = <0 0x0ae94400 0 0x200>,
3514 <0 0x0ae94600 0 0x280>,
3515 <0 0x0ae94900 0 0x260>;
3516 reg-names = "dsi_phy",
3520 #clock-cells = <1>;
3521 #phy-cells = <0>;
3525 clock-names = "iface", "ref";
3531 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3532 reg = <0 0x0ae96000 0 0x400>;
3533 reg-names = "dsi_ctrl";
3535 interrupt-parent = <&mdss>;
3544 clock-names = "byte",
3551 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3552 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3554 operating-points-v2 = <&mdss_dsi_opp_table>;
3555 power-domains = <&rpmhpd RPMHPD_MMCX>;
3558 phy-names = "dsi";
3560 #address-cells = <1>;
3561 #size-cells = <0>;
3566 #address-cells = <1>;
3567 #size-cells = <0>;
3569 port@0 {
3570 reg = <0>;
3572 remote-endpoint = <&dpu_intf2_out>;
3585 compatible = "qcom,sm8450-dsi-phy-5nm";
3586 reg = <0 0x0ae96400 0 0x200>,
3587 <0 0x0ae96600 0 0x280>,
3588 <0 0x0ae96900 0 0x260>;
3589 reg-names = "dsi_phy",
3593 #clock-cells = <1>;
3594 #phy-cells = <0>;
3598 clock-names = "iface", "ref";
3604 dispcc: clock-controller@af00000 {
3605 compatible = "qcom,sm8450-dispcc";
3606 reg = <0 0x0af00000 0 0x20000>;
3611 <&mdss_dsi0_phy 0>,
3613 <&mdss_dsi1_phy 0>,
3617 <0>, /* dp1 */
3618 <0>,
3619 <0>, /* dp2 */
3620 <0>,
3621 <0>, /* dp3 */
3622 <0>;
3623 power-domains = <&rpmhpd RPMHPD_MMCX>;
3624 required-opps = <&rpmhpd_opp_low_svs>;
3625 #clock-cells = <1>;
3626 #reset-cells = <1>;
3627 #power-domain-cells = <1>;
3630 pdc: interrupt-controller@b220000 {
3631 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3632 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3633 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3635 #interrupt-cells = <2>;
3636 interrupt-parent = <&intc>;
3637 interrupt-controller;
3640 tsens0: thermal-sensor@c263000 {
3641 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3642 reg = <0 0x0c263000 0 0x1000>, /* TM */
3643 <0 0x0c222000 0 0x1000>; /* SROT */
3647 interrupt-names = "uplow", "critical";
3648 #thermal-sensor-cells = <1>;
3651 tsens1: thermal-sensor@c265000 {
3652 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3653 reg = <0 0x0c265000 0 0x1000>, /* TM */
3654 <0 0x0c223000 0 0x1000>; /* SROT */
3658 interrupt-names = "uplow", "critical";
3659 #thermal-sensor-cells = <1>;
3662 aoss_qmp: power-management@c300000 {
3663 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3664 reg = <0 0x0c300000 0 0x400>;
3665 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3669 #clock-cells = <0>;
3673 compatible = "qcom,rpmh-stats";
3674 reg = <0 0x0c3f0000 0 0x400>;
3678 compatible = "qcom,spmi-pmic-arb";
3679 reg = <0 0x0c400000 0 0x00003000>,
3680 <0 0x0c500000 0 0x00400000>,
3681 <0 0x0c440000 0 0x00080000>,
3682 <0 0x0c4c0000 0 0x00010000>,
3683 <0 0x0c42d000 0 0x00010000>;
3684 reg-names = "core",
3689 interrupt-names = "periph_irq";
3690 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3691 qcom,ee = <0>;
3692 qcom,channel = <0>;
3693 interrupt-controller;
3694 #interrupt-cells = <4>;
3695 #address-cells = <2>;
3696 #size-cells = <0>;
3700 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3701 reg = <0 0x0ed18000 0 0x1000>;
3703 interrupt-controller;
3704 #interrupt-cells = <3>;
3705 #mbox-cells = <2>;
3709 compatible = "qcom,sm8450-tlmm";
3710 reg = <0 0x0f100000 0 0x300000>;
3712 gpio-controller;
3713 #gpio-cells = <2>;
3714 interrupt-controller;
3715 #interrupt-cells = <2>;
3716 gpio-ranges = <&tlmm 0 0 211>;
3717 wakeup-parent = <&pdc>;
3719 sdc2_default_state: sdc2-default-state {
3720 clk-pins {
3722 drive-strength = <16>;
3723 bias-disable;
3726 cmd-pins {
3728 drive-strength = <16>;
3729 bias-pull-up;
3732 data-pins {
3734 drive-strength = <16>;
3735 bias-pull-up;
3739 sdc2_sleep_state: sdc2-sleep-state {
3740 clk-pins {
3742 drive-strength = <2>;
3743 bias-disable;
3746 cmd-pins {
3748 drive-strength = <2>;
3749 bias-pull-up;
3752 data-pins {
3754 drive-strength = <2>;
3755 bias-pull-up;
3759 cci0_default: cci0-default-state {
3763 drive-strength = <2>;
3764 bias-pull-up;
3767 cci0_sleep: cci0-sleep-state {
3771 drive-strength = <2>;
3772 bias-pull-down;
3775 cci1_default: cci1-default-state {
3779 drive-strength = <2>;
3780 bias-pull-up;
3783 cci1_sleep: cci1-sleep-state {
3787 drive-strength = <2>;
3788 bias-pull-down;
3791 cci2_default: cci2-default-state {
3795 drive-strength = <2>;
3796 bias-pull-up;
3799 cci2_sleep: cci2-sleep-state {
3803 drive-strength = <2>;
3804 bias-pull-down;
3807 cci3_default: cci3-default-state {
3811 drive-strength = <2>;
3812 bias-pull-up;
3815 cci3_sleep: cci3-sleep-state {
3819 drive-strength = <2>;
3820 bias-pull-down;
3823 pcie0_default_state: pcie0-default-state {
3824 perst-pins {
3827 drive-strength = <2>;
3828 bias-pull-down;
3831 clkreq-pins {
3834 drive-strength = <2>;
3835 bias-pull-up;
3838 wake-pins {
3841 drive-strength = <2>;
3842 bias-pull-up;
3846 pcie1_default_state: pcie1-default-state {
3847 perst-pins {
3850 drive-strength = <2>;
3851 bias-pull-down;
3854 clkreq-pins {
3857 drive-strength = <2>;
3858 bias-pull-up;
3861 wake-pins {
3864 drive-strength = <2>;
3865 bias-pull-up;
3869 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3874 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3879 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3884 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3889 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3894 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3899 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3904 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3909 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3914 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3919 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3924 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3929 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3932 drive-strength = <2>;
3933 bias-pull-up;
3936 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3939 drive-strength = <2>;
3940 bias-pull-up;
3943 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3948 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3953 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3958 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3963 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3968 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3973 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3978 qup_spi0_cs: qup-spi0-cs-state {
3983 qup_spi0_data_clk: qup-spi0-data-clk-state {
3988 qup_spi1_cs: qup-spi1-cs-state {
3993 qup_spi1_data_clk: qup-spi1-data-clk-state {
3998 qup_spi2_cs: qup-spi2-cs-state {
4003 qup_spi2_data_clk: qup-spi2-data-clk-state {
4008 qup_spi3_cs: qup-spi3-cs-state {
4013 qup_spi3_data_clk: qup-spi3-data-clk-state {
4018 qup_spi4_cs: qup-spi4-cs-state {
4021 drive-strength = <6>;
4022 bias-disable;
4025 qup_spi4_data_clk: qup-spi4-data-clk-state {
4030 qup_spi5_cs: qup-spi5-cs-state {
4035 qup_spi5_data_clk: qup-spi5-data-clk-state {
4040 qup_spi6_cs: qup-spi6-cs-state {
4045 qup_spi6_data_clk: qup-spi6-data-clk-state {
4050 qup_spi8_cs: qup-spi8-cs-state {
4055 qup_spi8_data_clk: qup-spi8-data-clk-state {
4060 qup_spi9_cs: qup-spi9-cs-state {
4065 qup_spi9_data_clk: qup-spi9-data-clk-state {
4070 qup_spi10_cs: qup-spi10-cs-state {
4075 qup_spi10_data_clk: qup-spi10-data-clk-state {
4080 qup_spi11_cs: qup-spi11-cs-state {
4085 qup_spi11_data_clk: qup-spi11-data-clk-state {
4090 qup_spi12_cs: qup-spi12-cs-state {
4095 qup_spi12_data_clk: qup-spi12-data-clk-state {
4100 qup_spi13_cs: qup-spi13-cs-state {
4105 qup_spi13_data_clk: qup-spi13-data-clk-state {
4110 qup_spi14_cs: qup-spi14-cs-state {
4115 qup_spi14_data_clk: qup-spi14-data-clk-state {
4120 qup_spi15_cs: qup-spi15-cs-state {
4125 qup_spi15_data_clk: qup-spi15-data-clk-state {
4130 qup_spi16_cs: qup-spi16-cs-state {
4135 qup_spi16_data_clk: qup-spi16-data-clk-state {
4140 qup_spi17_cs: qup-spi17-cs-state {
4145 qup_spi17_data_clk: qup-spi17-data-clk-state {
4150 qup_spi18_cs: qup-spi18-cs-state {
4153 drive-strength = <6>;
4154 bias-disable;
4157 qup_spi18_data_clk: qup-spi18-data-clk-state {
4160 drive-strength = <6>;
4161 bias-disable;
4164 qup_spi19_cs: qup-spi19-cs-state {
4167 drive-strength = <6>;
4168 bias-disable;
4171 qup_spi19_data_clk: qup-spi19-data-clk-state {
4174 drive-strength = <6>;
4175 bias-disable;
4178 qup_spi20_cs: qup-spi20-cs-state {
4183 qup_spi20_data_clk: qup-spi20-data-clk-state {
4188 qup_spi21_cs: qup-spi21-cs-state {
4193 qup_spi21_data_clk: qup-spi21-data-clk-state {
4198 qup_uart7_rx: qup-uart7-rx-state {
4201 drive-strength = <2>;
4202 bias-disable;
4205 qup_uart7_tx: qup-uart7-tx-state {
4208 drive-strength = <2>;
4209 bias-disable;
4212 qup_uart20_default: qup-uart20-default-state {
4219 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4220 reg = <0 0x03440000 0x0 0x20000>,
4221 <0 0x034d0000 0x0 0x10000>;
4222 gpio-controller;
4223 #gpio-cells = <2>;
4224 gpio-ranges = <&lpass_tlmm 0 0 23>;
4228 clock-names = "core", "audio";
4230 tx_swr_active: tx-swr-active-state {
4231 clk-pins {
4234 drive-strength = <2>;
4235 slew-rate = <1>;
4236 bias-disable;
4239 data-pins {
4242 drive-strength = <2>;
4243 slew-rate = <1>;
4244 bias-bus-hold;
4248 rx_swr_active: rx-swr-active-state {
4249 clk-pins {
4252 drive-strength = <2>;
4253 slew-rate = <1>;
4254 bias-disable;
4257 data-pins {
4260 drive-strength = <2>;
4261 slew-rate = <1>;
4262 bias-bus-hold;
4266 dmic01_default: dmic01-default-state {
4267 clk-pins {
4270 drive-strength = <8>;
4271 output-high;
4274 data-pins {
4277 drive-strength = <8>;
4281 dmic23_default: dmic23-default-state {
4282 clk-pins {
4285 drive-strength = <8>;
4286 output-high;
4289 data-pins {
4292 drive-strength = <8>;
4296 wsa_swr_active: wsa-swr-active-state {
4297 clk-pins {
4300 drive-strength = <2>;
4301 slew-rate = <1>;
4302 bias-disable;
4305 data-pins {
4308 drive-strength = <2>;
4309 slew-rate = <1>;
4310 bias-bus-hold;
4314 wsa2_swr_active: wsa2-swr-active-state {
4315 clk-pins {
4318 drive-strength = <2>;
4319 slew-rate = <1>;
4320 bias-disable;
4323 data-pins {
4326 drive-strength = <2>;
4327 slew-rate = <1>;
4328 bias-bus-hold;
4334 compatible = "arm,coresight-stm", "arm,primecell";
4335 reg = <0x0 0x10002000 0x0 0x1000>,
4336 <0x0 0x16280000 0x0 0x180000>;
4337 reg-names = "stm-base", "stm-stimulus-base";
4340 clock-names = "apb_pclk";
4342 out-ports {
4345 remote-endpoint =
4353 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4354 reg = <0x0 0x10041000 0x0 0x1000>;
4357 clock-names = "apb_pclk";
4359 in-ports {
4360 #address-cells = <1>;
4361 #size-cells = <0>;
4366 remote-endpoint =
4372 out-ports {
4375 remote-endpoint =
4383 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4385 reg = <0x0 0x10042000 0x0 0x1000>;
4388 clock-names = "apb_pclk";
4390 in-ports {
4391 #address-cells = <1>;
4392 #size-cells = <0>;
4397 remote-endpoint =
4405 remote-endpoint =
4411 out-ports {
4414 remote-endpoint =
4422 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4423 reg = <0x0 0x10045000 0x0 0x1000>;
4426 clock-names = "apb_pclk";
4428 in-ports {
4429 #address-cells = <1>;
4430 #size-cells = <0>;
4432 port@0 {
4433 reg = <0>;
4435 remote-endpoint =
4443 remote-endpoint =
4449 out-ports {
4452 remote-endpoint =
4460 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
4461 reg = <0x0 0x10046000 0x0 0x1000>;
4464 clock-names = "apb_pclk";
4466 in-ports {
4469 remote-endpoint =
4475 out-ports {
4479 remote-endpoint =
4487 compatible = "arm,coresight-tmc", "arm,primecell";
4488 reg = <0x0 0x10048000 0x0 0x1000>;
4490 iommus = <&apps_smmu 0x0600 0>;
4491 arm,buffer-size = <0x10000>;
4493 arm,scatter-gather;
4495 clock-names = "apb_pclk";
4497 in-ports {
4500 remote-endpoint =
4508 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
4509 reg = <0x0 0x1004e000 0x0 0x1000>;
4512 clock-names = "apb_pclk";
4514 in-ports {
4517 remote-endpoint =
4523 out-ports {
4528 remote-endpoint =
4536 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4538 reg = <0x0 0x10b04000 0x0 0x1000>;
4541 clock-names = "apb_pclk";
4543 in-ports {
4544 #address-cells = <1>;
4545 #size-cells = <0>;
4550 remote-endpoint =
4558 remote-endpoint =
4564 out-ports {
4567 remote-endpoint =
4575 compatible = "arm,coresight-tmc", "arm,primecell";
4576 reg = <0x0 0x10b05000 0x0 0x1000>;
4579 clock-names = "apb_pclk";
4581 in-ports {
4584 remote-endpoint =
4590 out-ports {
4593 remote-endpoint =
4601 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
4602 reg = <0x0 0x10b06000 0x0 0x1000>;
4604 qcom,replicator-loses-context;
4606 clock-names = "apb_pclk";
4608 in-ports {
4611 remote-endpoint =
4617 out-ports {
4621 remote-endpoint =
4629 compatible = "qcom,coresight-tpda", "arm,primecell";
4631 reg = <0x0 0x10b08000 0x0 0x1000>;
4634 clock-names = "apb_pclk";
4636 in-ports {
4638 #address-cells = <1>;
4639 #size-cells = <0>;
4641 port@0 {
4642 reg = <0>;
4644 remote-endpoint =
4652 remote-endpoint =
4658 out-ports {
4662 remote-endpoint =
4670 compatible = "qcom,coresight-tpdm", "arm,primecell";
4671 reg = <0x0 0x10b09000 0x0 0x1000>;
4675 clock-names = "apb_pclk";
4677 out-ports {
4680 remote-endpoint =
4688 compatible = "qcom,coresight-tpdm", "arm,primecell";
4689 reg = <0x0 0x10b0d000 0x0 0x1000>;
4692 clock-names = "apb_pclk";
4694 out-ports {
4697 remote-endpoint =
4705 compatible = "qcom,coresight-tpdm", "arm,primecell";
4706 reg = <0x0 0x10c28000 0x0 0x1000>;
4709 clock-names = "apb_pclk";
4711 out-ports {
4714 remote-endpoint =
4722 compatible = "qcom,coresight-tpdm", "arm,primecell";
4723 reg = <0x0 0x10c29000 0x0 0x1000>;
4726 clock-names = "apb_pclk";
4728 out-ports {
4731 remote-endpoint =
4739 compatible = "arm,coresight-cti", "arm,primecell";
4740 reg = <0x0 0x10c2a000 0x0 0x1000>;
4743 clock-names = "apb_pclk";
4747 compatible = "arm,coresight-cti", "arm,primecell";
4748 reg = <0x0 0x10c2b000 0x0 0x1000>;
4751 clock-names = "apb_pclk";
4755 compatible = "qcom,coresight-tpda", "arm,primecell";
4756 reg = <0x0 0x10c2e000 0x0 0x1000>;
4759 clock-names = "apb_pclk";
4761 in-ports {
4763 #address-cells = <1>;
4764 #size-cells = <0>;
4769 remote-endpoint =
4777 remote-endpoint =
4783 out-ports {
4787 remote-endpoint =
4795 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4796 reg = <0x0 0x10c2f000 0x0 0x1000>;
4799 clock-names = "apb_pclk";
4801 in-ports {
4805 remote-endpoint =
4811 out-ports {
4814 remote-endpoint =
4822 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4824 reg = <0x0 0x13810000 0x0 0x1000>;
4827 clock-names = "apb_pclk";
4829 in-ports {
4833 remote-endpoint =
4839 out-ports {
4842 remote-endpoint =
4850 compatible = "arm,coresight-cti", "arm,primecell";
4851 reg = <0x0 0x138e0000 0x0 0x1000>;
4854 clock-names = "apb_pclk";
4858 compatible = "arm,coresight-cti", "arm,primecell";
4859 reg = <0x0 0x138f0000 0x0 0x1000>;
4862 clock-names = "apb_pclk";
4866 compatible = "arm,coresight-cti", "arm,primecell";
4867 reg = <0x0 0x13900000 0x0 0x1000>;
4870 clock-names = "apb_pclk";
4874 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4875 reg = <0 0x146aa000 0 0x1000>;
4876 ranges = <0 0 0x146aa000 0x1000>;
4878 #address-cells = <1>;
4879 #size-cells = <1>;
4881 pil-reloc@94c {
4882 compatible = "qcom,pil-reloc-info";
4883 reg = <0x94c 0xc8>;
4888 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4889 reg = <0 0x15000000 0 0x100000>;
4890 #iommu-cells = <2>;
4891 #global-interrupts = <1>;
4989 dma-coherent;
4992 intc: interrupt-controller@17100000 {
4993 compatible = "arm,gic-v3";
4994 #interrupt-cells = <3>;
4995 interrupt-controller;
4996 #redistributor-regions = <1>;
4997 redistributor-stride = <0x0 0x40000>;
4998 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4999 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
5001 #address-cells = <2>;
5002 #size-cells = <2>;
5005 gic_its: msi-controller@17140000 {
5006 compatible = "arm,gic-v3-its";
5007 reg = <0x0 0x17140000 0x0 0x20000>;
5008 msi-controller;
5009 #msi-cells = <1>;
5014 compatible = "arm,armv7-timer-mem";
5015 #address-cells = <1>;
5016 #size-cells = <1>;
5017 ranges = <0 0 0 0x20000000>;
5018 reg = <0x0 0x17420000 0x0 0x1000>;
5019 clock-frequency = <19200000>;
5022 frame-number = <0>;
5025 reg = <0x17421000 0x1000>,
5026 <0x17422000 0x1000>;
5030 frame-number = <1>;
5032 reg = <0x17423000 0x1000>;
5037 frame-number = <2>;
5039 reg = <0x17425000 0x1000>;
5044 frame-number = <3>;
5046 reg = <0x17427000 0x1000>;
5051 frame-number = <4>;
5053 reg = <0x17429000 0x1000>;
5058 frame-number = <5>;
5060 reg = <0x1742b000 0x1000>;
5065 frame-number = <6>;
5067 reg = <0x1742d000 0x1000>;
5074 compatible = "qcom,rpmh-rsc";
5075 reg = <0x0 0x17a00000 0x0 0x10000>,
5076 <0x0 0x17a10000 0x0 0x10000>,
5077 <0x0 0x17a20000 0x0 0x10000>,
5078 <0x0 0x17a30000 0x0 0x10000>;
5079 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
5083 qcom,tcs-offset = <0xd00>;
5084 qcom,drv-id = <2>;
5085 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5086 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5087 power-domains = <&cluster_pd>;
5089 apps_bcm_voter: bcm-voter {
5090 compatible = "qcom,bcm-voter";
5093 rpmhcc: clock-controller {
5094 compatible = "qcom,sm8450-rpmh-clk";
5095 #clock-cells = <1>;
5096 clock-names = "xo";
5100 rpmhpd: power-controller {
5101 compatible = "qcom,sm8450-rpmhpd";
5102 #power-domain-cells = <1>;
5103 operating-points-v2 = <&rpmhpd_opp_table>;
5105 rpmhpd_opp_table: opp-table {
5106 compatible = "operating-points-v2";
5109 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5113 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5117 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5121 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5125 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5129 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5133 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5137 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5141 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5145 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5149 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5153 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5157 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5161 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5168 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
5169 reg = <0 0x17d91000 0 0x1000>,
5170 <0 0x17d92000 0 0x1000>,
5171 <0 0x17d93000 0 0x1000>;
5172 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
5174 clock-names = "xo", "alternate";
5178 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5179 #freq-domain-cells = <1>;
5180 #clock-cells = <1>;
5184 compatible = "qcom,sm8450-gem-noc";
5185 reg = <0 0x19100000 0 0xbb800>;
5186 #interconnect-cells = <2>;
5187 qcom,bcm-voters = <&apps_bcm_voter>;
5190 system-cache-controller@19200000 {
5191 compatible = "qcom,sm8450-llcc";
5192 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
5193 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
5194 <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>;
5195 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
5202 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
5203 "jedec,ufs-2.0";
5204 reg = <0 0x01d84000 0 0x3000>;
5207 phy-names = "ufsphy";
5208 lanes-per-direction = <2>;
5209 #reset-cells = <1>;
5211 reset-names = "rst";
5213 power-domains = <&gcc UFS_PHY_GDSC>;
5215 iommus = <&apps_smmu 0xe0 0x0>;
5216 dma-coherent;
5218 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
5219 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
5220 interconnect-names = "ufs-ddr", "cpu-ufs";
5221 clock-names =
5239 freq-table-hz =
5241 <0 0>,
5242 <0 0>,
5245 <0 0>,
5246 <0 0>,
5247 <0 0>;
5254 compatible = "qcom,sm8450-qmp-ufs-phy";
5255 reg = <0 0x01d87000 0 0x1000>;
5257 clock-names = "ref", "ref_aux", "qref";
5262 power-domains = <&gcc UFS_PHY_GDSC>;
5264 resets = <&ufs_mem_hc 0>;
5265 reset-names = "ufsphy";
5267 #clock-cells = <1>;
5268 #phy-cells = <0>;
5274 compatible = "qcom,sm8450-inline-crypto-engine",
5275 "qcom,inline-crypto-engine";
5276 reg = <0 0x01d88000 0 0x8000>;
5280 cryptobam: dma-controller@1dc4000 {
5281 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5282 reg = <0 0x01dc4000 0 0x28000>;
5284 #dma-cells = <1>;
5285 qcom,ee = <0>;
5286 qcom,controlled-remotely;
5287 iommus = <&apps_smmu 0x584 0x11>,
5288 <&apps_smmu 0x588 0x0>,
5289 <&apps_smmu 0x598 0x5>,
5290 <&apps_smmu 0x59a 0x0>,
5291 <&apps_smmu 0x59f 0x0>;
5295 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
5296 reg = <0 0x01dfa000 0 0x6000>;
5298 dma-names = "rx", "tx";
5299 iommus = <&apps_smmu 0x584 0x11>,
5300 <&apps_smmu 0x588 0x0>,
5301 <&apps_smmu 0x598 0x5>,
5302 <&apps_smmu 0x59a 0x0>,
5303 <&apps_smmu 0x59f 0x0>;
5304 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
5305 interconnect-names = "memory";
5309 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
5310 reg = <0 0x08804000 0 0x1000>;
5314 interrupt-names = "hc_irq", "pwr_irq";
5319 clock-names = "iface", "core", "xo";
5321 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
5322 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
5323 interconnect-names = "sdhc-ddr","cpu-sdhc";
5324 iommus = <&apps_smmu 0x4a0 0x0>;
5325 power-domains = <&rpmhpd RPMHPD_CX>;
5326 operating-points-v2 = <&sdhc2_opp_table>;
5327 bus-width = <4>;
5328 dma-coherent;
5330 /* Forbid SDR104/SDR50 - broken hw! */
5331 sdhci-caps-mask = <0x3 0x0>;
5335 sdhc2_opp_table: opp-table {
5336 compatible = "operating-points-v2";
5338 opp-100000000 {
5339 opp-hz = /bits/ 64 <100000000>;
5340 required-opps = <&rpmhpd_opp_low_svs>;
5343 opp-202000000 {
5344 opp-hz = /bits/ 64 <202000000>;
5345 required-opps = <&rpmhpd_opp_svs_l1>;
5351 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
5352 reg = <0 0x0a6f8800 0 0x400>;
5354 #address-cells = <2>;
5355 #size-cells = <2>;
5364 clock-names = "cfg_noc",
5371 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5373 assigned-clock-rates = <19200000>, <200000000>;
5375 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
5380 interrupt-names = "pwr_event",
5386 power-domains = <&gcc USB30_PRIM_GDSC>;
5390 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
5391 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
5392 interconnect-names = "usb-ddr", "apps-usb";
5396 reg = <0 0x0a600000 0 0xcd00>;
5398 iommus = <&apps_smmu 0x0 0x0>;
5401 snps,dis-u1-entry-quirk;
5402 snps,dis-u2-entry-quirk;
5404 phy-names = "usb2-phy", "usb3-phy";
5407 #address-cells = <1>;
5408 #size-cells = <0>;
5410 port@0 {
5411 reg = <0>;
5421 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
5429 compatible = "qcom,sm8450-nsp-noc";
5430 reg = <0 0x320c0000 0 0x10000>;
5431 #interconnect-cells = <2>;
5432 qcom,bcm-voters = <&apps_bcm_voter>;
5436 compatible = "qcom,sm8450-lpass-ag-noc";
5437 reg = <0 0x03c40000 0 0x17200>;
5438 #interconnect-cells = <2>;
5439 qcom,bcm-voters = <&apps_bcm_voter>;
5446 thermal-zones {
5447 aoss0-thermal {
5448 thermal-sensors = <&tsens0 0>;
5451 thermal-engine-config {
5457 reset-mon-cfg {
5465 cpuss0-thermal {
5466 thermal-sensors = <&tsens0 1>;
5469 thermal-engine-config {
5475 reset-mon-cfg {
5483 cpuss1-thermal {
5484 thermal-sensors = <&tsens0 2>;
5487 thermal-engine-config {
5493 reset-mon-cfg {
5501 cpuss3-thermal {
5502 thermal-sensors = <&tsens0 3>;
5505 thermal-engine-config {
5511 reset-mon-cfg {
5519 cpuss4-thermal {
5520 thermal-sensors = <&tsens0 4>;
5523 thermal-engine-config {
5529 reset-mon-cfg {
5537 cpu4-top-thermal {
5538 thermal-sensors = <&tsens0 5>;
5541 cpu4_top_alert0: trip-point0 {
5547 cpu4_top_alert1: trip-point1 {
5553 cpu4_top_crit: cpu-crit {
5561 cpu4-bottom-thermal {
5562 thermal-sensors = <&tsens0 6>;
5565 cpu4_bottom_alert0: trip-point0 {
5571 cpu4_bottom_alert1: trip-point1 {
5577 cpu4_bottom_crit: cpu-crit {
5585 cpu5-top-thermal {
5586 thermal-sensors = <&tsens0 7>;
5589 cpu5_top_alert0: trip-point0 {
5595 cpu5_top_alert1: trip-point1 {
5601 cpu5_top_crit: cpu-crit {
5609 cpu5-bottom-thermal {
5610 thermal-sensors = <&tsens0 8>;
5613 cpu5_bottom_alert0: trip-point0 {
5619 cpu5_bottom_alert1: trip-point1 {
5625 cpu5_bottom_crit: cpu-crit {
5633 cpu6-top-thermal {
5634 thermal-sensors = <&tsens0 9>;
5637 cpu6_top_alert0: trip-point0 {
5643 cpu6_top_alert1: trip-point1 {
5649 cpu6_top_crit: cpu-crit {
5657 cpu6-bottom-thermal {
5658 thermal-sensors = <&tsens0 10>;
5661 cpu6_bottom_alert0: trip-point0 {
5667 cpu6_bottom_alert1: trip-point1 {
5673 cpu6_bottom_crit: cpu-crit {
5681 cpu7-top-thermal {
5682 thermal-sensors = <&tsens0 11>;
5685 cpu7_top_alert0: trip-point0 {
5691 cpu7_top_alert1: trip-point1 {
5697 cpu7_top_crit: cpu-crit {
5705 cpu7-middle-thermal {
5706 thermal-sensors = <&tsens0 12>;
5709 cpu7_middle_alert0: trip-point0 {
5715 cpu7_middle_alert1: trip-point1 {
5721 cpu7_middle_crit: cpu-crit {
5729 cpu7-bottom-thermal {
5730 thermal-sensors = <&tsens0 13>;
5733 cpu7_bottom_alert0: trip-point0 {
5739 cpu7_bottom_alert1: trip-point1 {
5745 cpu7_bottom_crit: cpu-crit {
5753 gpu-top-thermal {
5754 polling-delay-passive = <10>;
5756 thermal-sensors = <&tsens0 14>;
5758 cooling-maps {
5761 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5766 gpu_top_alert0: trip-point0 {
5772 trip-point1 {
5778 trip-point2 {
5786 gpu-bottom-thermal {
5787 polling-delay-passive = <10>;
5789 thermal-sensors = <&tsens0 15>;
5791 cooling-maps {
5794 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5799 gpu_bottom_alert0: trip-point0 {
5805 trip-point1 {
5811 trip-point2 {
5819 aoss1-thermal {
5820 thermal-sensors = <&tsens1 0>;
5823 thermal-engine-config {
5829 reset-mon-cfg {
5837 cpu0-thermal {
5838 thermal-sensors = <&tsens1 1>;
5841 cpu0_alert0: trip-point0 {
5847 cpu0_alert1: trip-point1 {
5853 cpu0_crit: cpu-crit {
5861 cpu1-thermal {
5862 thermal-sensors = <&tsens1 2>;
5865 cpu1_alert0: trip-point0 {
5871 cpu1_alert1: trip-point1 {
5877 cpu1_crit: cpu-crit {
5885 cpu2-thermal {
5886 thermal-sensors = <&tsens1 3>;
5889 cpu2_alert0: trip-point0 {
5895 cpu2_alert1: trip-point1 {
5901 cpu2_crit: cpu-crit {
5909 cpu3-thermal {
5910 thermal-sensors = <&tsens1 4>;
5913 cpu3_alert0: trip-point0 {
5919 cpu3_alert1: trip-point1 {
5925 cpu3_crit: cpu-crit {
5933 cdsp0-thermal {
5934 polling-delay-passive = <10>;
5936 thermal-sensors = <&tsens1 5>;
5939 thermal-engine-config {
5945 thermal-hal-config {
5951 reset-mon-cfg {
5957 cdsp_0_config: junction-config {
5965 cdsp1-thermal {
5966 polling-delay-passive = <10>;
5968 thermal-sensors = <&tsens1 6>;
5971 thermal-engine-config {
5977 thermal-hal-config {
5983 reset-mon-cfg {
5989 cdsp_1_config: junction-config {
5997 cdsp2-thermal {
5998 polling-delay-passive = <10>;
6000 thermal-sensors = <&tsens1 7>;
6003 thermal-engine-config {
6009 thermal-hal-config {
6015 reset-mon-cfg {
6021 cdsp_2_config: junction-config {
6029 video-thermal {
6030 thermal-sensors = <&tsens1 8>;
6033 thermal-engine-config {
6039 reset-mon-cfg {
6047 mem-thermal {
6048 polling-delay-passive = <10>;
6050 thermal-sensors = <&tsens1 9>;
6053 thermal-engine-config {
6059 ddr_config0: ddr0-config {
6065 reset-mon-cfg {
6073 modem0-thermal {
6074 thermal-sensors = <&tsens1 10>;
6077 thermal-engine-config {
6083 mdmss0_config0: mdmss0-config0 {
6089 mdmss0_config1: mdmss0-config1 {
6095 reset-mon-cfg {
6103 modem1-thermal {
6104 thermal-sensors = <&tsens1 11>;
6107 thermal-engine-config {
6113 mdmss1_config0: mdmss1-config0 {
6119 mdmss1_config1: mdmss1-config1 {
6125 reset-mon-cfg {
6133 modem2-thermal {
6134 thermal-sensors = <&tsens1 12>;
6137 thermal-engine-config {
6143 mdmss2_config0: mdmss2-config0 {
6149 mdmss2_config1: mdmss2-config1 {
6155 reset-mon-cfg {
6163 modem3-thermal {
6164 thermal-sensors = <&tsens1 13>;
6167 thermal-engine-config {
6173 mdmss3_config0: mdmss3-config0 {
6179 mdmss3_config1: mdmss3-config1 {
6185 reset-mon-cfg {
6193 camera0-thermal {
6194 thermal-sensors = <&tsens1 14>;
6197 thermal-engine-config {
6203 reset-mon-cfg {
6211 camera1-thermal {
6212 thermal-sensors = <&tsens1 15>;
6215 thermal-engine-config {
6221 reset-mon-cfg {
6231 compatible = "arm,armv8-timer";
6236 clock-frequency = <19200000>;