Lines Matching +full:1 +full:d88000
143 qcom,freq-domain = <&cpufreq_hw 1>;
145 clocks = <&cpufreq_hw 1>;
162 qcom,freq-domain = <&cpufreq_hw 1>;
164 clocks = <&cpufreq_hw 1>;
181 qcom,freq-domain = <&cpufreq_hw 1>;
183 clocks = <&cpufreq_hw 1>;
260 big_cpu_sleep_0: cpu-sleep-1-0 {
280 cluster_sleep_1: cluster-sleep-1 {
303 ete-1 {
407 #address-cells = <1>;
418 port@1 {
419 reg = <1>;
481 #reset-cells = <1>;
491 mc_virt: interconnect-1 {
731 qcom,client-id = <1>;
834 #qcom,smem-state-cells = <1>;
858 #qcom,smem-state-cells = <1>;
878 qcom,remote-pid = <1>;
882 #qcom,smem-state-cells = <1>;
893 #qcom,smem-state-cells = <1>;
917 #qcom,smem-state-cells = <1>;
937 #clock-cells = <1>;
938 #reset-cells = <1>;
939 #power-domain-cells = <1>;
946 <&ufs_mem_phy 1>,
1002 #address-cells = <1>;
1009 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1026 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1028 #address-cells = <1>;
1041 #address-cells = <1>;
1047 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1048 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1064 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1065 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1067 #address-cells = <1>;
1080 #address-cells = <1>;
1087 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1104 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1106 #address-cells = <1>;
1119 #address-cells = <1>;
1126 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1143 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1145 #address-cells = <1>;
1158 #address-cells = <1>;
1165 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1182 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1184 #address-cells = <1>;
1197 #address-cells = <1>;
1204 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1238 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1240 #address-cells = <1>;
1253 #address-cells = <1>;
1260 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1277 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1279 #address-cells = <1>;
1329 #address-cells = <1>;
1336 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1356 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1358 #address-cells = <1>;
1371 #address-cells = <1>;
1377 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1378 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1395 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1396 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1398 #address-cells = <1>;
1411 #address-cells = <1>;
1418 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1436 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1438 #address-cells = <1>;
1452 #address-cells = <1>;
1459 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1477 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1479 #address-cells = <1>;
1492 #address-cells = <1>;
1499 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1519 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1521 #address-cells = <1>;
1534 #address-cells = <1>;
1541 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1559 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1561 #address-cells = <1>;
1575 #address-cells = <1>;
1582 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1600 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1602 #address-cells = <1>;
1669 #address-cells = <1>;
1676 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1694 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1696 #address-cells = <1>;
1709 #address-cells = <1>;
1715 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1716 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1733 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1734 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1736 #address-cells = <1>;
1749 #address-cells = <1>;
1756 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1774 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1776 #address-cells = <1>;
1789 #address-cells = <1>;
1796 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1814 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1816 #address-cells = <1>;
1829 #address-cells = <1>;
1836 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1854 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1856 #address-cells = <1>;
1874 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1876 #address-cells = <1>;
1894 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1896 #address-cells = <1>;
1914 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1916 #address-cells = <1>;
1934 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1936 #address-cells = <1>;
1947 pcie0: pcie@1c00000 {
1958 num-lanes = <1>;
1987 #interrupt-cells = <1>;
1989 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2049 /* GEN 1 x1 */
2053 opp-peak-kBps = <250000 1>;
2060 opp-peak-kBps = <500000 1>;
2067 opp-peak-kBps = <984500 1>;
2082 pcie0_phy: phy@1c06000 {
2111 pcie1: pcie@1c08000 {
2120 linux,pci-domain = <1>;
2151 #interrupt-cells = <1>;
2153 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2211 /* GEN 1 x1 */
2215 opp-peak-kBps = <250000 1>;
2218 /* GEN 1 x2 and GEN 2 x1 */
2222 opp-peak-kBps = <500000 1>;
2229 opp-peak-kBps = <1000000 1>;
2236 opp-peak-kBps = <984500 1>;
2243 opp-peak-kBps = <1969000 1>;
2250 opp-peak-kBps = <3938000 1>;
2265 pcie1_phy: phy@1c0e000 {
2281 #clock-cells = <1>;
2342 tcsr_mutex: hwlock@1f40000 {
2345 #hwlock-cells = <1>;
2348 tcsr: syscon@1fc0000 {
2365 <&adreno_smmu 1 0x400>;
2501 #clock-cells = <1>;
2502 #reset-cells = <1>;
2503 #power-domain-cells = <1>;
2511 #global-interrupts = <1>;
2581 #clock-cells = <1>;
2582 #phy-cells = <1>;
2589 #address-cells = <1>;
2599 port@1 {
2600 reg = <1>;
2623 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2660 #address-cells = <1>;
2663 compute-cb@1 {
2665 reg = <1>;
2691 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2728 #address-cells = <1>;
2731 q6apm: service@1 {
2745 #sound-dai-cells = <1>;
2767 #address-cells = <1>;
2803 #sound-dai-cells = <1>;
2832 #sound-dai-cells = <1>;
2848 #sound-dai-cells = <1>;
2876 #sound-dai-cells = <1>;
2892 #sound-dai-cells = <1>;
2907 #sound-dai-cells = <1>;
2936 #sound-dai-cells = <1>;
2968 #sound-dai-cells = <1>;
2983 #sound-dai-cells = <1>;
2993 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3030 #address-cells = <1>;
3033 compute-cb@1 {
3035 reg = <1>;
3100 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
3130 qcom,remote-pid = <1>;
3141 #clock-cells = <1>;
3142 #reset-cells = <1>;
3143 #power-domain-cells = <1>;
3163 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
3167 #address-cells = <1>;
3173 #address-cells = <1>;
3177 cci0_i2c1: i2c-bus@1 {
3178 reg = <1>;
3180 #address-cells = <1>;
3202 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3206 #address-cells = <1>;
3212 #address-cells = <1>;
3216 cci1_i2c1: i2c-bus@1 {
3217 reg = <1>;
3219 #address-cells = <1>;
3233 #clock-cells = <1>;
3234 #reset-cells = <1>;
3235 #power-domain-cells = <1>;
3264 #interrupt-cells = <1>;
3303 #address-cells = <1>;
3313 port@1 {
3314 reg = <1>;
3394 #address-cells = <1>;
3404 port@1 {
3405 reg = <1>;
3460 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3468 #address-cells = <1>;
3474 #address-cells = <1>;
3484 port@1 {
3485 reg = <1>;
3520 #clock-cells = <1>;
3552 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3560 #address-cells = <1>;
3566 #address-cells = <1>;
3576 port@1 {
3577 reg = <1>;
3593 #clock-cells = <1>;
3612 <&mdss_dsi0_phy 1>,
3614 <&mdss_dsi1_phy 1>,
3625 #clock-cells = <1>;
3626 #reset-cells = <1>;
3627 #power-domain-cells = <1>;
3634 <94 609 31>, <125 63 1>, <126 716 12>;
3648 #thermal-sensor-cells = <1>;
3659 #thermal-sensor-cells = <1>;
3690 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4235 slew-rate = <1>;
4243 slew-rate = <1>;
4253 slew-rate = <1>;
4261 slew-rate = <1>;
4301 slew-rate = <1>;
4309 slew-rate = <1>;
4319 slew-rate = <1>;
4327 slew-rate = <1>;
4360 #address-cells = <1>;
4391 #address-cells = <1>;
4429 #address-cells = <1>;
4440 port@1 {
4441 reg = <1>;
4544 #address-cells = <1>;
4638 #address-cells = <1>;
4763 #address-cells = <1>;
4766 port@1a {
4774 port@1b {
4878 #address-cells = <1>;
4879 #size-cells = <1>;
4891 #global-interrupts = <1>;
4996 #redistributor-regions = <1>;
5009 #msi-cells = <1>;
5015 #address-cells = <1>;
5016 #size-cells = <1>;
5030 frame-number = <1>;
5079 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
5095 #clock-cells = <1>;
5102 #power-domain-cells = <1>;
5178 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5179 #freq-domain-cells = <1>;
5180 #clock-cells = <1>;
5201 ufs_mem_hc: ufshc@1d84000 {
5209 #reset-cells = <1>;
5253 ufs_mem_phy: phy@1d87000 {
5267 #clock-cells = <1>;
5273 ice: crypto@1d88000 {
5280 cryptobam: dma-controller@1dc4000 {
5284 #dma-cells = <1>;
5294 crypto: crypto@1dfa000 {
5407 #address-cells = <1>;
5417 port@1 {
5418 reg = <1>;
5466 thermal-sensors = <&tsens0 1>;
5838 thermal-sensors = <&tsens1 1>;