Lines Matching +full:0 +full:x5000000
39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
100 reg = <0x0 0x200>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
107 clocks = <&cpufreq_hw 0>;
119 reg = <0x0 0x300>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
126 clocks = <&cpufreq_hw 0>;
138 reg = <0x0 0x400>;
157 reg = <0x0 0x500>;
176 reg = <0x0 0x600>;
195 reg = <0x0 0x700>;
250 little_cpu_sleep_0: cpu-sleep-0-0 {
253 arm,psci-suspend-param = <0x40000004>;
260 big_cpu_sleep_0: cpu-sleep-1-0 {
263 arm,psci-suspend-param = <0x40000004>;
272 cluster_sleep_0: cluster-sleep-0 {
274 arm,psci-suspend-param = <0x41000044>;
282 arm,psci-suspend-param = <0x4100c344>;
290 ete-0 {
408 #size-cells = <0>;
410 port@0 {
411 reg = <0>;
479 qcom,dload-mode = <&tcsr 0x13000>;
480 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
485 clk_virt: interconnect-0 {
500 reg = <0x0 0xa0000000 0x0 0x0>;
513 #power-domain-cells = <0>;
519 #power-domain-cells = <0>;
525 #power-domain-cells = <0>;
531 #power-domain-cells = <0>;
537 #power-domain-cells = <0>;
543 #power-domain-cells = <0>;
549 #power-domain-cells = <0>;
555 #power-domain-cells = <0>;
561 #power-domain-cells = <0>;
591 reg = <0x0 0x80000000 0x0 0x600000>;
596 reg = <0x0 0x80600000 0x0 0x40000>;
601 reg = <0x0 0x80640000 0x0 0x180000>;
606 reg = <0x0 0x807c0000 0x0 0x40000>;
611 reg = <0x0 0x80800000 0x0 0x60000>;
617 reg = <0x0 0x80860000 0x0 0x20000>;
622 reg = <0x0 0x80880000 0x0 0x20000>;
627 reg = <0x0 0x808a0000 0x0 0x40000>;
632 reg = <0x0 0x808e0000 0x0 0x4000>;
637 reg = <0x0 0x808e4000 0x0 0x10000>;
644 reg = <0x0 0x80900000 0x0 0x200000>;
650 reg = <0x0 0x80b00000 0x0 0x100000>;
655 reg = <0x0 0x80c00000 0x0 0x4600000>;
660 reg = <0x0 0x85700000 0x0 0x700000>;
665 reg = <0x0 0x85e00000 0x0 0x2100000>;
670 reg = <0x0 0x88000000 0x0 0x1900000>;
675 reg = <0x0 0x89900000 0x0 0x2000000>;
680 reg = <0x0 0x8b900000 0x0 0x10000>;
685 reg = <0x0 0x8b910000 0x0 0xa000>;
690 reg = <0x0 0x8b91a000 0x0 0x2000>;
695 reg = <0x0 0x8ba00000 0x0 0x180000>;
701 reg = <0x0 0x8bb80000 0x0 0x60000>;
707 reg = <0x0 0x8bbe0000 0x0 0x20000>;
712 reg = <0x0 0x8bc00000 0x0 0x13200000>;
717 reg = <0x0 0x9ee00000 0x0 0x700000>;
722 reg = <0x0 0x9f500000 0x0 0x800000>;
728 reg = <0x0 0x9fd00000 0x0 0x280000>;
736 reg = <0x0 0xa6e00000 0x0 0x40000>;
741 reg = <0x0 0xa6f00000 0x0 0x100000>;
747 /* Linux kernel image is loaded at 0xa0000000 */
750 reg = <0x0 0xbb000000 0x0 0x5000000>;
755 reg = <0x0 0xc0000000 0x0 0x20000000>;
760 reg = <0x0 0xe0000000 0x0 0x600000>;
765 reg = <0x0 0xe0600000 0x0 0x400000>;
770 reg = <0x0 0xe0a00000 0x0 0x100000>;
775 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
780 reg = <0x0 0xe55f3000 0x0 0x9000>;
785 reg = <0x0 0xe55fc000 0x0 0x4000>;
790 reg = <0x0 0xe5600000 0x0 0x100000>;
795 reg = <0x0 0xe8800000 0x0 0x100000>;
800 reg = <0x0 0xe8900000 0x0 0x1200000>;
805 reg = <0x0 0xe9b00000 0x0 0x500000>;
810 reg = <0x0 0xea000000 0x0 0x3900000>;
815 reg = <0x0 0xed900000 0x0 0x3b00000>;
829 qcom,local-pid = <0>;
853 qcom,local-pid = <0>;
877 qcom,local-pid = <0>;
912 qcom,local-pid = <0>;
927 soc: soc@0 {
930 ranges = <0 0 0 0 0x10 0>;
931 dma-ranges = <0 0 0 0 0x10 0>;
936 reg = <0x0 0x00100000 0x0 0x1f4200>;
945 <&ufs_mem_phy 0>,
963 reg = <0 0x00800000 0 0x60000>;
977 dma-channel-mask = <0x7e>;
978 iommus = <&apps_smmu 0x496 0x0>;
984 reg = <0x0 0x008c0000 0x0 0x2000>;
988 iommus = <&apps_smmu 0x483 0x0>;
996 reg = <0x0 0x00880000 0x0 0x4000>;
1000 pinctrl-0 = <&qup_i2c15_data_clk>;
1003 #size-cells = <0>;
1004 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1005 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1006 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1008 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1009 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1016 reg = <0x0 0x00880000 0x0 0x4000>;
1021 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1022 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1023 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1025 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1026 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1029 #size-cells = <0>;
1035 reg = <0x0 0x00884000 0x0 0x4000>;
1039 pinctrl-0 = <&qup_i2c16_data_clk>;
1042 #size-cells = <0>;
1043 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1044 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1045 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1047 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1055 reg = <0x0 0x00884000 0x0 0x4000>;
1060 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1062 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1064 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1068 #size-cells = <0>;
1074 reg = <0x0 0x00888000 0x0 0x4000>;
1078 pinctrl-0 = <&qup_i2c17_data_clk>;
1081 #size-cells = <0>;
1082 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1083 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1084 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1086 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1094 reg = <0x0 0x00888000 0x0 0x4000>;
1099 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
1100 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1101 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1103 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1107 #size-cells = <0>;
1113 reg = <0x0 0x0088c000 0x0 0x4000>;
1117 pinctrl-0 = <&qup_i2c18_data_clk>;
1120 #size-cells = <0>;
1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1122 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1123 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1125 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1133 reg = <0 0x0088c000 0 0x4000>;
1138 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1139 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1140 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1142 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1146 #size-cells = <0>;
1152 reg = <0x0 0x00890000 0x0 0x4000>;
1156 pinctrl-0 = <&qup_i2c19_data_clk>;
1159 #size-cells = <0>;
1160 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1161 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1162 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1164 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1172 reg = <0 0x00890000 0 0x4000>;
1177 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1178 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1179 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1181 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1185 #size-cells = <0>;
1191 reg = <0x0 0x00894000 0x0 0x4000>;
1195 pinctrl-0 = <&qup_i2c20_data_clk>;
1198 #size-cells = <0>;
1199 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1200 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1201 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1203 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1211 reg = <0 0x00894000 0 0x4000>;
1215 pinctrl-0 = <&qup_uart20_default>;
1228 reg = <0 0x00894000 0 0x4000>;
1233 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1234 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1235 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1237 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1241 #size-cells = <0>;
1247 reg = <0x0 0x00898000 0x0 0x4000>;
1251 pinctrl-0 = <&qup_i2c21_data_clk>;
1254 #size-cells = <0>;
1255 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1256 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1257 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1259 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1267 reg = <0 0x00898000 0 0x4000>;
1272 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1273 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1274 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1276 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1280 #size-cells = <0>;
1288 reg = <0 0x00900000 0 0x60000>;
1302 dma-channel-mask = <0x7e>;
1303 iommus = <&apps_smmu 0x5b6 0x0>;
1309 reg = <0x0 0x009c0000 0x0 0x2000>;
1313 iommus = <&apps_smmu 0x5a3 0x0>;
1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1323 reg = <0x0 0x00980000 0x0 0x4000>;
1327 pinctrl-0 = <&qup_i2c0_data_clk>;
1330 #size-cells = <0>;
1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1332 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1333 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1335 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1336 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1343 reg = <0x0 0x00980000 0x0 0x4000>;
1348 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1352 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1353 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1355 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1356 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1359 #size-cells = <0>;
1365 reg = <0x0 0x00984000 0x0 0x4000>;
1369 pinctrl-0 = <&qup_i2c1_data_clk>;
1372 #size-cells = <0>;
1373 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1374 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1375 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1377 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1385 reg = <0x0 0x00984000 0x0 0x4000>;
1390 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1395 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1399 #size-cells = <0>;
1405 reg = <0x0 0x00988000 0x0 0x4000>;
1409 pinctrl-0 = <&qup_i2c2_data_clk>;
1412 #size-cells = <0>;
1413 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1414 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1415 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1417 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1425 reg = <0x0 0x00988000 0x0 0x4000>;
1430 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1431 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1432 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1433 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1435 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1439 #size-cells = <0>;
1446 reg = <0x0 0x0098c000 0x0 0x4000>;
1450 pinctrl-0 = <&qup_i2c3_data_clk>;
1453 #size-cells = <0>;
1454 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1455 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1456 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1458 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1466 reg = <0x0 0x0098c000 0x0 0x4000>;
1471 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1472 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1473 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1474 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1476 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1480 #size-cells = <0>;
1486 reg = <0x0 0x00990000 0x0 0x4000>;
1490 pinctrl-0 = <&qup_i2c4_data_clk>;
1493 #size-cells = <0>;
1494 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1495 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1496 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1498 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1506 reg = <0x0 0x00990000 0x0 0x4000>;
1511 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1514 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1515 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1516 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1518 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1522 #size-cells = <0>;
1528 reg = <0x0 0x00994000 0x0 0x4000>;
1532 pinctrl-0 = <&qup_i2c5_data_clk>;
1535 #size-cells = <0>;
1536 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1537 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1538 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1540 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1548 reg = <0x0 0x00994000 0x0 0x4000>;
1553 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1554 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1555 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1556 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1558 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1562 #size-cells = <0>;
1569 reg = <0x0 0x00998000 0x0 0x4000>;
1573 pinctrl-0 = <&qup_i2c6_data_clk>;
1576 #size-cells = <0>;
1577 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1578 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1579 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1581 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1589 reg = <0x0 0x00998000 0x0 0x4000>;
1594 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1595 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1596 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1597 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1599 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1603 #size-cells = <0>;
1609 reg = <0 0x0099c000 0 0x4000>;
1613 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1628 reg = <0 0x00a00000 0 0x60000>;
1642 dma-channel-mask = <0x7e>;
1643 iommus = <&apps_smmu 0x56 0x0>;
1649 reg = <0x0 0x00ac0000 0x0 0x6000>;
1653 iommus = <&apps_smmu 0x43 0x0>;
1654 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1663 reg = <0x0 0x00a80000 0x0 0x4000>;
1667 pinctrl-0 = <&qup_i2c8_data_clk>;
1670 #size-cells = <0>;
1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1672 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1673 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1675 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1676 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1683 reg = <0x0 0x00a80000 0x0 0x4000>;
1688 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1689 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1690 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1691 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1693 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1694 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1697 #size-cells = <0>;
1703 reg = <0x0 0x00a84000 0x0 0x4000>;
1707 pinctrl-0 = <&qup_i2c9_data_clk>;
1710 #size-cells = <0>;
1711 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1712 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1713 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1715 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1723 reg = <0x0 0x00a84000 0x0 0x4000>;
1728 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1729 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1730 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1731 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1733 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1737 #size-cells = <0>;
1743 reg = <0x0 0x00a88000 0x0 0x4000>;
1747 pinctrl-0 = <&qup_i2c10_data_clk>;
1750 #size-cells = <0>;
1751 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1752 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1753 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1755 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1763 reg = <0x0 0x00a88000 0x0 0x4000>;
1768 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1769 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1770 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1771 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1773 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1777 #size-cells = <0>;
1783 reg = <0x0 0x00a8c000 0x0 0x4000>;
1787 pinctrl-0 = <&qup_i2c11_data_clk>;
1790 #size-cells = <0>;
1791 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1792 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1793 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1795 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1803 reg = <0x0 0x00a8c000 0x0 0x4000>;
1808 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1809 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1810 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1811 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1813 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1817 #size-cells = <0>;
1823 reg = <0x0 0x00a90000 0x0 0x4000>;
1827 pinctrl-0 = <&qup_i2c12_data_clk>;
1830 #size-cells = <0>;
1831 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1832 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1833 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1835 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1843 reg = <0x0 0x00a90000 0x0 0x4000>;
1848 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1850 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1851 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1853 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1857 #size-cells = <0>;
1863 reg = <0 0x00a94000 0 0x4000>;
1867 pinctrl-0 = <&qup_i2c13_data_clk>;
1869 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1870 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1871 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1873 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1877 #size-cells = <0>;
1883 reg = <0x0 0x00a94000 0x0 0x4000>;
1888 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1889 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1890 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1891 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1893 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1897 #size-cells = <0>;
1903 reg = <0 0x00a98000 0 0x4000>;
1907 pinctrl-0 = <&qup_i2c14_data_clk>;
1909 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1910 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1911 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1913 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1917 #size-cells = <0>;
1923 reg = <0x0 0x00a98000 0x0 0x4000>;
1928 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1929 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1930 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1931 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1933 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1937 #size-cells = <0>;
1944 reg = <0 0x010c3000 0 0x1000>;
1949 reg = <0 0x01c00000 0 0x3000>,
1950 <0 0x60000000 0 0xf1d>,
1951 <0 0x60000f20 0 0xa8>,
1952 <0 0x60001000 0 0x1000>,
1953 <0 0x60100000 0 0x100000>;
1956 linux,pci-domain = <0>;
1957 bus-range = <0x00 0xff>;
1963 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1964 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1966 msi-map = <0x0 &gic_its 0x5980 0x1>,
1967 <0x100 &gic_its 0x5981 0x1>;
1968 msi-map-mask = <0xff00>;
1988 interrupt-map-mask = <0 0 0 0x7>;
1989 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1990 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1991 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1992 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2025 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2026 <0x100 &apps_smmu 0x1c01 0x1>;
2040 pinctrl-0 = <&pcie0_default_state>;
2071 pcieport0: pcie@0 {
2073 reg = <0x0 0x0 0x0 0x0 0x0>;
2074 bus-range = <0x01 0xff>;
2084 reg = <0 0x01c06000 0 0x2000>;
2098 #clock-cells = <0>;
2100 #phy-cells = <0>;
2113 reg = <0 0x01c08000 0 0x3000>,
2114 <0 0x40000000 0 0xf1d>,
2115 <0 0x40000f20 0 0xa8>,
2116 <0 0x40001000 0 0x1000>,
2117 <0 0x40100000 0 0x100000>;
2121 bus-range = <0x00 0xff>;
2127 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2128 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2130 msi-map = <0x0 &gic_its 0x5a00 0x1>,
2131 <0x100 &gic_its 0x5a01 0x1>;
2132 msi-map-mask = <0xff00>;
2152 interrupt-map-mask = <0 0 0 0x7>;
2153 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2154 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2155 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2156 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2187 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2188 <0x100 &apps_smmu 0x1c81 0x1>;
2202 pinctrl-0 = <&pcie1_default_state>;
2254 pcie@0 {
2256 reg = <0x0 0x0 0x0 0x0 0x0>;
2257 bus-range = <0x01 0xff>;
2267 reg = <0 0x01c0e000 0 0x2000>;
2283 #phy-cells = <0>;
2296 reg = <0 0x01500000 0 0x1c000>;
2303 reg = <0 0x01680000 0 0x1e200>;
2310 reg = <0 0x016c0000 0 0xe280>;
2317 reg = <0 0x016e0000 0 0x1c080>;
2326 reg = <0 0x01700000 0 0x31080>;
2337 reg = <0 0x01740000 0 0x1f080>;
2344 reg = <0x0 0x01f40000 0x0 0x40000>;
2350 reg = <0x0 0x1fc0000 0x0 0x30000>;
2355 reg = <0x0 0x03d00000 0x0 0x40000>,
2356 <0x0 0x03d9e000 0x0 0x1000>,
2357 <0x0 0x03d61000 0x0 0x800>;
2364 iommus = <&adreno_smmu 0 0x400>,
2365 <&adreno_smmu 1 0x400>;
2445 reg = <0x0 0x03d6a000 0x0 0x35000>,
2446 <0x0 0x03d50000 0x0 0x10000>,
2447 <0x0 0x0b290000 0x0 0x10000>;
2474 iommus = <&adreno_smmu 5 0x400>;
2497 reg = <0x0 0x03d90000 0x0 0xa000>;
2509 reg = <0x0 0x03da0000 0x0 0x40000>;
2557 reg = <0 0x088e3000 0 0x400>;
2559 #phy-cells = <0>;
2569 reg = <0 0x088e8000 0 0x3000>;
2590 #size-cells = <0>;
2592 port@0 {
2593 reg = <0>;
2619 reg = <0 0x02400000 0 0x4000>;
2622 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2640 qcom,smem-states = <&smp2p_slpi_out 0>;
2661 #size-cells = <0>;
2666 iommus = <&apps_smmu 0x0541 0x0>;
2672 iommus = <&apps_smmu 0x0542 0x0>;
2678 iommus = <&apps_smmu 0x0543 0x0>;
2687 reg = <0x0 0x03000000 0x0 0x10000>;
2690 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2708 qcom,smem-states = <&smp2p_adsp_out 0>;
2729 #size-cells = <0>;
2734 #sound-dai-cells = <0>;
2740 iommus = <&apps_smmu 0x1801 0x0>;
2768 #size-cells = <0>;
2773 iommus = <&apps_smmu 0x1803 0x0>;
2779 iommus = <&apps_smmu 0x1804 0x0>;
2785 iommus = <&apps_smmu 0x1805 0x0>;
2793 reg = <0 0x031e0000 0 0x1000>;
2801 #clock-cells = <0>;
2808 reg = <0 0x031f0000 0 0x2000>;
2814 pinctrl-0 = <&wsa2_swr_active>;
2820 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2821 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2822 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2823 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2824 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2825 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2826 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2827 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2828 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2831 #size-cells = <0>;
2838 reg = <0 0x03200000 0 0x1000>;
2846 #clock-cells = <0>;
2853 reg = <0 0x03210000 0 0x2000>;
2858 qcom,din-ports = <0>;
2861 pinctrl-0 = <&rx_swr_active>;
2864 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2865 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2866 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2867 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2868 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2869 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2870 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2871 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2872 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2875 #size-cells = <0>;
2882 reg = <0 0x03220000 0 0x1000>;
2890 #clock-cells = <0>;
2897 reg = <0 0x03240000 0 0x1000>;
2905 #clock-cells = <0>;
2912 reg = <0 0x03250000 0 0x2000>;
2918 pinctrl-0 = <&wsa_swr_active>;
2924 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2925 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2926 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2927 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2928 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2929 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2930 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2931 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2932 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2935 #size-cells = <0>;
2942 reg = <0 0x033b0000 0 0x2000>;
2951 pinctrl-0 = <&tx_swr_active>;
2955 qcom,dout-ports = <0>;
2956 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2957 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2958 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2959 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2960 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2961 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2962 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2963 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2964 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2967 #size-cells = <0>;
2974 reg = <0 0x033f0000 0 0x1000>;
2981 #clock-cells = <0>;
2989 reg = <0 0x32300000 0 0x10000>;
2992 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3010 qcom,smem-states = <&smp2p_cdsp_out 0>;
3031 #size-cells = <0>;
3036 iommus = <&apps_smmu 0x2161 0x0400>,
3037 <&apps_smmu 0x1021 0x1420>;
3043 iommus = <&apps_smmu 0x2162 0x0400>,
3044 <&apps_smmu 0x1022 0x1420>;
3050 iommus = <&apps_smmu 0x2163 0x0400>,
3051 <&apps_smmu 0x1023 0x1420>;
3057 iommus = <&apps_smmu 0x2164 0x0400>,
3058 <&apps_smmu 0x1024 0x1420>;
3064 iommus = <&apps_smmu 0x2165 0x0400>,
3065 <&apps_smmu 0x1025 0x1420>;
3071 iommus = <&apps_smmu 0x2166 0x0400>,
3072 <&apps_smmu 0x1026 0x1420>;
3078 iommus = <&apps_smmu 0x2167 0x0400>,
3079 <&apps_smmu 0x1027 0x1420>;
3085 iommus = <&apps_smmu 0x2168 0x0400>,
3086 <&apps_smmu 0x1028 0x1420>;
3096 reg = <0x0 0x04080000 0x0 0x10000>;
3099 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
3118 qcom,smem-states = <&smp2p_modem_out 0>;
3136 reg = <0 0x0aaf0000 0 0x10000>;
3148 reg = <0 0x0ac15000 0 0x1000>;
3162 pinctrl-0 = <&cci0_default &cci1_default>;
3168 #size-cells = <0>;
3170 cci0_i2c0: i2c-bus@0 {
3171 reg = <0>;
3174 #size-cells = <0>;
3181 #size-cells = <0>;
3187 reg = <0 0x0ac16000 0 0x1000>;
3201 pinctrl-0 = <&cci2_default &cci3_default>;
3207 #size-cells = <0>;
3209 cci1_i2c0: i2c-bus@0 {
3210 reg = <0>;
3213 #size-cells = <0>;
3220 #size-cells = <0>;
3226 reg = <0 0x0ade0000 0 0x20000>;
3241 reg = <0 0x0ae00000 0 0x1000>;
3245 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3246 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3266 iommus = <&apps_smmu 0x2800 0x402>;
3276 reg = <0 0x0ae01000 0 0x8f000>,
3277 <0 0x0aeb0000 0 0x2008>;
3300 interrupts = <0>;
3304 #size-cells = <0>;
3306 port@0 {
3307 reg = <0>;
3360 reg = <0 0xae90000 0 0x200>,
3361 <0 0xae90200 0 0x200>,
3362 <0 0xae90400 0 0xc00>,
3363 <0 0xae91000 0 0x400>,
3364 <0 0xae91400 0 0x400>;
3386 #sound-dai-cells = <0>;
3395 #size-cells = <0>;
3397 port@0 {
3398 reg = <0>;
3440 reg = <0 0x0ae94000 0 0x400>;
3460 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3469 #size-cells = <0>;
3475 #size-cells = <0>;
3477 port@0 {
3478 reg = <0>;
3513 reg = <0 0x0ae94400 0 0x200>,
3514 <0 0x0ae94600 0 0x280>,
3515 <0 0x0ae94900 0 0x260>;
3521 #phy-cells = <0>;
3532 reg = <0 0x0ae96000 0 0x400>;
3552 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3561 #size-cells = <0>;
3567 #size-cells = <0>;
3569 port@0 {
3570 reg = <0>;
3586 reg = <0 0x0ae96400 0 0x200>,
3587 <0 0x0ae96600 0 0x280>,
3588 <0 0x0ae96900 0 0x260>;
3594 #phy-cells = <0>;
3606 reg = <0 0x0af00000 0 0x20000>;
3611 <&mdss_dsi0_phy 0>,
3613 <&mdss_dsi1_phy 0>,
3617 <0>, /* dp1 */
3618 <0>,
3619 <0>, /* dp2 */
3620 <0>,
3621 <0>, /* dp3 */
3622 <0>;
3632 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3633 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3642 reg = <0 0x0c263000 0 0x1000>, /* TM */
3643 <0 0x0c222000 0 0x1000>; /* SROT */
3653 reg = <0 0x0c265000 0 0x1000>, /* TM */
3654 <0 0x0c223000 0 0x1000>; /* SROT */
3664 reg = <0 0x0c300000 0 0x400>;
3669 #clock-cells = <0>;
3674 reg = <0 0x0c3f0000 0 0x400>;
3679 reg = <0 0x0c400000 0 0x00003000>,
3680 <0 0x0c500000 0 0x00400000>,
3681 <0 0x0c440000 0 0x00080000>,
3682 <0 0x0c4c0000 0 0x00010000>,
3683 <0 0x0c42d000 0 0x00010000>;
3691 qcom,ee = <0>;
3692 qcom,channel = <0>;
3696 #size-cells = <0>;
3701 reg = <0 0x0ed18000 0 0x1000>;
3710 reg = <0 0x0f100000 0 0x300000>;
3716 gpio-ranges = <&tlmm 0 0 211>;
4220 reg = <0 0x03440000 0x0 0x20000>,
4221 <0 0x034d0000 0x0 0x10000>;
4224 gpio-ranges = <&lpass_tlmm 0 0 23>;
4335 reg = <0x0 0x10002000 0x0 0x1000>,
4336 <0x0 0x16280000 0x0 0x180000>;
4354 reg = <0x0 0x10041000 0x0 0x1000>;
4361 #size-cells = <0>;
4385 reg = <0x0 0x10042000 0x0 0x1000>;
4392 #size-cells = <0>;
4423 reg = <0x0 0x10045000 0x0 0x1000>;
4430 #size-cells = <0>;
4432 port@0 {
4433 reg = <0>;
4461 reg = <0x0 0x10046000 0x0 0x1000>;
4488 reg = <0x0 0x10048000 0x0 0x1000>;
4490 iommus = <&apps_smmu 0x0600 0>;
4491 arm,buffer-size = <0x10000>;
4509 reg = <0x0 0x1004e000 0x0 0x1000>;
4538 reg = <0x0 0x10b04000 0x0 0x1000>;
4545 #size-cells = <0>;
4576 reg = <0x0 0x10b05000 0x0 0x1000>;
4602 reg = <0x0 0x10b06000 0x0 0x1000>;
4631 reg = <0x0 0x10b08000 0x0 0x1000>;
4639 #size-cells = <0>;
4641 port@0 {
4642 reg = <0>;
4671 reg = <0x0 0x10b09000 0x0 0x1000>;
4689 reg = <0x0 0x10b0d000 0x0 0x1000>;
4706 reg = <0x0 0x10c28000 0x0 0x1000>;
4723 reg = <0x0 0x10c29000 0x0 0x1000>;
4740 reg = <0x0 0x10c2a000 0x0 0x1000>;
4748 reg = <0x0 0x10c2b000 0x0 0x1000>;
4756 reg = <0x0 0x10c2e000 0x0 0x1000>;
4764 #size-cells = <0>;
4796 reg = <0x0 0x10c2f000 0x0 0x1000>;
4824 reg = <0x0 0x13810000 0x0 0x1000>;
4851 reg = <0x0 0x138e0000 0x0 0x1000>;
4859 reg = <0x0 0x138f0000 0x0 0x1000>;
4867 reg = <0x0 0x13900000 0x0 0x1000>;
4875 reg = <0 0x146aa000 0 0x1000>;
4876 ranges = <0 0 0x146aa000 0x1000>;
4883 reg = <0x94c 0xc8>;
4889 reg = <0 0x15000000 0 0x100000>;
4997 redistributor-stride = <0x0 0x40000>;
4998 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4999 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
5007 reg = <0x0 0x17140000 0x0 0x20000>;
5017 ranges = <0 0 0 0x20000000>;
5018 reg = <0x0 0x17420000 0x0 0x1000>;
5022 frame-number = <0>;
5025 reg = <0x17421000 0x1000>,
5026 <0x17422000 0x1000>;
5032 reg = <0x17423000 0x1000>;
5039 reg = <0x17425000 0x1000>;
5046 reg = <0x17427000 0x1000>;
5053 reg = <0x17429000 0x1000>;
5060 reg = <0x1742b000 0x1000>;
5067 reg = <0x1742d000 0x1000>;
5075 reg = <0x0 0x17a00000 0x0 0x10000>,
5076 <0x0 0x17a10000 0x0 0x10000>,
5077 <0x0 0x17a20000 0x0 0x10000>,
5078 <0x0 0x17a30000 0x0 0x10000>;
5079 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
5083 qcom,tcs-offset = <0xd00>;
5086 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5169 reg = <0 0x17d91000 0 0x1000>,
5170 <0 0x17d92000 0 0x1000>,
5171 <0 0x17d93000 0 0x1000>;
5178 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5185 reg = <0 0x19100000 0 0xbb800>;
5192 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
5193 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
5194 <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>;
5204 reg = <0 0x01d84000 0 0x3000>;
5215 iommus = <&apps_smmu 0xe0 0x0>;
5218 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
5219 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
5241 <0 0>,
5242 <0 0>,
5245 <0 0>,
5246 <0 0>,
5247 <0 0>;
5255 reg = <0 0x01d87000 0 0x1000>;
5264 resets = <&ufs_mem_hc 0>;
5268 #phy-cells = <0>;
5276 reg = <0 0x01d88000 0 0x8000>;
5282 reg = <0 0x01dc4000 0 0x28000>;
5285 qcom,ee = <0>;
5287 iommus = <&apps_smmu 0x584 0x11>,
5288 <&apps_smmu 0x588 0x0>,
5289 <&apps_smmu 0x598 0x5>,
5290 <&apps_smmu 0x59a 0x0>,
5291 <&apps_smmu 0x59f 0x0>;
5296 reg = <0 0x01dfa000 0 0x6000>;
5299 iommus = <&apps_smmu 0x584 0x11>,
5300 <&apps_smmu 0x588 0x0>,
5301 <&apps_smmu 0x598 0x5>,
5302 <&apps_smmu 0x59a 0x0>,
5303 <&apps_smmu 0x59f 0x0>;
5304 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
5310 reg = <0 0x08804000 0 0x1000>;
5321 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
5322 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
5324 iommus = <&apps_smmu 0x4a0 0x0>;
5331 sdhci-caps-mask = <0x3 0x0>;
5352 reg = <0 0x0a6f8800 0 0x400>;
5390 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
5391 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
5396 reg = <0 0x0a600000 0 0xcd00>;
5398 iommus = <&apps_smmu 0x0 0x0>;
5408 #size-cells = <0>;
5410 port@0 {
5411 reg = <0>;
5430 reg = <0 0x320c0000 0 0x10000>;
5437 reg = <0 0x03c40000 0 0x17200>;
5448 thermal-sensors = <&tsens0 0>;
5820 thermal-sensors = <&tsens1 0>;