Lines Matching +full:0 +full:x05e94400
33 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
68 reg = <0x0 0x1>;
69 clocks = <&cpufreq_hw 0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x2>;
83 clocks = <&cpufreq_hw 0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0x0 0x3>;
97 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
110 reg = <0x0 0x100>;
129 reg = <0x0 0x101>;
143 reg = <0x0 0x102>;
157 reg = <0x0 0x103>;
209 little_cpu_sleep_0: cpu-sleep-0-0 {
212 arm,psci-suspend-param = <0x40000003>;
219 big_cpu_sleep_0: cpu-sleep-1-0 {
222 arm,psci-suspend-param = <0x40000003>;
231 cluster_0_sleep_0: cluster-sleep-0-0 {
234 arm,psci-suspend-param = <0x40000022>;
240 cluster_0_sleep_1: cluster-sleep-0-1 {
243 arm,psci-suspend-param = <0x41000044>;
249 cluster_1_sleep_0: cluster-sleep-1-0 {
252 arm,psci-suspend-param = <0x40000042>;
261 arm,psci-suspend-param = <0x41000044>;
281 reg = <0 0x80000000 0 0>;
313 #power-domain-cells = <0>;
319 #power-domain-cells = <0>;
325 #power-domain-cells = <0>;
331 #power-domain-cells = <0>;
337 #power-domain-cells = <0>;
343 #power-domain-cells = <0>;
349 #power-domain-cells = <0>;
355 #power-domain-cells = <0>;
361 #power-domain-cells = <0>;
366 #power-domain-cells = <0>;
379 mboxes = <&apcs_glb 0>;
443 reg = <0x0 0x45700000 0x0 0x600000>;
448 reg = <0x0 0x45e00000 0x0 0x140000>;
453 reg = <0x0 0x45fff000 0x0 0x1000>;
459 reg = <0x0 0x46000000 0x0 0x200000>;
467 reg = <0x0 0x46200000 0x0 0x1e00000>;
472 reg = <0x0 0x4ab00000 0x0 0x6900000>;
477 reg = <0x0 0x51400000 0x0 0x500000>;
482 reg = <0x0 0x51900000 0x0 0x100000>;
487 reg = <0x0 0x51a00000 0x0 0x1e00000>;
492 reg = <0x0 0x53800000 0x0 0x2800000>;
497 reg = <0x0 0x56100000 0x0 0x10000>;
502 reg = <0x0 0x56110000 0x0 0x5000>;
507 reg = <0x0 0x56115000 0x0 0x2000>;
512 reg = <0x0 0x5c000000 0x0 0x00f00000>;
517 reg = <0x0 0x5cf00000 0x0 0x0100000>;
522 reg = <0x0 0x60000000 0x0 0x3900000>;
528 reg = <0x0 0x89b01000 0x0 0x200000>;
544 qcom,local-pid = <0>;
568 qcom,local-pid = <0>;
592 qcom,local-pid = <0>;
608 soc: soc@0 {
612 ranges = <0 0 0 0 0x10 0>;
613 dma-ranges = <0 0 0 0 0x10 0>;
617 reg = <0x0 0x00340000 0x0 0x20000>;
623 reg = <0x0 0x003c0000 0x0 0x40000>;
628 reg = <0x0 0x00500000 0x0 0x400000>,
629 <0x0 0x00900000 0x0 0x400000>,
630 <0x0 0x00d00000 0x0 0x400000>;
634 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
816 reg = <0x0 0x0a7c0000 0x0 0x20000>,
817 <0x0 0x0a950000 0x0 0x10000>;
824 gpio-ranges = <&lpass_tlmm 0 0 19>;
830 reg = <0x0 0x01400000 0x0 0x1f0000>;
840 reg = <0x0 0x01613000 0x0 0x180>;
841 #phy-cells = <0>;
854 reg = <0x0 0x01b04000 0x0 0x24000>;
859 qcom,ee = <0>;
861 iommus = <&apps_smmu 0x92 0>,
862 <&apps_smmu 0x94 0x11>,
863 <&apps_smmu 0x96 0x11>,
864 <&apps_smmu 0x98 0x1>,
865 <&apps_smmu 0x9F 0>;
870 reg = <0x0 0x01b3a000 0x0 0x6000>;
876 iommus = <&apps_smmu 0x92 0>,
877 <&apps_smmu 0x94 0x11>,
878 <&apps_smmu 0x96 0x11>,
879 <&apps_smmu 0x98 0x1>,
880 <&apps_smmu 0x9F 0>;
885 reg = <0x0 0x01615000 0x0 0x1000>;
900 #clock-cells = <0>;
903 #phy-cells = <0>;
906 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
912 #size-cells = <0>;
914 port@0 {
915 reg = <0>;
933 reg = <0x0 0x01880000 0x0 0x5f080>;
962 reg = <0x0 0x01900000 0x0 0x6200>;
970 reg = <0x0 0x01b40000 0x0 0x7000>;
975 reg = <0x25b 0x1>;
980 reg = <0x6006 0x2>;
987 reg = <0x0 0x01b53000 0x0 0x1000>;
994 reg = <0x0 0x01b8e300 0x0 0x600>;
1004 opp-0 {
1048 reg = <0x0 0x01c40000 0x0 0x1100>,
1049 <0x0 0x01e00000 0x0 0x2000000>,
1050 <0x0 0x03e00000 0x0 0x100000>,
1051 <0x0 0x03f00000 0x0 0xa0000>,
1052 <0x0 0x01c0a000 0x0 0x26000>;
1056 qcom,ee = <0>;
1057 qcom,channel = <0>;
1059 #size-cells = <0>;
1066 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
1067 <0x0 0x04410000 0x0 0x8>; /* SROT */
1077 reg = <0x0 0x04480000 0x0 0x80000>;
1083 reg = <0x0 0x045f0000 0x0 0x7000>;
1088 reg = <0x0 0x04690000 0x0 0x10000>;
1093 reg = <0x0 0x04744000 0x0 0x1000>,
1094 <0x0 0x04745000 0x0 0x1000>,
1095 <0x0 0x04748000 0x0 0x8000>;
1112 iommus = <&apps_smmu 0x00c0 0x0>;
1151 reg = <0x0 0x04784000 0x0 0x1000>;
1165 iommus = <&apps_smmu 0x00a0 0x0>;
1175 qcom,dll-config = <0x0007642c>;
1176 qcom,ddr-config = <0x80040868>;
1200 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
1211 iommus = <&apps_smmu 0x100 0>;
1231 <0 0>,
1232 <0 0>,
1234 <0 0>,
1235 <0 0>,
1236 <0 0>,
1244 reg = <0x0 0x04807000 0x0 0x1000>;
1255 resets = <&ufs_mem_hc 0>;
1258 #phy-cells = <0>;
1265 reg = <0x0 0x04a00000 0x0 0x60000>;
1277 dma-channel-mask = <0xf>;
1278 iommus = <&apps_smmu 0xf6 0x0>;
1285 reg = <0x0 0x04ac0000 0x0 0x2000>;
1291 iommus = <&apps_smmu 0xe3 0x0>;
1297 reg = <0x0 0x04a80000 0x0 0x4000>;
1301 pinctrl-0 = <&qup_i2c0_default>;
1303 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1304 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1316 #size-cells = <0>;
1322 reg = <0x0 0x04a80000 0x0 0x4000>;
1326 pinctrl-0 = <&qup_spi0_default>;
1328 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1329 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1341 #size-cells = <0>;
1347 reg = <0x0 0x04a84000 0x0 0x4000>;
1351 pinctrl-0 = <&qup_i2c1_default>;
1353 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1366 #size-cells = <0>;
1372 reg = <0x0 0x04a84000 0x0 0x4000>;
1376 pinctrl-0 = <&qup_spi1_default>;
1378 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1391 #size-cells = <0>;
1397 reg = <0x0 0x04a88000 0x0 0x4000>;
1401 pinctrl-0 = <&qup_i2c2_default>;
1403 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1416 #size-cells = <0>;
1422 reg = <0x0 0x04a88000 0x0 0x4000>;
1426 pinctrl-0 = <&qup_spi2_default>;
1428 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1441 #size-cells = <0>;
1447 reg = <0x0 0x04a8c000 0x0 0x4000>;
1451 pinctrl-0 = <&qup_i2c3_default>;
1453 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1466 #size-cells = <0>;
1472 reg = <0x0 0x04a8c000 0x0 0x4000>;
1476 pinctrl-0 = <&qup_spi3_default>;
1478 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1491 #size-cells = <0>;
1497 reg = <0x0 0x04a8c000 0x0 0x4000>;
1514 reg = <0x0 0x04a90000 0x0 0x4000>;
1518 pinctrl-0 = <&qup_i2c4_default>;
1520 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1533 #size-cells = <0>;
1539 reg = <0x0 0x04a90000 0x0 0x4000>;
1543 pinctrl-0 = <&qup_spi4_default>;
1545 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1558 #size-cells = <0>;
1564 reg = <0x0 0x04a90000 0x0 0x4000>;
1579 reg = <0x0 0x04a94000 0x0 0x4000>;
1583 pinctrl-0 = <&qup_i2c5_default>;
1585 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1598 #size-cells = <0>;
1604 reg = <0x0 0x04a94000 0x0 0x4000>;
1608 pinctrl-0 = <&qup_spi5_default>;
1610 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1623 #size-cells = <0>;
1630 reg = <0x0 0x04ef8800 0x0 0x400>;
1670 reg = <0x0 0x04e00000 0x0 0xcd00>;
1674 iommus = <&apps_smmu 0x120 0x0>;
1678 snps,hird-threshold = /bits/ 8 <0x10>;
1686 #size-cells = <0>;
1688 port@0 {
1689 reg = <0>;
1708 reg = <0x0 0x05900000 0x0 0x40000>;
1727 iommus = <&adreno_smmu 0 1>;
1748 opp-supported-hw = <0x1f>;
1754 opp-supported-hw = <0x1f>;
1760 opp-supported-hw = <0x1f>;
1766 opp-supported-hw = <0xf>;
1772 opp-supported-hw = <0x7>;
1778 opp-supported-hw = <0x7>;
1785 opp-supported-hw = <0x4>;
1791 opp-supported-hw = <0x3>;
1798 reg = <0x0 0x0596a000 0x0 0x30000>;
1807 reg = <0x0 0x05990000 0x0 0x9000>;
1819 reg = <0x0 0x059a0000 0x0 0x10000>;
1844 reg = <0x0 0x05e00000 0x0 0x1000>;
1857 iommus = <&apps_smmu 0x420 0x2>,
1858 <&apps_smmu 0x421 0x0>;
1875 reg = <0x0 0x05e01000 0x0 0x8f000>,
1876 <0x0 0x05eb0000 0x0 0x2008>;
1896 interrupts = <0>;
1900 #size-cells = <0>;
1902 port@0 {
1903 reg = <0>;
1942 reg = <0x0 0x05e94000 0x0 0x400>;
1963 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1970 #size-cells = <0>;
1976 #size-cells = <0>;
1978 port@0 {
1979 reg = <0>;
2014 reg = <0x0 0x05e94400 0x0 0x100>,
2015 <0x0 0x05e94500 0x0 0x300>,
2016 <0x0 0x05e94800 0x0 0x188>;
2022 #phy-cells = <0>;
2034 reg = <0x0 0x05f00000 0 0x20000>;
2037 <&mdss_dsi0_phy 0>,
2047 reg = <0x0 0x06080000 0x0 0x10000>;
2050 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2065 qcom,smem-states = <&modem_smp2p_out 0>;
2080 reg = <0x0 0x08002000 0x0 0x1000>,
2081 <0x0 0x0e280000 0x0 0x180000>;
2100 reg = <0x0 0x08010000 0x0 0x1000>;
2110 reg = <0x0 0x08011000 0x0 0x1000>;
2120 reg = <0x0 0x08012000 0x0 0x1000>;
2130 reg = <0x0 0x08013000 0x0 0x1000>;
2140 reg = <0x0 0x08014000 0x0 0x1000>;
2150 reg = <0x0 0x08015000 0x0 0x1000>;
2160 reg = <0x0 0x08016000 0x0 0x1000>;
2170 reg = <0x0 0x08017000 0x0 0x1000>;
2180 reg = <0x0 0x08018000 0x0 0x1000>;
2190 reg = <0x0 0x08019000 0x0 0x1000>;
2200 reg = <0x0 0x0801a000 0x0 0x1000>;
2210 reg = <0x0 0x0801b000 0x0 0x1000>;
2220 reg = <0x0 0x0801c000 0x0 0x1000>;
2230 reg = <0x0 0x0801d000 0x0 0x1000>;
2240 reg = <0x0 0x0801e000 0x0 0x1000>;
2250 reg = <0x0 0x0801f000 0x0 0x1000>;
2260 reg = <0x0 0x08046000 0x0 0x1000>;
2286 reg = <0x0 0x08047000 0x0 0x1000>;
2312 reg = <0x0 0x08048000 0x0 0x1000>;
2330 reg = <0x0 0x08041000 0x0 0x1000>;
2356 reg = <0x0 0x08042000 0x0 0x1000>;
2382 reg = <0x0 0x08045000 0x0 0x1000>;
2399 #size-cells = <0>;
2401 port@0 {
2402 reg = <0>;
2419 reg = <0x0 0x09040000 0x0 0x1000>;
2440 reg = <0x0 0x09140000 0x0 0x1000>;
2461 reg = <0x0 0x09240000 0x0 0x1000>;
2482 reg = <0x0 0x09340000 0x0 0x1000>;
2503 reg = <0x0 0x09440000 0x0 0x1000>;
2524 reg = <0x0 0x09540000 0x0 0x1000>;
2545 reg = <0x0 0x09640000 0x0 0x1000>;
2566 reg = <0x0 0x09740000 0x0 0x1000>;
2587 reg = <0x0 0x09800000 0x0 0x1000>;
2604 #size-cells = <0>;
2606 port@0 {
2607 reg = <0>;
2666 reg = <0x0 0x09810000 0x0 0x1000>;
2692 reg = <0x0 0x0a400000 0x0 0x4040>;
2695 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2710 qcom,smem-states = <&adsp_smp2p_out 0>;
2726 #size-cells = <0>;
2743 #size-cells = <0>;
2761 #size-cells = <0>;
2763 iommus = <&apps_smmu 0x1c1 0x0>;
2765 dai@0 {
2786 #sound-dai-cells = <0>;
2797 #size-cells = <0>;
2802 iommus = <&apps_smmu 0x01c3 0x0>;
2808 iommus = <&apps_smmu 0x01c4 0x0>;
2814 iommus = <&apps_smmu 0x01c5 0x0>;
2820 iommus = <&apps_smmu 0x01c6 0x0>;
2826 iommus = <&apps_smmu 0x01c7 0x0>;
2834 reg = <0x0 0x0b300000 0x0 0x4040>;
2837 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2851 qcom,smem-states = <&cdsp_smp2p_out 0>;
2868 #size-cells = <0>;
2873 iommus = <&apps_smmu 0x0c01 0x0>;
2879 iommus = <&apps_smmu 0x0c02 0x0>;
2885 iommus = <&apps_smmu 0x0c03 0x0>;
2891 iommus = <&apps_smmu 0x0c04 0x0>;
2897 iommus = <&apps_smmu 0x0c05 0x0>;
2903 iommus = <&apps_smmu 0x0c06 0x0>;
2913 reg = <0x0 0x0c600000 0x0 0x80000>;
2986 reg = <0x0 0x0c800000 0x0 0x800000>;
3001 iommus = <&apps_smmu 0x1a0 0x1>;
3008 reg = <0x0 0x0f017000 0x0 0x1000>;
3016 reg = <0x0 0x0f111000 0x0 0x1000>;
3023 reg = <0x0 0x0f120000 0x0 0x1000>;
3026 ranges = <0x0 0x0 0x0 0x0 0x20000000>;
3030 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
3031 frame-number = <0>;
3037 reg = <0x0 0x0f123000 0x1000>;
3044 reg = <0x0 0x0f124000 0x1000>;
3051 reg = <0x0 0x0f125000 0x1000>;
3058 reg = <0x0 0x0f126000 0x1000>;
3065 reg = <0x0 0x0f127000 0x1000>;
3072 reg = <0x0 0x0f128000 0x1000>;
3081 reg = <0x0 0x0f200000 0x0 0x10000>,
3082 <0x0 0x0f300000 0x0 0x100000>;
3087 redistributor-stride = <0x0 0x20000>;
3093 reg = <0x0 0x0f521000 0x0 0x1000>,
3094 <0x0 0x0f523000 0x0 0x1000>;
3107 thermal-sensors = <&tsens0 0>;
3451 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;