Lines Matching +full:0 +full:x0c40a000
78 #clock-cells = <0>;
85 #clock-cells = <0>;
92 #size-cells = <0>;
94 cpu0: cpu@0 {
97 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
126 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw 0>;
131 qcom,freq-domain = <&cpufreq_hw 0>;
150 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw 0>;
155 qcom,freq-domain = <&cpufreq_hw 0>;
174 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw 0>;
179 qcom,freq-domain = <&cpufreq_hw 0>;
198 reg = <0x0 0x400>;
222 reg = <0x0 0x500>;
246 reg = <0x0 0x600>;
270 reg = <0x0 0x700>;
330 little_cpu_sleep_0: cpu-sleep-0-0 {
333 arm,psci-suspend-param = <0x40000004>;
340 big_cpu_sleep_0: cpu-sleep-1-0 {
343 arm,psci-suspend-param = <0x40000004>;
352 cluster_sleep_0: cluster-sleep-0 {
354 arm,psci-suspend-param = <0x4100c244>;
371 reg = <0 0x80000000 0 0>;
721 #power-domain-cells = <0>;
727 #power-domain-cells = <0>;
733 #power-domain-cells = <0>;
739 #power-domain-cells = <0>;
745 #power-domain-cells = <0>;
751 #power-domain-cells = <0>;
757 #power-domain-cells = <0>;
763 #power-domain-cells = <0>;
769 #power-domain-cells = <0>;
780 reg = <0 0x85700000 0 0x600000>;
785 reg = <0 0x85e00000 0 0x100000>;
790 reg = <0 0x85fc0000 0 0x20000>;
796 reg = <0x0 0x85fe0000 0 0x20000>;
802 reg = <0x0 0x86000000 0 0x200000>;
808 reg = <0 0x86200000 0 0x2d00000>;
814 reg = <0 0x88f00000 0 0x200000>;
822 reg = <0 0x8ab00000 0 0x1400000>;
827 reg = <0 0x8bf00000 0 0x500000>;
832 reg = <0 0x8c400000 0 0x10000>;
837 reg = <0 0x8c410000 0 0x5000>;
842 reg = <0 0x8c415000 0 0x2000>;
847 reg = <0 0x8c500000 0 0x1a00000>;
852 reg = <0 0x8df00000 0 0x100000>;
857 reg = <0 0x8e000000 0 0x7800000>;
862 reg = <0 0x95800000 0 0x500000>;
867 reg = <0 0x95d00000 0 0x800000>;
872 reg = <0 0x96500000 0 0x200000>;
877 reg = <0 0x96700000 0 0x1400000>;
882 reg = <0 0x97b00000 0 0x100000>;
887 alloc-ranges = <0 0xa0000000 0 0x20000000>;
888 size = <0 0x4000>;
894 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
895 alignment = <0x0 0x400000>;
896 size = <0x0 0x1000000>;
905 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
919 qcom,smem-states = <&adsp_smp2p_out 0>;
935 #size-cells = <0>;
951 #size-cells = <0>;
963 #size-cells = <0>;
965 iommus = <&apps_smmu 0x1821 0x0>;
975 #sound-dai-cells = <0>;
986 #size-cells = <0>;
991 iommus = <&apps_smmu 0x1823 0x0>;
997 iommus = <&apps_smmu 0x1824 0x0>;
1007 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1021 qcom,smem-states = <&cdsp_smp2p_out 0>;
1037 #size-cells = <0>;
1042 iommus = <&apps_smmu 0x1401 0x30>;
1048 iommus = <&apps_smmu 0x1402 0x30>;
1054 iommus = <&apps_smmu 0x1403 0x30>;
1060 iommus = <&apps_smmu 0x1404 0x30>;
1066 iommus = <&apps_smmu 0x1405 0x30>;
1072 iommus = <&apps_smmu 0x1406 0x30>;
1078 iommus = <&apps_smmu 0x1407 0x30>;
1084 iommus = <&apps_smmu 0x1408 0x30>;
1098 qcom,local-pid = <0>;
1122 qcom,local-pid = <0>;
1143 qcom,local-pid = <0>;
1174 qcom,local-pid = <0>;
1189 soc: soc@0 {
1192 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0>;
1198 reg = <0 0x00100000 0 0x1f0000>;
1217 reg = <0 0x00784000 0 0x8ff>;
1222 reg = <0x1eb 0x1>;
1227 reg = <0x1eb 0x2>;
1234 reg = <0 0x00793000 0 0x1000>;
1242 reg = <0 0x00800000 0 0x60000>;
1257 dma-channel-mask = <0xfa>;
1258 iommus = <&apps_smmu 0x0016 0x0>;
1264 reg = <0 0x008c0000 0 0x6000>;
1268 iommus = <&apps_smmu 0x3 0x0>;
1272 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1278 reg = <0 0x00880000 0 0x4000>;
1282 pinctrl-0 = <&qup_i2c0_default>;
1285 #size-cells = <0>;
1288 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1292 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1293 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1300 reg = <0 0x00880000 0 0x4000>;
1304 pinctrl-0 = <&qup_spi0_default>;
1307 #size-cells = <0>;
1308 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1311 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1312 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1319 reg = <0 0x00880000 0 0x4000>;
1323 pinctrl-0 = <&qup_uart0_default>;
1327 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1335 reg = <0 0x00884000 0 0x4000>;
1339 pinctrl-0 = <&qup_i2c1_default>;
1342 #size-cells = <0>;
1345 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1349 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1357 reg = <0 0x00884000 0 0x4000>;
1361 pinctrl-0 = <&qup_spi1_default>;
1364 #size-cells = <0>;
1365 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1368 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1376 reg = <0 0x00884000 0 0x4000>;
1380 pinctrl-0 = <&qup_uart1_default>;
1384 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1392 reg = <0 0x00888000 0 0x4000>;
1396 pinctrl-0 = <&qup_i2c2_default>;
1399 #size-cells = <0>;
1402 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1406 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1414 reg = <0 0x00888000 0 0x4000>;
1418 pinctrl-0 = <&qup_spi2_default>;
1421 #size-cells = <0>;
1422 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1425 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1433 reg = <0 0x00888000 0 0x4000>;
1437 pinctrl-0 = <&qup_uart2_default>;
1441 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1449 reg = <0 0x0088c000 0 0x4000>;
1453 pinctrl-0 = <&qup_i2c3_default>;
1456 #size-cells = <0>;
1459 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1463 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1471 reg = <0 0x0088c000 0 0x4000>;
1475 pinctrl-0 = <&qup_spi3_default>;
1478 #size-cells = <0>;
1479 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1482 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1490 reg = <0 0x0088c000 0 0x4000>;
1494 pinctrl-0 = <&qup_uart3_default>;
1498 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1506 reg = <0 0x00890000 0 0x4000>;
1510 pinctrl-0 = <&qup_i2c4_default>;
1513 #size-cells = <0>;
1516 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1520 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1528 reg = <0 0x00890000 0 0x4000>;
1532 pinctrl-0 = <&qup_spi4_default>;
1535 #size-cells = <0>;
1536 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1539 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1547 reg = <0 0x00890000 0 0x4000>;
1551 pinctrl-0 = <&qup_uart4_default>;
1555 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1563 reg = <0 0x00894000 0 0x4000>;
1567 pinctrl-0 = <&qup_i2c5_default>;
1570 #size-cells = <0>;
1573 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1577 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1585 reg = <0 0x00894000 0 0x4000>;
1589 pinctrl-0 = <&qup_spi5_default>;
1592 #size-cells = <0>;
1593 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1596 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1604 reg = <0 0x00894000 0 0x4000>;
1608 pinctrl-0 = <&qup_uart5_default>;
1612 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1620 reg = <0 0x00898000 0 0x4000>;
1624 pinctrl-0 = <&qup_i2c6_default>;
1627 #size-cells = <0>;
1630 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1634 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1642 reg = <0 0x00898000 0 0x4000>;
1646 pinctrl-0 = <&qup_spi6_default>;
1649 #size-cells = <0>;
1650 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1653 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1661 reg = <0 0x00898000 0 0x4000>;
1665 pinctrl-0 = <&qup_uart6_default>;
1669 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1677 reg = <0 0x0089c000 0 0x4000>;
1681 pinctrl-0 = <&qup_i2c7_default>;
1684 #size-cells = <0>;
1692 reg = <0 0x0089c000 0 0x4000>;
1696 pinctrl-0 = <&qup_spi7_default>;
1699 #size-cells = <0>;
1700 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1703 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1711 reg = <0 0x0089c000 0 0x4000>;
1715 pinctrl-0 = <&qup_uart7_default>;
1719 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1729 reg = <0 0x00a00000 0 0x60000>;
1744 dma-channel-mask = <0xfa>;
1745 iommus = <&apps_smmu 0x06d6 0x0>;
1751 reg = <0 0x00ac0000 0 0x6000>;
1755 iommus = <&apps_smmu 0x6c3 0x0>;
1759 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1765 reg = <0 0x00a80000 0 0x4000>;
1769 pinctrl-0 = <&qup_i2c8_default>;
1772 #size-cells = <0>;
1775 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1779 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1780 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1787 reg = <0 0x00a80000 0 0x4000>;
1791 pinctrl-0 = <&qup_spi8_default>;
1794 #size-cells = <0>;
1795 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1798 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1799 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1806 reg = <0 0x00a80000 0 0x4000>;
1810 pinctrl-0 = <&qup_uart8_default>;
1814 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1822 reg = <0 0x00a84000 0 0x4000>;
1826 pinctrl-0 = <&qup_i2c9_default>;
1829 #size-cells = <0>;
1832 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1836 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1844 reg = <0 0x00a84000 0 0x4000>;
1848 pinctrl-0 = <&qup_spi9_default>;
1851 #size-cells = <0>;
1852 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1855 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 reg = <0 0x00a84000 0 0x4000>;
1867 pinctrl-0 = <&qup_uart9_default>;
1871 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1879 reg = <0 0x00a88000 0 0x4000>;
1883 pinctrl-0 = <&qup_i2c10_default>;
1886 #size-cells = <0>;
1889 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1893 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1901 reg = <0 0x00a88000 0 0x4000>;
1905 pinctrl-0 = <&qup_spi10_default>;
1908 #size-cells = <0>;
1909 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1912 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1920 reg = <0 0x00a88000 0 0x4000>;
1924 pinctrl-0 = <&qup_uart10_default>;
1928 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1936 reg = <0 0x00a8c000 0 0x4000>;
1940 pinctrl-0 = <&qup_i2c11_default>;
1943 #size-cells = <0>;
1946 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1950 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1958 reg = <0 0x00a8c000 0 0x4000>;
1962 pinctrl-0 = <&qup_spi11_default>;
1965 #size-cells = <0>;
1966 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1969 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1977 reg = <0 0x00a8c000 0 0x4000>;
1981 pinctrl-0 = <&qup_uart11_default>;
1985 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1993 reg = <0 0x00a90000 0 0x4000>;
1997 pinctrl-0 = <&qup_i2c12_default>;
2000 #size-cells = <0>;
2003 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2007 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2015 reg = <0 0x00a90000 0 0x4000>;
2019 pinctrl-0 = <&qup_spi12_default>;
2022 #size-cells = <0>;
2023 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2026 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2034 reg = <0 0x00a90000 0 0x4000>;
2038 pinctrl-0 = <&qup_uart12_default>;
2042 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2050 reg = <0 0x00a94000 0 0x4000>;
2054 pinctrl-0 = <&qup_i2c13_default>;
2057 #size-cells = <0>;
2060 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2064 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2072 reg = <0 0x00a94000 0 0x4000>;
2076 pinctrl-0 = <&qup_spi13_default>;
2079 #size-cells = <0>;
2080 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2083 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2091 reg = <0 0x00a94000 0 0x4000>;
2095 pinctrl-0 = <&qup_uart13_default>;
2099 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2107 reg = <0 0x00a98000 0 0x4000>;
2111 pinctrl-0 = <&qup_i2c14_default>;
2114 #size-cells = <0>;
2117 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2121 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2129 reg = <0 0x00a98000 0 0x4000>;
2133 pinctrl-0 = <&qup_spi14_default>;
2136 #size-cells = <0>;
2137 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2140 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2148 reg = <0 0x00a98000 0 0x4000>;
2152 pinctrl-0 = <&qup_uart14_default>;
2156 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2164 reg = <0 0x00a9c000 0 0x4000>;
2168 pinctrl-0 = <&qup_i2c15_default>;
2171 #size-cells = <0>;
2175 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2179 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2186 reg = <0 0x00a9c000 0 0x4000>;
2190 pinctrl-0 = <&qup_spi15_default>;
2193 #size-cells = <0>;
2194 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2197 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2205 reg = <0 0x00a9c000 0 0x4000>;
2209 pinctrl-0 = <&qup_uart15_default>;
2213 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2222 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2223 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2224 <0 0x01300000 0 0x50000>;
2232 reg = <0x0 0x010a2000 0x0 0x1000>,
2233 <0x0 0x010ae000 0x0 0x2000>;
2238 reg = <0 0x0114a000 0 0x1000>;
2255 opp-0 {
2275 reg = <0 0x01436400 0 0x600>;
2292 opp-0 {
2312 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 0x100000>,
2316 <0 0x01c07000 0 0x1000>;
2319 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xff>;
2326 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2327 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2332 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2353 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &apps_smmu 0x1c1f 0x1>;
2380 pcie@0 {
2382 reg = <0x0 0x0 0x0 0x0 0x0>;
2383 bus-range = <0x01 0xff>;
2393 reg = <0 0x01c06000 0 0x1000>;
2406 #clock-cells = <0>;
2408 #phy-cells = <0>;
2421 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 0x100000>,
2425 <0 0x01c0c000 0 0x1000>;
2429 bus-range = <0x00 0xff>;
2435 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2441 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2467 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &apps_smmu 0x1c0f 0x1>;
2494 pcie@0 {
2496 reg = <0x0 0x0 0x0 0x0 0x0>;
2497 bus-range = <0x01 0xff>;
2507 reg = <0 0x01c0a000 0 0x2000>;
2520 #clock-cells = <0>;
2522 #phy-cells = <0>;
2535 reg = <0 0x01380000 0 0x27200>;
2542 reg = <0 0x014e0000 0 0x400>;
2549 reg = <0 0x01500000 0 0x5080>;
2556 reg = <0 0x01620000 0 0x18080>;
2563 reg = <0 0x016e0000 0 0x15080>;
2570 reg = <0 0x01700000 0 0x1f300>;
2577 reg = <0 0x01740000 0 0x1c100>;
2585 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 0x8000>;
2597 iommus = <&apps_smmu 0x100 0xf>;
2622 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2623 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2633 /bits/ 64 <0>,
2634 /bits/ 64 <0>,
2636 /bits/ 64 <0>,
2637 /bits/ 64 <0>,
2638 /bits/ 64 <0>,
2639 /bits/ 64 <0>,
2646 /bits/ 64 <0>,
2647 /bits/ 64 <0>,
2649 /bits/ 64 <0>,
2650 /bits/ 64 <0>,
2651 /bits/ 64 <0>,
2652 /bits/ 64 <0>,
2661 reg = <0 0x01d87000 0 0x1000>;
2672 resets = <&ufs_mem_hc 0>;
2675 #phy-cells = <0>;
2681 reg = <0 0x01dc4000 0 0x24000>;
2686 qcom,ee = <0>;
2688 iommus = <&apps_smmu 0x704 0x1>,
2689 <&apps_smmu 0x706 0x1>,
2690 <&apps_smmu 0x714 0x1>,
2691 <&apps_smmu 0x716 0x1>;
2696 reg = <0 0x01dfa000 0 0x6000>;
2703 iommus = <&apps_smmu 0x704 0x1>,
2704 <&apps_smmu 0x706 0x1>,
2705 <&apps_smmu 0x714 0x1>,
2706 <&apps_smmu 0x716 0x1>;
2712 iommus = <&apps_smmu 0x720 0x0>,
2713 <&apps_smmu 0x722 0x0>;
2714 reg = <0 0x01e40000 0 0x7000>,
2715 <0 0x01e47000 0 0x2000>,
2716 <0 0x01e04000 0 0x2c000>;
2723 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2733 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2740 qcom,smem-states = <&ipa_smp2p_out 0>,
2750 reg = <0 0x01f40000 0 0x20000>;
2756 reg = <0 0x01f60000 0 0x20000>;
2761 reg = <0 0x03400000 0 0xc00000>;
2767 gpio-ranges = <&tlmm 0 0 151>;
3300 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3305 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3327 qcom,smem-states = <&modem_smp2p_out 0>;
3334 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3365 reg = <0 0x05090000 0 0x9000>;
3379 reg = <0 0x5c00000 0 0x4000>;
3382 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3400 qcom,smem-states = <&slpi_smp2p_out 0>;
3420 #size-cells = <0>;
3422 compute-cb@0 {
3424 reg = <0>;
3432 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 0x180000>;
3451 reg = <0 0x06041000 0 0x1000>;
3467 #size-cells = <0>;
3480 reg = <0 0x06043000 0 0x1000>;
3496 #size-cells = <0>;
3510 reg = <0 0x06045000 0 0x1000>;
3525 #size-cells = <0>;
3527 port@0 {
3528 reg = <0>;
3547 reg = <0 0x06046000 0 0x1000>;
3571 reg = <0 0x06047000 0 0x1000>;
3598 reg = <0 0x06048000 0 0x1000>;
3616 reg = <0 0x07040000 0 0x1000>;
3636 reg = <0 0x07140000 0 0x1000>;
3656 reg = <0 0x07240000 0 0x1000>;
3676 reg = <0 0x07340000 0 0x1000>;
3696 reg = <0 0x07440000 0 0x1000>;
3716 reg = <0 0x07540000 0 0x1000>;
3736 reg = <0 0x07640000 0 0x1000>;
3756 reg = <0 0x07740000 0 0x1000>;
3776 reg = <0 0x07800000 0 0x1000>;
3792 #size-cells = <0>;
3794 port@0 {
3795 reg = <0>;
3862 reg = <0 0x07810000 0 0x1000>;
3888 reg = <0 0x08804000 0 0x1000>;
3898 iommus = <&apps_smmu 0xa0 0xf>;
3931 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu 0x160 0x0>;
3934 #size-cells = <0>;
3946 reg = <0 0x171c0000 0 0x2c000>;
3952 iommus = <&apps_smmu 0x1806 0x0>;
3954 #size-cells = <0>;
3960 reg = <0 0x17d70800 0 0x400>;
3972 reg = <0 0x17d78800 0 0x400>;
3984 reg = <0 0x088e2000 0 0x400>;
3986 #phy-cells = <0>;
3999 reg = <0 0x088e3000 0 0x400>;
4001 #phy-cells = <0>;
4014 reg = <0 0x088e8000 0 0x3000>;
4038 #size-cells = <0>;
4040 port@0 {
4041 reg = <0>;
4067 reg = <0 0x088eb000 0 0x1000>;
4080 #clock-cells = <0>;
4081 #phy-cells = <0>;
4093 reg = <0 0x0a6f8800 0 0x400>;
4130 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4136 reg = <0 0x0a600000 0 0xcd00>;
4138 iommus = <&apps_smmu 0x740 0>;
4149 #size-cells = <0>;
4151 port@0 {
4152 reg = <0>;
4171 reg = <0 0x0a8f8800 0 0x400>;
4208 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4209 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4214 reg = <0 0x0a800000 0 0xcd00>;
4216 iommus = <&apps_smmu 0x760 0>;
4229 reg = <0 0x0aa00000 0 0xff000>;
4247 iommus = <&apps_smmu 0x10a0 0x8>,
4248 <&apps_smmu 0x10b0 0x0>;
4250 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4251 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4301 reg = <0 0x0ab00000 0 0x10000>;
4312 reg = <0 0x0acb3000 0 0x1000>,
4313 <0 0x0acba000 0 0x1000>,
4314 <0 0x0acc8000 0 0x1000>,
4315 <0 0x0ac65000 0 0x1000>,
4316 <0 0x0ac66000 0 0x1000>,
4317 <0 0x0ac67000 0 0x1000>,
4318 <0 0x0ac68000 0 0x1000>,
4319 <0 0x0acaf000 0 0x4000>,
4320 <0 0x0acb6000 0 0x4000>,
4321 <0 0x0acc4000 0 0x4000>;
4431 iommus = <&apps_smmu 0x0808 0x0>,
4432 <&apps_smmu 0x0810 0x8>,
4433 <&apps_smmu 0x0c08 0x0>,
4434 <&apps_smmu 0x0c10 0x8>;
4440 #size-cells = <0>;
4442 port@0 {
4443 reg = <0>;
4463 #size-cells = <0>;
4465 reg = <0 0x0ac4a000 0 0x4000>;
4487 pinctrl-0 = <&cci0_default &cci1_default>;
4492 cci_i2c0: i2c-bus@0 {
4493 reg = <0>;
4496 #size-cells = <0>;
4503 #size-cells = <0>;
4509 reg = <0 0x0ad00000 0 0x10000>;
4519 reg = <0 0x0ae00000 0 0x1000>;
4532 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4533 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4536 iommus = <&apps_smmu 0x880 0x8>,
4537 <&apps_smmu 0xc80 0x8>;
4547 reg = <0 0x0ae01000 0 0x8f000>,
4548 <0 0x0aeb0000 0 0x2008>;
4564 interrupts = <0>;
4568 #size-cells = <0>;
4570 port@0 {
4571 reg = <0>;
4621 reg = <0 0x0ae90000 0 0x200>,
4622 <0 0x0ae90200 0 0x200>,
4623 <0 0x0ae90400 0 0x600>,
4624 <0 0x0ae90a00 0 0x600>,
4625 <0 0x0ae91000 0 0x600>;
4649 #size-cells = <0>;
4650 port@0 {
4651 reg = <0>;
4693 reg = <0 0x0ae94000 0 0x400>;
4712 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4722 #size-cells = <0>;
4726 #size-cells = <0>;
4728 port@0 {
4729 reg = <0>;
4745 reg = <0 0x0ae94400 0 0x200>,
4746 <0 0x0ae94600 0 0x280>,
4747 <0 0x0ae94a00 0 0x1e0>;
4753 #phy-cells = <0>;
4765 reg = <0 0x0ae96000 0 0x400>;
4784 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4794 #size-cells = <0>;
4798 #size-cells = <0>;
4800 port@0 {
4801 reg = <0>;
4817 reg = <0 0x0ae96400 0 0x200>,
4818 <0 0x0ae96600 0 0x280>,
4819 <0 0x0ae96a00 0 0x10e>;
4825 #phy-cells = <0>;
4838 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4848 iommus = <&adreno_smmu 0>;
4855 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4909 reg = <0 0x05040000 0 0x10000>;
4932 reg = <0 0x0506a000 0 0x30000>,
4933 <0 0x0b280000 0 0x10000>,
4934 <0 0x0b480000 0 0x10000>;
4974 reg = <0 0x0af00000 0 0x10000>;
4978 <&mdss_dsi0_phy 0>,
4980 <&mdss_dsi1_phy 0>,
5000 reg = <0 0x0b220000 0 0x30000>;
5001 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
5009 reg = <0 0x0b2e0000 0 0x20000>;
5015 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5016 <0 0x0c222000 0 0x1ff>; /* SROT */
5026 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5027 <0 0x0c223000 0 0x1ff>; /* SROT */
5037 reg = <0 0x0c2a0000 0 0x31000>;
5043 reg = <0 0x0c300000 0 0x400>;
5045 mboxes = <&apss_shared 0>;
5047 #clock-cells = <0>;
5060 reg = <0 0x0c3f0000 0 0x400>;
5065 reg = <0 0x0c440000 0 0x1100>,
5066 <0 0x0c600000 0 0x2000000>,
5067 <0 0x0e600000 0 0x100000>,
5068 <0 0x0e700000 0 0xa0000>,
5069 <0 0x0c40a000 0 0x26000>;
5073 qcom,ee = <0>;
5074 qcom,channel = <0>;
5076 #size-cells = <0>;
5083 reg = <0 0x146bf000 0 0x1000>;
5088 ranges = <0 0 0x146bf000 0x1000>;
5092 reg = <0x94c 0xc8>;
5098 reg = <0 0x15000000 0 0x80000>;
5170 reg = <0x0 0x150c5000 0x0 0x1000>;
5174 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
5179 reg = <0x0 0x150c9000 0x0 0x1000>;
5183 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
5188 reg = <0x0 0x150cd000 0x0 0x1000>;
5192 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
5197 reg = <0x0 0x150d1000 0x0 0x1000>;
5201 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
5206 reg = <0x0 0x150d5000 0x0 0x1000>;
5210 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
5215 reg = <0x0 0x150d9000 0x0 0x1000>;
5218 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
5223 reg = <0x0 0x150dd000 0x0 0x1000>;
5227 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
5232 reg = <0x0 0x150e1000 0x0 0x1000>;
5237 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
5242 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5250 reg = <0 0x17900000 0 0xd080>;
5257 reg = <0 0x17980000 0 0x1000>;
5259 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5264 reg = <0 0x17990000 0 0x1000>;
5271 reg = <0 0x179c0000 0 0x10000>,
5272 <0 0x179d0000 0 0x10000>,
5273 <0 0x179e0000 0 0x10000>;
5274 reg-names = "drv-0", "drv-1", "drv-2";
5278 qcom,tcs-offset = <0xd00>;
5355 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5356 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5363 reg = <0 0x17a40000 0 0x20000>;
5371 reg = <0 0x17184000 0 0x2a000>;
5377 iommus = <&apps_smmu 0x1806 0x0>;
5383 ranges = <0 0 0 0x20000000>;
5385 reg = <0 0x17c90000 0 0x1000>;
5388 frame-number = <0>;
5391 reg = <0x17ca0000 0x1000>,
5392 <0x17cb0000 0x1000>;
5398 reg = <0x17cc0000 0x1000>;
5405 reg = <0x17cd0000 0x1000>;
5412 reg = <0x17ce0000 0x1000>;
5419 reg = <0x17cf0000 0x1000>;
5426 reg = <0x17d00000 0x1000>;
5433 reg = <0x17d10000 0x1000>;
5440 reg = <0 0x17d41000 0 0x1400>;
5450 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5453 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5465 reg = <0 0x18800000 0 0x800000>;
5483 iommus = <&apps_smmu 0x0040 0x1>;
5702 thermal-sensors = <&tsens0 0>;
5820 thermal-sensors = <&tsens1 0>;
5935 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;