Lines Matching +full:domain +full:- +full:idle +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 interrupt-parent = <&intc>;
25 #address-cells = <2>;
26 #size-cells = <2>;
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32764>;
39 xo_board: xo-board {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <38400000>;
47 #address-cells = <2>;
48 #size-cells = <0>;
54 enable-method = "psci";
55 capacity-dmips-mhz = <610>;
56 dynamic-power-coefficient = <203>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
58 operating-points-v2 = <&cpu0_opp_table>;
61 power-domains = <&cpu_pd0>;
62 power-domain-names = "psci";
63 next-level-cache = <&l2_0>;
64 l2_0: l2-cache {
66 next-level-cache = <&l3_0>;
67 cache-level = <2>;
68 cache-unified;
69 l3_0: l3-cache {
71 cache-level = <3>;
72 cache-unified;
81 enable-method = "psci";
82 capacity-dmips-mhz = <610>;
83 dynamic-power-coefficient = <203>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
85 operating-points-v2 = <&cpu0_opp_table>;
88 power-domains = <&cpu_pd1>;
89 power-domain-names = "psci";
90 next-level-cache = <&l2_100>;
91 l2_100: l2-cache {
93 cache-level = <2>;
94 cache-unified;
95 next-level-cache = <&l3_0>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <610>;
105 dynamic-power-coefficient = <203>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 operating-points-v2 = <&cpu0_opp_table>;
110 power-domains = <&cpu_pd2>;
111 power-domain-names = "psci";
112 next-level-cache = <&l2_200>;
113 l2_200: l2-cache {
115 cache-level = <2>;
116 cache-unified;
117 next-level-cache = <&l3_0>;
125 enable-method = "psci";
126 capacity-dmips-mhz = <610>;
127 dynamic-power-coefficient = <203>;
128 qcom,freq-domain = <&cpufreq_hw 0>;
129 operating-points-v2 = <&cpu0_opp_table>;
132 power-domains = <&cpu_pd3>;
133 power-domain-names = "psci";
134 next-level-cache = <&l2_300>;
135 l2_300: l2-cache {
137 cache-level = <2>;
138 cache-unified;
139 next-level-cache = <&l3_0>;
147 enable-method = "psci";
148 capacity-dmips-mhz = <610>;
149 dynamic-power-coefficient = <203>;
150 qcom,freq-domain = <&cpufreq_hw 0>;
151 operating-points-v2 = <&cpu0_opp_table>;
154 power-domains = <&cpu_pd4>;
155 power-domain-names = "psci";
156 next-level-cache = <&l2_400>;
157 l2_400: l2-cache {
159 cache-level = <2>;
160 cache-unified;
161 next-level-cache = <&l3_0>;
169 enable-method = "psci";
170 capacity-dmips-mhz = <610>;
171 dynamic-power-coefficient = <203>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
173 operating-points-v2 = <&cpu0_opp_table>;
176 power-domains = <&cpu_pd5>;
177 power-domain-names = "psci";
178 next-level-cache = <&l2_500>;
179 l2_500: l2-cache {
181 cache-level = <2>;
182 cache-unified;
183 next-level-cache = <&l3_0>;
191 enable-method = "psci";
192 capacity-dmips-mhz = <1024>;
193 dynamic-power-coefficient = <393>;
194 qcom,freq-domain = <&cpufreq_hw 1>;
195 operating-points-v2 = <&cpu6_opp_table>;
198 power-domains = <&cpu_pd6>;
199 power-domain-names = "psci";
200 next-level-cache = <&l2_600>;
201 l2_600: l2-cache {
203 cache-level = <2>;
204 cache-unified;
205 next-level-cache = <&l3_0>;
213 enable-method = "psci";
214 capacity-dmips-mhz = <1024>;
215 dynamic-power-coefficient = <393>;
216 qcom,freq-domain = <&cpufreq_hw 1>;
217 operating-points-v2 = <&cpu6_opp_table>;
220 power-domains = <&cpu_pd7>;
221 power-domain-names = "psci";
222 next-level-cache = <&l2_700>;
223 l2_700: l2-cache {
225 cache-level = <2>;
226 cache-unified;
227 next-level-cache = <&l3_0>;
231 cpu-map {
267 idle-states {
268 entry-method = "psci";
270 little_cpu_sleep_0: cpu-sleep-0-0 {
271 compatible = "arm,idle-state";
272 idle-state-name = "little-rail-power-collapse";
273 arm,psci-suspend-param = <0x40000004>;
274 entry-latency-us = <702>;
275 exit-latency-us = <915>;
276 min-residency-us = <1617>;
277 local-timer-stop;
280 big_cpu_sleep_0: cpu-sleep-1-0 {
281 compatible = "arm,idle-state";
282 idle-state-name = "big-rail-power-collapse";
283 arm,psci-suspend-param = <0x40000004>;
284 entry-latency-us = <526>;
285 exit-latency-us = <1854>;
286 min-residency-us = <2380>;
287 local-timer-stop;
291 domain-idle-states {
292 cluster_sleep_0: cluster-sleep-0 {
293 compatible = "domain-idle-state";
294 arm,psci-suspend-param = <0x4100c244>;
295 entry-latency-us = <3263>;
296 exit-latency-us = <6562>;
297 min-residency-us = <9825>;
304 compatible = "qcom,scm-sdm670", "qcom,scm";
314 cpu0_opp_table: opp-table-cpu0 {
315 compatible = "operating-points-v2";
316 opp-shared;
318 cpu0_opp1: opp-300000000 {
319 opp-hz = /bits/ 64 <300000000>;
320 opp-peak-kBps = <400000 4800000>;
323 cpu0_opp2: opp-576000000 {
324 opp-hz = /bits/ 64 <576000000>;
325 opp-peak-kBps = <400000 4800000>;
328 cpu0_opp3: opp-748800000 {
329 opp-hz = /bits/ 64 <748800000>;
330 opp-peak-kBps = <1200000 4800000>;
333 cpu0_opp4: opp-998400000 {
334 opp-hz = /bits/ 64 <998400000>;
335 opp-peak-kBps = <1804000 8908800>;
338 cpu0_opp5: opp-1209600000 {
339 opp-hz = /bits/ 64 <1209600000>;
340 opp-peak-kBps = <2188000 8908800>;
343 cpu0_opp6: opp-1324800000 {
344 opp-hz = /bits/ 64 <1324800000>;
345 opp-peak-kBps = <2188000 13516800>;
348 cpu0_opp7: opp-1516800000 {
349 opp-hz = /bits/ 64 <1516800000>;
350 opp-peak-kBps = <3072000 15052800>;
353 cpu0_opp8: opp-1612800000 {
354 opp-hz = /bits/ 64 <1612800000>;
355 opp-peak-kBps = <3072000 22118400>;
358 cpu0_opp9: opp-1708800000 {
359 opp-hz = /bits/ 64 <1708800000>;
360 opp-peak-kBps = <4068000 23040000>;
364 cpu6_opp_table: opp-table-cpu6 {
365 compatible = "operating-points-v2";
366 opp-shared;
368 cpu6_opp1: opp-300000000 {
369 opp-hz = /bits/ 64 <300000000>;
370 opp-peak-kBps = <400000 4800000>;
373 cpu6_opp2: opp-652800000 {
374 opp-hz = /bits/ 64 <652800000>;
375 opp-peak-kBps = <400000 4800000>;
378 cpu6_opp3: opp-825600000 {
379 opp-hz = /bits/ 64 <825600000>;
380 opp-peak-kBps = <1200000 4800000>;
383 cpu6_opp4: opp-979200000 {
384 opp-hz = /bits/ 64 <979200000>;
385 opp-peak-kBps = <1200000 4800000>;
388 cpu6_opp5: opp-1132800000 {
389 opp-hz = /bits/ 64 <1132800000>;
390 opp-peak-kBps = <2188000 8908800>;
393 cpu6_opp6: opp-1363200000 {
394 opp-hz = /bits/ 64 <1363200000>;
395 opp-peak-kBps = <4068000 12902400>;
398 cpu6_opp7: opp-1536000000 {
399 opp-hz = /bits/ 64 <1536000000>;
400 opp-peak-kBps = <4068000 12902400>;
403 cpu6_opp8: opp-1747200000 {
404 opp-hz = /bits/ 64 <1747200000>;
405 opp-peak-kBps = <4068000 15052800>;
408 cpu6_opp9: opp-1843200000 {
409 opp-hz = /bits/ 64 <1843200000>;
410 opp-peak-kBps = <4068000 15052800>;
413 cpu6_opp10: opp-1996800000 {
414 opp-hz = /bits/ 64 <1996800000>;
415 opp-peak-kBps = <6220000 19046400>;
419 dsi_opp_table: opp-table-dsi {
420 compatible = "operating-points-v2";
422 opp-19200000 {
423 opp-hz = /bits/ 64 <19200000>;
424 required-opps = <&rpmhpd_opp_min_svs>;
427 opp-180000000 {
428 opp-hz = /bits/ 64 <180000000>;
429 required-opps = <&rpmhpd_opp_low_svs>;
432 opp-275000000 {
433 opp-hz = /bits/ 64 <275000000>;
434 required-opps = <&rpmhpd_opp_svs>;
437 opp-358000000 {
438 opp-hz = /bits/ 64 <358000000>;
439 required-opps = <&rpmhpd_opp_svs_l1>;
444 compatible = "arm,psci-1.0";
447 cpu_pd0: power-domain-cpu0 {
448 #power-domain-cells = <0>;
449 power-domains = <&cluster_pd>;
450 domain-idle-states = <&little_cpu_sleep_0>;
453 cpu_pd1: power-domain-cpu1 {
454 #power-domain-cells = <0>;
455 power-domains = <&cluster_pd>;
456 domain-idle-states = <&little_cpu_sleep_0>;
459 cpu_pd2: power-domain-cpu2 {
460 #power-domain-cells = <0>;
461 power-domains = <&cluster_pd>;
462 domain-idle-states = <&little_cpu_sleep_0>;
465 cpu_pd3: power-domain-cpu3 {
466 #power-domain-cells = <0>;
467 power-domains = <&cluster_pd>;
468 domain-idle-states = <&little_cpu_sleep_0>;
471 cpu_pd4: power-domain-cpu4 {
472 #power-domain-cells = <0>;
473 power-domains = <&cluster_pd>;
474 domain-idle-states = <&little_cpu_sleep_0>;
477 cpu_pd5: power-domain-cpu5 {
478 #power-domain-cells = <0>;
479 power-domains = <&cluster_pd>;
480 domain-idle-states = <&little_cpu_sleep_0>;
483 cpu_pd6: power-domain-cpu6 {
484 #power-domain-cells = <0>;
485 power-domains = <&cluster_pd>;
486 domain-idle-states = <&big_cpu_sleep_0>;
489 cpu_pd7: power-domain-cpu7 {
490 #power-domain-cells = <0>;
491 power-domains = <&cluster_pd>;
492 domain-idle-states = <&big_cpu_sleep_0>;
495 cluster_pd: power-domain-cluster {
496 #power-domain-cells = <0>;
497 domain-idle-states = <&cluster_sleep_0>;
501 reserved-memory {
502 #address-cells = <2>;
503 #size-cells = <2>;
506 hyp_mem: hyp-mem@85700000 {
508 no-map;
511 xbl_mem: xbl-mem@85e00000 {
513 no-map;
516 aop_mem: aop-mem@85fc0000 {
518 no-map;
521 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
522 compatible = "qcom,cmd-db";
524 no-map;
530 no-map;
536 no-map;
539 camera_mem: camera-mem@8ab00000 {
541 no-map;
546 no-map;
551 no-map;
554 wlan_msa_mem: wlan-msa@93300000 {
556 no-map;
561 no-map;
566 no-map;
571 no-map;
574 ipa_fw_mem: ipa-fw@95c00000 {
576 no-map;
579 ipa_gsi_mem: ipa-gsi@95c10000 {
581 no-map;
586 no-map;
591 no-map;
596 no-map;
601 compatible = "arm,armv8-timer";
609 #address-cells = <2>;
610 #size-cells = <2>;
612 dma-ranges = <0 0 0 0 0x10 0>;
613 compatible = "simple-bus";
615 gcc: clock-controller@100000 {
616 compatible = "qcom,gcc-sdm670";
621 clock-names = "bi_tcxo",
624 #clock-cells = <1>;
625 #reset-cells = <1>;
626 #power-domain-cells = <1>;
630 compatible = "qcom,sdm670-qfprom", "qcom,qfprom";
632 #address-cells = <1>;
633 #size-cells = <1>;
640 qusb2_hstx_trim: hstx-trim@1eb {
647 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
651 reg-names = "hc", "cqhci", "ice";
655 interrupt-names = "hc_irq", "pwr_irq";
662 clock-names = "iface", "core", "xo", "ice", "bus";
665 interconnect-names = "sdhc-ddr", "cpu-sdhc";
666 operating-points-v2 = <&sdhc1_opp_table>;
670 pinctrl-names = "default", "sleep";
671 pinctrl-0 = <&sdc1_state_on>;
672 pinctrl-1 = <&sdc1_state_off>;
673 power-domains = <&rpmhpd SDM670_CX>;
675 bus-width = <8>;
676 non-removable;
680 sdhc1_opp_table: opp-table {
681 compatible = "operating-points-v2";
683 opp-20000000 {
684 opp-hz = /bits/ 64 <20000000>;
685 required-opps = <&rpmhpd_opp_min_svs>;
686 opp-peak-kBps = <80000 80000>;
687 opp-avg-kBps = <52286 80000>;
690 opp-50000000 {
691 opp-hz = /bits/ 64 <50000000>;
692 required-opps = <&rpmhpd_opp_low_svs>;
693 opp-peak-kBps = <200000 100000>;
694 opp-avg-kBps = <130718 100000>;
697 opp-100000000 {
698 opp-hz = /bits/ 64 <100000000>;
699 required-opps = <&rpmhpd_opp_svs>;
700 opp-peak-kBps = <200000 130000>;
701 opp-avg-kBps = <130718 130000>;
704 opp-384000000 {
705 opp-hz = /bits/ 64 <384000000>;
706 required-opps = <&rpmhpd_opp_nom>;
707 opp-peak-kBps = <4096000 4096000>;
708 opp-avg-kBps = <1338562 1338562>;
713 gpi_dma0: dma-controller@800000 {
714 #dma-cells = <3>;
715 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
730 dma-channels = <13>;
731 dma-channel-mask = <0xfa>;
737 compatible = "qcom,geni-se-qup";
739 clock-names = "m-ahb", "s-ahb";
743 #address-cells = <2>;
744 #size-cells = <2>;
747 interconnect-names = "qup-core";
751 compatible = "qcom,geni-i2c";
753 clock-names = "se";
755 pinctrl-names = "default";
756 pinctrl-0 = <&qup_i2c0_default>;
758 #address-cells = <1>;
759 #size-cells = <0>;
760 power-domains = <&rpmhpd SDM670_CX>;
764 interconnect-names = "qup-core", "qup-config", "qup-memory";
767 dma-names = "tx", "rx";
772 compatible = "qcom,geni-i2c";
774 clock-names = "se";
776 pinctrl-names = "default";
777 pinctrl-0 = <&qup_i2c1_default>;
779 #address-cells = <1>;
780 #size-cells = <0>;
781 power-domains = <&rpmhpd SDM670_CX>;
785 interconnect-names = "qup-core", "qup-config", "qup-memory";
788 dma-names = "tx", "rx";
793 compatible = "qcom,geni-i2c";
795 clock-names = "se";
797 pinctrl-names = "default";
798 pinctrl-0 = <&qup_i2c2_default>;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 power-domains = <&rpmhpd SDM670_CX>;
806 interconnect-names = "qup-core", "qup-config", "qup-memory";
809 dma-names = "tx", "rx";
814 compatible = "qcom,geni-i2c";
816 clock-names = "se";
818 pinctrl-names = "default";
819 pinctrl-0 = <&qup_i2c3_default>;
821 #address-cells = <1>;
822 #size-cells = <0>;
823 power-domains = <&rpmhpd SDM670_CX>;
827 interconnect-names = "qup-core", "qup-config", "qup-memory";
830 dma-names = "tx", "rx";
835 compatible = "qcom,geni-i2c";
837 clock-names = "se";
839 pinctrl-names = "default";
840 pinctrl-0 = <&qup_i2c4_default>;
842 #address-cells = <1>;
843 #size-cells = <0>;
844 power-domains = <&rpmhpd SDM670_CX>;
848 interconnect-names = "qup-core", "qup-config", "qup-memory";
851 dma-names = "tx", "rx";
856 compatible = "qcom,geni-i2c";
858 clock-names = "se";
860 pinctrl-names = "default";
861 pinctrl-0 = <&qup_i2c5_default>;
863 #address-cells = <1>;
864 #size-cells = <0>;
865 power-domains = <&rpmhpd SDM670_CX>;
869 interconnect-names = "qup-core", "qup-config", "qup-memory";
872 dma-names = "tx", "rx";
877 compatible = "qcom,geni-i2c";
879 clock-names = "se";
881 pinctrl-names = "default";
882 pinctrl-0 = <&qup_i2c6_default>;
884 #address-cells = <1>;
885 #size-cells = <0>;
886 power-domains = <&rpmhpd SDM670_CX>;
890 interconnect-names = "qup-core", "qup-config", "qup-memory";
893 dma-names = "tx", "rx";
898 compatible = "qcom,geni-i2c";
900 clock-names = "se";
902 pinctrl-names = "default";
903 pinctrl-0 = <&qup_i2c7_default>;
905 #address-cells = <1>;
906 #size-cells = <0>;
907 power-domains = <&rpmhpd SDM670_CX>;
911 interconnect-names = "qup-core", "qup-config", "qup-memory";
914 dma-names = "tx", "rx";
919 gpi_dma1: dma-controller@a00000 {
920 #dma-cells = <3>;
921 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
936 dma-channels = <13>;
937 dma-channel-mask = <0xfa>;
943 compatible = "qcom,geni-se-qup";
945 clock-names = "m-ahb", "s-ahb";
949 #address-cells = <2>;
950 #size-cells = <2>;
953 interconnect-names = "qup-core";
957 compatible = "qcom,geni-i2c";
959 clock-names = "se";
961 pinctrl-names = "default";
962 pinctrl-0 = <&qup_i2c8_default>;
964 #address-cells = <1>;
965 #size-cells = <0>;
966 power-domains = <&rpmhpd SDM670_CX>;
970 interconnect-names = "qup-core", "qup-config", "qup-memory";
973 dma-names = "tx", "rx";
978 compatible = "qcom,geni-i2c";
980 clock-names = "se";
982 pinctrl-names = "default";
983 pinctrl-0 = <&qup_i2c9_default>;
985 #address-cells = <1>;
986 #size-cells = <0>;
987 power-domains = <&rpmhpd SDM670_CX>;
991 interconnect-names = "qup-core", "qup-config", "qup-memory";
994 dma-names = "tx", "rx";
999 compatible = "qcom,geni-i2c";
1001 clock-names = "se";
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&qup_i2c10_default>;
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1008 power-domains = <&rpmhpd SDM670_CX>;
1012 interconnect-names = "qup-core", "qup-config", "qup-memory";
1015 dma-names = "tx", "rx";
1020 compatible = "qcom,geni-i2c";
1022 clock-names = "se";
1024 pinctrl-names = "default";
1025 pinctrl-0 = <&qup_i2c11_default>;
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1029 power-domains = <&rpmhpd SDM670_CX>;
1033 interconnect-names = "qup-core", "qup-config", "qup-memory";
1036 dma-names = "tx", "rx";
1041 compatible = "qcom,geni-i2c";
1043 clock-names = "se";
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_i2c12_default>;
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1050 power-domains = <&rpmhpd SDM670_CX>;
1054 interconnect-names = "qup-core", "qup-config", "qup-memory";
1057 dma-names = "tx", "rx";
1062 compatible = "qcom,geni-i2c";
1064 clock-names = "se";
1066 pinctrl-names = "default";
1067 pinctrl-0 = <&qup_i2c13_default>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 power-domains = <&rpmhpd SDM670_CX>;
1075 interconnect-names = "qup-core", "qup-config", "qup-memory";
1078 dma-names = "tx", "rx";
1083 compatible = "qcom,geni-i2c";
1085 clock-names = "se";
1087 pinctrl-names = "default";
1088 pinctrl-0 = <&qup_i2c14_default>;
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1092 power-domains = <&rpmhpd SDM670_CX>;
1096 interconnect-names = "qup-core", "qup-config", "qup-memory";
1099 dma-names = "tx", "rx";
1104 compatible = "qcom,geni-i2c";
1106 clock-names = "se";
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&qup_i2c15_default>;
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1113 power-domains = <&rpmhpd SDM670_CX>;
1117 interconnect-names = "qup-core", "qup-config", "qup-memory";
1120 dma-names = "tx", "rx";
1126 compatible = "qcom,sdm670-mem-noc";
1128 #interconnect-cells = <2>;
1129 qcom,bcm-voters = <&apps_bcm_voter>;
1133 compatible = "qcom,sdm670-dc-noc";
1135 #interconnect-cells = <2>;
1136 qcom,bcm-voters = <&apps_bcm_voter>;
1140 compatible = "qcom,sdm670-config-noc";
1142 #interconnect-cells = <2>;
1143 qcom,bcm-voters = <&apps_bcm_voter>;
1147 compatible = "qcom,sdm670-system-noc";
1149 #interconnect-cells = <2>;
1150 qcom,bcm-voters = <&apps_bcm_voter>;
1154 compatible = "qcom,sdm670-aggre1-noc";
1156 #interconnect-cells = <2>;
1157 qcom,bcm-voters = <&apps_bcm_voter>;
1161 compatible = "qcom,sdm670-aggre2-noc";
1163 #interconnect-cells = <2>;
1164 qcom,bcm-voters = <&apps_bcm_voter>;
1168 compatible = "qcom,sdm670-mmss-noc";
1170 #interconnect-cells = <2>;
1171 qcom,bcm-voters = <&apps_bcm_voter>;
1175 compatible = "qcom,tcsr-mutex";
1177 #hwlock-cells = <1>;
1181 compatible = "qcom,sdm670-tlmm";
1184 gpio-controller;
1185 #gpio-cells = <2>;
1186 interrupt-controller;
1187 #interrupt-cells = <2>;
1188 gpio-ranges = <&tlmm 0 0 151>;
1189 wakeup-parent = <&pdc>;
1191 qup_i2c0_default: qup-i2c0-default-state {
1196 qup_i2c1_default: qup-i2c1-default-state {
1201 qup_i2c2_default: qup-i2c2-default-state {
1206 qup_i2c3_default: qup-i2c3-default-state {
1211 qup_i2c4_default: qup-i2c4-default-state {
1216 qup_i2c5_default: qup-i2c5-default-state {
1221 qup_i2c6_default: qup-i2c6-default-state {
1226 qup_i2c7_default: qup-i2c7-default-state {
1231 qup_i2c8_default: qup-i2c8-default-state {
1236 qup_i2c9_default: qup-i2c9-default-state {
1241 qup_i2c10_default: qup-i2c10-default-state {
1246 qup_i2c11_default: qup-i2c11-default-state {
1251 qup_i2c12_default: qup-i2c12-default-state {
1256 qup_i2c13_default: qup-i2c13-default-state {
1261 qup_i2c14_default: qup-i2c14-default-state {
1266 qup_i2c15_default: qup-i2c15-default-state {
1271 sdc1_state_on: sdc1-on-state {
1272 clk-pins {
1274 bias-disable;
1275 drive-strength = <16>;
1278 cmd-pins {
1280 bias-pull-up;
1281 drive-strength = <10>;
1284 data-pins {
1286 bias-pull-up;
1287 drive-strength = <10>;
1290 rclk-pins {
1292 bias-pull-down;
1296 sdc1_state_off: sdc1-off-state {
1297 clk-pins {
1299 bias-disable;
1300 drive-strength = <2>;
1303 cmd-pins {
1305 bias-pull-up;
1306 drive-strength = <2>;
1309 data-pins {
1311 bias-pull-up;
1312 drive-strength = <2>;
1315 rclk-pins {
1317 bias-pull-down;
1323 compatible = "qcom,adreno-615.0", "qcom,adreno";
1326 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
1337 operating-points-v2 = <&gpu_opp_table>;
1342 interconnect-names = "gfx-mem";
1344 nvmem-cells = <&gpu_speed_bin>;
1345 nvmem-cell-names = "speed_bin";
1349 gpu_opp_table: opp-table {
1350 compatible = "operating-points-v2";
1352 opp-780000000 {
1353 opp-hz = /bits/ 64 <780000000>;
1354 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1355 opp-peak-kBps = <7216000>;
1356 opp-supported-hw = <0x8>;
1359 opp-750000000 {
1360 opp-hz = /bits/ 64 <750000000>;
1361 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1362 opp-peak-kBps = <7216000>;
1363 opp-supported-hw = <0x8>;
1366 opp-700000000 {
1367 opp-hz = /bits/ 64 <700000000>;
1368 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1369 opp-peak-kBps = <7216000>;
1370 opp-supported-hw = <0x4>;
1373 opp-650000000 {
1374 opp-hz = /bits/ 64 <650000000>;
1375 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1376 opp-peak-kBps = <7216000>;
1377 opp-supported-hw = <0xc>;
1380 opp-565000000 {
1381 opp-hz = /bits/ 64 <565000000>;
1382 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1383 opp-peak-kBps = <7216000>;
1384 opp-supported-hw = <0xc>;
1387 opp-504000000 {
1388 opp-hz = /bits/ 64 <504000000>;
1389 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1390 opp-peak-kBps = <7216000>;
1391 opp-supported-hw = <0x2>;
1394 opp-430000000 {
1395 opp-hz = /bits/ 64 <430000000>;
1396 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1397 opp-peak-kBps = <7216000>;
1398 opp-supported-hw = <0xf>;
1401 opp-355000000 {
1402 opp-hz = /bits/ 64 <355000000>;
1403 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1404 opp-peak-kBps = <6220000>;
1405 opp-supported-hw = <0xf>;
1408 opp-267000000 {
1409 opp-hz = /bits/ 64 <267000000>;
1410 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1411 opp-peak-kBps = <4068000>;
1412 opp-supported-hw = <0xf>;
1415 opp-180000000 {
1416 opp-hz = /bits/ 64 <180000000>;
1417 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1418 opp-peak-kBps = <1804000>;
1419 opp-supported-hw = <0xf>;
1425 compatible = "qcom,sdm670-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1427 #iommu-cells = <1>;
1428 #global-interrupts = <2>;
1441 clock-names = "bus", "iface";
1443 power-domains = <&gpucc GPU_CX_GDSC>;
1447 compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu";
1452 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1456 interrupt-names = "hfi", "gmu";
1462 clock-names = "gmu", "cxo", "axi", "memnoc";
1464 power-domains = <&gpucc GPU_CX_GDSC>,
1466 power-domain-names = "cx", "gx";
1470 operating-points-v2 = <&gmu_opp_table>;
1472 gmu_opp_table: opp-table {
1473 compatible = "operating-points-v2";
1475 opp-200000000 {
1476 opp-hz = /bits/ 64 <200000000>;
1477 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1482 gpucc: clock-controller@5090000 {
1483 compatible = "qcom,sdm845-gpucc";
1485 #clock-cells = <1>;
1486 #reset-cells = <1>;
1487 #power-domain-cells = <1>;
1491 clock-names = "bi_tcxo",
1497 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
1499 #phy-cells = <0>;
1503 clock-names = "cfg_ahb", "ref";
1507 nvmem-cells = <&qusb2_hstx_trim>;
1513 compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
1515 #address-cells = <2>;
1516 #size-cells = <2>;
1518 dma-ranges;
1525 clock-names = "cfg_noc",
1531 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1533 assigned-clock-rates = <19200000>, <150000000>;
1535 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1540 interrupt-names = "pwr_event",
1546 power-domains = <&gcc USB30_PRIM_GDSC>;
1552 interconnect-names = "usb-ddr", "apps-usb";
1564 phy-names = "usb2-phy";
1568 pdc: interrupt-controller@b220000 {
1569 compatible = "qcom,sdm670-pdc", "qcom,pdc";
1571 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1574 #interrupt-cells = <2>;
1575 interrupt-parent = <&intc>;
1576 interrupt-controller;
1580 compatible = "qcom,spmi-pmic-arb";
1586 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1587 interrupt-names = "periph_irq";
1591 #address-cells = <2>;
1592 #size-cells = <0>;
1593 interrupt-controller;
1594 #interrupt-cells = <4>;
1597 camcc: clock-controller@ad00000 {
1598 compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc";
1601 clock-names = "bi_tcxo";
1602 #clock-cells = <1>;
1603 #reset-cells = <1>;
1604 #power-domain-cells = <1>;
1607 mdss: display-subsystem@ae00000 {
1608 compatible = "qcom,sdm670-mdss";
1610 reg-names = "mdss";
1612 power-domains = <&dispcc MDSS_GDSC>;
1616 clock-names = "iface", "core";
1619 interrupt-controller;
1620 #interrupt-cells = <1>;
1624 interconnect-names = "mdp0-mem", "mdp1-mem";
1629 #address-cells = <2>;
1630 #size-cells = <2>;
1635 mdss_mdp: display-controller@ae01000 {
1636 compatible = "qcom,sdm670-dpu";
1639 reg-names = "mdp", "vbif";
1646 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
1648 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1649 assigned-clock-rates = <19200000>;
1650 operating-points-v2 = <&mdp_opp_table>;
1651 power-domains = <&rpmhpd SDM670_CX>;
1653 interrupt-parent = <&mdss>;
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1663 remote-endpoint = <&mdss_dsi0_in>;
1670 remote-endpoint = <&mdss_dsi1_in>;
1675 mdp_opp_table: opp-table {
1676 compatible = "operating-points-v2";
1678 opp-19200000 {
1679 opp-hz = /bits/ 64 <19200000>;
1680 required-opps = <&rpmhpd_opp_min_svs>;
1683 opp-171428571 {
1684 opp-hz = /bits/ 64 <171428571>;
1685 required-opps = <&rpmhpd_opp_low_svs>;
1688 opp-358000000 {
1689 opp-hz = /bits/ 64 <358000000>;
1690 required-opps = <&rpmhpd_opp_svs_l1>;
1693 opp-430000000 {
1694 opp-hz = /bits/ 64 <430000000>;
1695 required-opps = <&rpmhpd_opp_nom>;
1701 compatible = "qcom,sdm670-dsi-ctrl",
1702 "qcom,mdss-dsi-ctrl";
1704 reg-names = "dsi_ctrl";
1706 interrupt-parent = <&mdss>;
1715 clock-names = "byte",
1721 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1723 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1726 operating-points-v2 = <&dsi_opp_table>;
1727 power-domains = <&rpmhpd SDM670_CX>;
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1737 #address-cells = <1>;
1738 #size-cells = <0>;
1743 remote-endpoint = <&dpu_intf0_out>;
1756 compatible = "qcom,dsi-phy-10nm";
1760 reg-names = "dsi_phy",
1764 #clock-cells = <1>;
1765 #phy-cells = <0>;
1769 clock-names = "iface", "ref";
1775 compatible = "qcom,sdm670-dsi-ctrl",
1776 "qcom,mdss-dsi-ctrl";
1778 reg-names = "dsi_ctrl";
1780 interrupt-parent = <&mdss>;
1789 clock-names = "byte",
1795 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
1797 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1799 operating-points-v2 = <&dsi_opp_table>;
1800 power-domains = <&rpmhpd SDM670_CX>;
1804 #address-cells = <1>;
1805 #size-cells = <0>;
1810 #address-cells = <1>;
1811 #size-cells = <0>;
1816 remote-endpoint = <&dpu_intf1_out>;
1829 compatible = "qcom,dsi-phy-10nm";
1833 reg-names = "dsi_phy",
1837 #clock-cells = <1>;
1838 #phy-cells = <0>;
1842 clock-names = "iface", "ref";
1848 dispcc: clock-controller@af00000 {
1849 compatible = "qcom,sdm845-dispcc";
1860 clock-names = "bi_tcxo",
1869 #clock-cells = <1>;
1870 #reset-cells = <1>;
1871 #power-domain-cells = <1>;
1875 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1877 #iommu-cells = <2>;
1878 #global-interrupts = <1>;
1944 dma-coherent;
1948 compatible = "qcom,sdm670-gladiator-noc";
1950 #interconnect-cells = <2>;
1951 qcom,bcm-voters = <&apps_bcm_voter>;
1955 compatible = "qcom,rpmh-rsc";
1959 reg-names = "drv-0", "drv-1", "drv-2";
1964 qcom,tcs-offset = <0xd00>;
1965 qcom,drv-id = <2>;
1966 qcom,tcs-config = <ACTIVE_TCS 2>,
1970 power-domains = <&cluster_pd>;
1972 apps_bcm_voter: bcm-voter {
1973 compatible = "qcom,bcm-voter";
1976 rpmhcc: clock-controller {
1977 compatible = "qcom,sdm670-rpmh-clk";
1978 #clock-cells = <1>;
1979 clock-names = "xo";
1983 rpmhpd: power-controller {
1984 compatible = "qcom,sdm670-rpmhpd";
1985 #power-domain-cells = <1>;
1986 operating-points-v2 = <&rpmhpd_opp_table>;
1988 rpmhpd_opp_table: opp-table {
1989 compatible = "operating-points-v2";
1992 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1996 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2000 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2004 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2008 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2012 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2016 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2020 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2024 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2028 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2034 intc: interrupt-controller@17a00000 {
2035 compatible = "arm,gic-v3";
2038 interrupt-controller;
2040 #interrupt-cells = <3>;
2044 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
2048 clock-names = "xo", "alternate";
2050 #interconnect-cells = <1>;
2054 compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw";
2056 reg-names = "freq-domain0", "freq-domain1";
2059 clock-names = "xo", "alternate";
2061 #freq-domain-cells = <1>;