Lines Matching +full:0 +full:x0c40a000
35 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0 0x0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
124 reg = <0x0 0x300>;
128 qcom,freq-domain = <&cpufreq_hw 0>;
146 reg = <0x0 0x400>;
150 qcom,freq-domain = <&cpufreq_hw 0>;
168 reg = <0x0 0x500>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
190 reg = <0x0 0x600>;
212 reg = <0x0 0x700>;
270 little_cpu_sleep_0: cpu-sleep-0-0 {
273 arm,psci-suspend-param = <0x40000004>;
280 big_cpu_sleep_0: cpu-sleep-1-0 {
283 arm,psci-suspend-param = <0x40000004>;
292 cluster_sleep_0: cluster-sleep-0 {
294 arm,psci-suspend-param = <0x4100c244>;
311 reg = <0x0 0x80000000 0x0 0x0>;
448 #power-domain-cells = <0>;
454 #power-domain-cells = <0>;
460 #power-domain-cells = <0>;
466 #power-domain-cells = <0>;
472 #power-domain-cells = <0>;
478 #power-domain-cells = <0>;
484 #power-domain-cells = <0>;
490 #power-domain-cells = <0>;
496 #power-domain-cells = <0>;
507 reg = <0 0x85700000 0 0x600000>;
512 reg = <0 0x85e00000 0 0x100000>;
517 reg = <0 0x85fc0000 0 0x20000>;
523 reg = <0 0x85fe0000 0 0x20000>;
529 reg = <0 0x86000000 0 0x200000>;
535 reg = <0 0x86200000 0 0x2d00000>;
540 reg = <0 0x8ab00000 0 0x500000>;
545 reg = <0 0x8b000000 0 0x7e00000>;
550 reg = <0 0x92e00000 0 0x500000>;
555 reg = <0 0x93300000 0 0x100000>;
560 reg = <0 0x93400000 0 0x800000>;
565 reg = <0 0x93c00000 0 0x200000>;
570 reg = <0 0x93e00000 0 0x1e00000>;
575 reg = <0 0x95c00000 0 0x10000>;
580 reg = <0 0x95c10000 0 0x5000>;
585 reg = <0 0x95c15000 0 0x2000>;
590 reg = <0 0x97b00000 0 0x100000>;
595 reg = <0 0x9e400000 0 0x1400000>;
605 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
608 soc: soc@0 {
611 ranges = <0 0 0 0 0x10 0>;
612 dma-ranges = <0 0 0 0 0x10 0>;
617 reg = <0 0x00100000 0 0x1f0000>;
631 reg = <0 0x00784000 0 0x1000>;
636 reg = <0x1a2 0x2>;
641 reg = <0x1eb 0x1>;
648 reg = <0 0x007c4000 0 0x1000>,
649 <0 0x007c5000 0 0x1000>,
650 <0 0x007c8000 0 0x8000>;
663 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>,
664 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>;
668 iommus = <&apps_smmu 0x140 0xf>;
671 pinctrl-0 = <&sdc1_state_on>;
716 reg = <0 0x00800000 0 0x60000>;
731 dma-channel-mask = <0xfa>;
732 iommus = <&apps_smmu 0x16 0x0>;
738 reg = <0 0x008c0000 0 0x6000>;
742 iommus = <&apps_smmu 0x3 0x0>;
746 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>;
752 reg = <0 0x00880000 0 0x4000>;
756 pinctrl-0 = <&qup_i2c0_default>;
759 #size-cells = <0>;
761 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
762 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
763 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
765 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
766 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
773 reg = <0 0x00884000 0 0x4000>;
777 pinctrl-0 = <&qup_i2c1_default>;
780 #size-cells = <0>;
782 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
783 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
784 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
786 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
794 reg = <0 0x00888000 0 0x4000>;
798 pinctrl-0 = <&qup_i2c2_default>;
801 #size-cells = <0>;
803 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
804 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
805 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
807 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
815 reg = <0 0x0088c000 0 0x4000>;
819 pinctrl-0 = <&qup_i2c3_default>;
822 #size-cells = <0>;
824 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
825 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
826 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
828 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
836 reg = <0 0x00890000 0 0x4000>;
840 pinctrl-0 = <&qup_i2c4_default>;
843 #size-cells = <0>;
845 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
846 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
847 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
849 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
857 reg = <0 0x00894000 0 0x4000>;
861 pinctrl-0 = <&qup_i2c5_default>;
864 #size-cells = <0>;
866 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
867 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
868 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
870 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
878 reg = <0 0x00898000 0 0x4000>;
882 pinctrl-0 = <&qup_i2c6_default>;
885 #size-cells = <0>;
887 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
888 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
889 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
891 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
899 reg = <0 0x0089c000 0 0x4000>;
903 pinctrl-0 = <&qup_i2c7_default>;
906 #size-cells = <0>;
908 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
909 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
910 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
912 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
922 reg = <0 0x00a00000 0 0x60000>;
937 dma-channel-mask = <0xfa>;
938 iommus = <&apps_smmu 0x6d6 0x0>;
944 reg = <0 0x00ac0000 0 0x6000>;
948 iommus = <&apps_smmu 0x6c3 0x0>;
952 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>;
958 reg = <0 0x00a80000 0 0x4000>;
962 pinctrl-0 = <&qup_i2c8_default>;
965 #size-cells = <0>;
967 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
968 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
969 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
971 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
972 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
979 reg = <0 0x00a84000 0 0x4000>;
983 pinctrl-0 = <&qup_i2c9_default>;
986 #size-cells = <0>;
988 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
989 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
990 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
992 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1000 reg = <0 0x00a88000 0 0x4000>;
1004 pinctrl-0 = <&qup_i2c10_default>;
1007 #size-cells = <0>;
1009 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1010 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1011 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1013 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1021 reg = <0 0x00a8c000 0 0x4000>;
1025 pinctrl-0 = <&qup_i2c11_default>;
1028 #size-cells = <0>;
1030 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1031 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1032 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1034 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1042 reg = <0 0x00a90000 0 0x4000>;
1046 pinctrl-0 = <&qup_i2c12_default>;
1049 #size-cells = <0>;
1051 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1052 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1053 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1055 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1063 reg = <0 0x00a94000 0 0x4000>;
1067 pinctrl-0 = <&qup_i2c13_default>;
1070 #size-cells = <0>;
1072 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1073 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1074 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1076 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1084 reg = <0 0x00a98000 0 0x4000>;
1088 pinctrl-0 = <&qup_i2c14_default>;
1091 #size-cells = <0>;
1093 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1094 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1095 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1097 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1105 reg = <0 0x00a9c000 0 0x4000>;
1109 pinctrl-0 = <&qup_i2c15_default>;
1112 #size-cells = <0>;
1114 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1115 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1116 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1118 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1127 reg = <0 0x01380000 0 0x27200>;
1134 reg = <0 0x014e0000 0 0x400>;
1141 reg = <0 0x01500000 0 0x5080>;
1148 reg = <0 0x01620000 0 0x18080>;
1155 reg = <0 0x016e0000 0 0x15080>;
1162 reg = <0 0x01700000 0 0x1f300>;
1169 reg = <0 0x01740000 0 0x1c100>;
1176 reg = <0 0x01f40000 0 0x20000>;
1182 reg = <0 0x03400000 0 0xc00000>;
1188 gpio-ranges = <&tlmm 0 0 151>;
1325 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>;
1335 iommus = <&adreno_smmu 0>;
1341 interconnects = <&mem_noc MASTER_GRAPHICS_3D 0 &mem_noc SLAVE_EBI_CH0 0>;
1356 opp-supported-hw = <0x8>;
1363 opp-supported-hw = <0x8>;
1370 opp-supported-hw = <0x4>;
1377 opp-supported-hw = <0xc>;
1384 opp-supported-hw = <0xc>;
1391 opp-supported-hw = <0x2>;
1398 opp-supported-hw = <0xf>;
1405 opp-supported-hw = <0xf>;
1412 opp-supported-hw = <0xf>;
1419 opp-supported-hw = <0xf>;
1426 reg = <0 0x05040000 0 0x10000>;
1449 reg = <0 0x0506a000 0 0x30000>,
1450 <0 0x0b280000 0 0x10000>,
1451 <0 0x0b480000 0 0x10000>;
1484 reg = <0 0x05090000 0 0x9000>;
1498 reg = <0 0x088e2000 0 0x400>;
1499 #phy-cells = <0>;
1514 reg = <0 0x0a6f8800 0 0x400>;
1550 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>,
1551 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1558 reg = <0 0x0a600000 0 0xcd00>;
1560 iommus = <&apps_smmu 0x740 0>;
1570 reg = <0 0x0b220000 0 0x30000>;
1571 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1581 reg = <0 0x0c440000 0 0x1100>,
1582 <0 0x0c600000 0 0x2000000>,
1583 <0 0x0e600000 0 0x100000>,
1584 <0 0x0e700000 0 0xa0000>,
1585 <0 0x0c40a000 0 0x26000>;
1589 qcom,ee = <0>;
1590 qcom,channel = <0>;
1592 #size-cells = <0>;
1599 reg = <0 0x0ad00000 0 0x10000>;
1609 reg = <0 0x0ae00000 0 0x1000>;
1622 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
1623 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
1626 iommus = <&apps_smmu 0x880 0x8>,
1627 <&apps_smmu 0xc80 0x8>;
1637 reg = <0 0x0ae01000 0 0x8f000>,
1638 <0 0x0aeb0000 0 0x2008>;
1654 interrupts = <0>;
1658 #size-cells = <0>;
1660 port@0 {
1661 reg = <0>;
1703 reg = <0 0x0ae94000 0 0x400>;
1723 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1732 #size-cells = <0>;
1738 #size-cells = <0>;
1740 port@0 {
1741 reg = <0>;
1757 reg = <0 0x0ae94400 0 0x200>,
1758 <0 0x0ae94600 0 0x280>,
1759 <0 0x0ae94a00 0 0x1e0>;
1765 #phy-cells = <0>;
1777 reg = <0 0x0ae96000 0 0x400>;
1797 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1805 #size-cells = <0>;
1811 #size-cells = <0>;
1813 port@0 {
1814 reg = <0>;
1830 reg = <0 0x0ae96400 0 0x200>,
1831 <0 0x0ae96600 0 0x280>,
1832 <0 0x0ae96a00 0 0x10e>;
1838 #phy-cells = <0>;
1850 reg = <0 0x0af00000 0 0x10000>;
1854 <&mdss_dsi0_phy 0>,
1856 <&mdss_dsi1_phy 0>,
1858 <0>,
1859 <0>;
1876 reg = <0 0x15000000 0 0x80000>;
1949 reg = <0 0x17900000 0 0xd080>;
1956 reg = <0 0x179c0000 0 0x10000>,
1957 <0 0x179d0000 0 0x10000>,
1958 <0 0x179e0000 0 0x10000>;
1959 reg-names = "drv-0", "drv-1", "drv-2";
1964 qcom,tcs-offset = <0xd00>;
2036 reg = <0 0x17a00000 0 0x10000>, /* GICD */
2037 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
2045 reg = <0 0x17d41000 0 0x1400>;
2055 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;