Lines Matching refs:gcc
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
799 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
800 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
801 <&gcc GCC_EMAC0_PTP_CLK>,
802 <&gcc GCC_EMAC0_RGMII_CLK>;
813 power-domains = <&gcc EMAC_0_GDSC>;
823 gcc: clock-controller@100000 { label
824 compatible = "qcom,gcc-sc8280xp";
889 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
890 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
905 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
921 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
937 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
953 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
967 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
983 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
999 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1013 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1033 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1049 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1065 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1081 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1096 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1113 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1130 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1145 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1162 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1177 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1192 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1193 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1209 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1224 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1241 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1256 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1273 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1288 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1302 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1319 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1334 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1349 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1366 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1383 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1398 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1415 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1430 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1447 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1462 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1477 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1478 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1493 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1509 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1525 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1541 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1557 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1573 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1589 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1605 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1621 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1637 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1653 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1669 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1685 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1701 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1717 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1733 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1788 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1789 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1790 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1791 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1792 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1793 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1794 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1795 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1796 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1807 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1814 resets = <&gcc GCC_PCIE_4_BCR>;
1817 power-domains = <&gcc PCIE_4_GDSC>;
1840 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1841 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1842 <&gcc GCC_PCIE_4_CLKREF_CLK>,
1843 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1844 <&gcc GCC_PCIE_4_PIPE_CLK>,
1845 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1849 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1852 power-domains = <&gcc PCIE_4_GDSC>;
1854 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1901 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1902 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1903 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1904 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1905 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1906 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1907 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1908 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1918 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1925 resets = <&gcc GCC_PCIE_3B_BCR>;
1928 power-domains = <&gcc PCIE_3B_GDSC>;
1951 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1952 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1953 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1954 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1955 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1956 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1960 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1963 power-domains = <&gcc PCIE_3B_GDSC>;
1965 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
2012 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2013 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2014 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
2015 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
2016 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
2017 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2018 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2019 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2029 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2036 resets = <&gcc GCC_PCIE_3A_BCR>;
2039 power-domains = <&gcc PCIE_3A_GDSC>;
2063 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2064 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2065 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2066 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2067 <&gcc GCC_PCIE_3A_PIPE_CLK>,
2068 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2072 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2075 power-domains = <&gcc PCIE_3A_GDSC>;
2077 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2126 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2127 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2128 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2129 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2130 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2131 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2132 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2133 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2143 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2150 resets = <&gcc GCC_PCIE_2B_BCR>;
2153 power-domains = <&gcc PCIE_2B_GDSC>;
2176 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2177 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2178 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2179 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2180 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2181 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2185 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2188 power-domains = <&gcc PCIE_2B_GDSC>;
2190 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2237 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2238 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2239 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2240 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2241 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2242 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2243 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2244 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2254 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2261 resets = <&gcc GCC_PCIE_2A_BCR>;
2264 power-domains = <&gcc PCIE_2A_GDSC>;
2288 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2289 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2290 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2291 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2292 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2293 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2297 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2300 power-domains = <&gcc PCIE_2A_GDSC>;
2302 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2324 resets = <&gcc GCC_UFS_PHY_BCR>;
2327 power-domains = <&gcc UFS_PHY_GDSC>;
2333 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2334 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2335 <&gcc GCC_UFS_PHY_AHB_CLK>,
2336 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2337 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2338 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2339 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2340 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2365 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2366 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
2371 power-domains = <&gcc UFS_PHY_GDSC>;
2390 resets = <&gcc GCC_UFS_CARD_BCR>;
2393 power-domains = <&gcc UFS_CARD_GDSC>;
2398 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2399 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2400 <&gcc GCC_UFS_CARD_AHB_CLK>,
2401 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2402 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2403 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2404 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2405 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2430 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
2431 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
2436 power-domains = <&gcc UFS_CARD_GDSC>;
2541 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2542 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2579 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2580 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2612 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2613 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2637 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2648 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2650 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2661 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2663 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2674 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2676 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2687 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2689 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2700 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2701 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2702 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2703 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2706 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2707 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2710 power-domains = <&gcc USB30_MP_GDSC>;
2724 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2725 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2726 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2727 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2730 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2731 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2734 power-domains = <&gcc USB30_MP_GDSC>;
3177 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3178 <&gcc GCC_SDCC2_APPS_CLK>,
3181 resets = <&gcc GCC_SDCC2_BCR>;
3216 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3217 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3218 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3219 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3222 power-domains = <&gcc USB30_PRIM_GDSC>;
3224 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3225 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3268 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3277 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3278 <&gcc GCC_USB4_CLKREF_CLK>,
3279 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3280 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3283 power-domains = <&gcc USB30_SEC_GDSC>;
3285 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3286 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3467 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
3468 <&gcc GCC_USB30_MP_MASTER_CLK>,
3469 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
3470 <&gcc GCC_USB30_MP_SLEEP_CLK>,
3471 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3472 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3473 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3474 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3475 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3479 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3480 <&gcc GCC_USB30_MP_MASTER_CLK>;
3512 power-domains = <&gcc USB30_MP_GDSC>;
3515 resets = <&gcc GCC_USB30_MP_BCR>;
3551 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3552 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3553 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3554 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3555 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3556 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3557 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3558 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3559 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3563 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3564 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3578 power-domains = <&gcc USB30_PRIM_GDSC>;
3581 resets = <&gcc GCC_USB30_PRIM_BCR>;
3630 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3631 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3632 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3633 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3634 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3635 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3636 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3637 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3638 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3642 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3643 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3657 power-domains = <&gcc USB30_SEC_GDSC>;
3660 resets = <&gcc GCC_USB30_SEC_BCR>;
3999 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4000 <&gcc GCC_CAMERA_SF_AXI_CLK>;
4103 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4119 clocks = <&gcc GCC_DISP_AHB_CLK>,
4147 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4148 <&gcc GCC_DISP_SF_AXI_CLK>,
4571 clocks = <&gcc GCC_DISP_AHB_CLK>,
5237 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5254 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5436 clocks = <&gcc GCC_DISP_AHB_CLK>,
5465 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5466 <&gcc GCC_DISP_SF_AXI_CLK>,
5876 clocks = <&gcc GCC_DISP_AHB_CLK>,
5906 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
5907 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
5908 <&gcc GCC_EMAC1_PTP_CLK>,
5909 <&gcc GCC_EMAC1_RGMII_CLK>;
5920 power-domains = <&gcc EMAC_1_GDSC>;