Lines Matching +full:spi +full:- +full:qup +full:- +full:v2
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
31 xo_board_clk: xo-board-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32764>;
44 #address-cells = <2>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a78c";
52 enable-method = "psci";
53 capacity-dmips-mhz = <981>;
54 dynamic-power-coefficient = <549>;
55 next-level-cache = <&l2_0>;
56 power-domains = <&cpu_pd0>;
57 power-domain-names = "psci";
58 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = <&cpu0_opp_table>;
61 #cooling-cells = <2>;
62 l2_0: l2-cache {
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&l3_0>;
67 l3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
77 compatible = "arm,cortex-a78c";
80 enable-method = "psci";
81 capacity-dmips-mhz = <981>;
82 dynamic-power-coefficient = <549>;
83 next-level-cache = <&l2_100>;
84 power-domains = <&cpu_pd1>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = <&cpu0_opp_table>;
89 #cooling-cells = <2>;
90 l2_100: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&l3_0>;
100 compatible = "arm,cortex-a78c";
103 enable-method = "psci";
104 capacity-dmips-mhz = <981>;
105 dynamic-power-coefficient = <549>;
106 next-level-cache = <&l2_200>;
107 power-domains = <&cpu_pd2>;
108 power-domain-names = "psci";
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
112 #cooling-cells = <2>;
113 l2_200: l2-cache {
115 cache-level = <2>;
116 cache-unified;
117 next-level-cache = <&l3_0>;
123 compatible = "arm,cortex-a78c";
126 enable-method = "psci";
127 capacity-dmips-mhz = <981>;
128 dynamic-power-coefficient = <549>;
129 next-level-cache = <&l2_300>;
130 power-domains = <&cpu_pd3>;
131 power-domain-names = "psci";
132 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = <&cpu0_opp_table>;
135 #cooling-cells = <2>;
136 l2_300: l2-cache {
138 cache-level = <2>;
139 cache-unified;
140 next-level-cache = <&l3_0>;
146 compatible = "arm,cortex-x1c";
149 enable-method = "psci";
150 capacity-dmips-mhz = <1024>;
151 dynamic-power-coefficient = <590>;
152 next-level-cache = <&l2_400>;
153 power-domains = <&cpu_pd4>;
154 power-domain-names = "psci";
155 qcom,freq-domain = <&cpufreq_hw 1>;
156 operating-points-v2 = <&cpu4_opp_table>;
158 #cooling-cells = <2>;
159 l2_400: l2-cache {
161 cache-level = <2>;
162 cache-unified;
163 next-level-cache = <&l3_0>;
169 compatible = "arm,cortex-x1c";
172 enable-method = "psci";
173 capacity-dmips-mhz = <1024>;
174 dynamic-power-coefficient = <590>;
175 next-level-cache = <&l2_500>;
176 power-domains = <&cpu_pd5>;
177 power-domain-names = "psci";
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu4_opp_table>;
181 #cooling-cells = <2>;
182 l2_500: l2-cache {
184 cache-level = <2>;
185 cache-unified;
186 next-level-cache = <&l3_0>;
192 compatible = "arm,cortex-x1c";
195 enable-method = "psci";
196 capacity-dmips-mhz = <1024>;
197 dynamic-power-coefficient = <590>;
198 next-level-cache = <&l2_600>;
199 power-domains = <&cpu_pd6>;
200 power-domain-names = "psci";
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu4_opp_table>;
204 #cooling-cells = <2>;
205 l2_600: l2-cache {
207 cache-level = <2>;
208 cache-unified;
209 next-level-cache = <&l3_0>;
215 compatible = "arm,cortex-x1c";
218 enable-method = "psci";
219 capacity-dmips-mhz = <1024>;
220 dynamic-power-coefficient = <590>;
221 next-level-cache = <&l2_700>;
222 power-domains = <&cpu_pd7>;
223 power-domain-names = "psci";
224 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = <&cpu4_opp_table>;
227 #cooling-cells = <2>;
228 l2_700: l2-cache {
230 cache-level = <2>;
231 cache-unified;
232 next-level-cache = <&l3_0>;
236 cpu-map {
272 idle-states {
273 entry-method = "psci";
275 little_cpu_sleep_0: cpu-sleep-0-0 {
276 compatible = "arm,idle-state";
277 idle-state-name = "little-rail-power-collapse";
278 arm,psci-suspend-param = <0x40000004>;
279 entry-latency-us = <355>;
280 exit-latency-us = <909>;
281 min-residency-us = <3934>;
282 local-timer-stop;
285 big_cpu_sleep_0: cpu-sleep-1-0 {
286 compatible = "arm,idle-state";
287 idle-state-name = "big-rail-power-collapse";
288 arm,psci-suspend-param = <0x40000004>;
289 entry-latency-us = <241>;
290 exit-latency-us = <1461>;
291 min-residency-us = <4488>;
292 local-timer-stop;
296 domain-idle-states {
297 cluster_sleep_0: cluster-sleep-0 {
298 compatible = "domain-idle-state";
299 arm,psci-suspend-param = <0x4100c344>;
300 entry-latency-us = <3263>;
301 exit-latency-us = <6562>;
302 min-residency-us = <9987>;
309 compatible = "qcom,scm-sc8280xp", "qcom,scm";
311 qcom,dload-mode = <&tcsr 0x13000>;
315 aggre1_noc: interconnect-aggre1-noc {
316 compatible = "qcom,sc8280xp-aggre1-noc";
317 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_voter>;
321 aggre2_noc: interconnect-aggre2-noc {
322 compatible = "qcom,sc8280xp-aggre2-noc";
323 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_voter>;
327 clk_virt: interconnect-clk-virt {
328 compatible = "qcom,sc8280xp-clk-virt";
329 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_voter>;
333 config_noc: interconnect-config-noc {
334 compatible = "qcom,sc8280xp-config-noc";
335 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_voter>;
339 dc_noc: interconnect-dc-noc {
340 compatible = "qcom,sc8280xp-dc-noc";
341 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_voter>;
345 gem_noc: interconnect-gem-noc {
346 compatible = "qcom,sc8280xp-gem-noc";
347 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_voter>;
351 lpass_noc: interconnect-lpass-ag-noc {
352 compatible = "qcom,sc8280xp-lpass-ag-noc";
353 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_voter>;
357 mc_virt: interconnect-mc-virt {
358 compatible = "qcom,sc8280xp-mc-virt";
359 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_voter>;
363 mmss_noc: interconnect-mmss-noc {
364 compatible = "qcom,sc8280xp-mmss-noc";
365 #interconnect-cells = <2>;
366 qcom,bcm-voters = <&apps_bcm_voter>;
369 nspa_noc: interconnect-nspa-noc {
370 compatible = "qcom,sc8280xp-nspa-noc";
371 #interconnect-cells = <2>;
372 qcom,bcm-voters = <&apps_bcm_voter>;
375 nspb_noc: interconnect-nspb-noc {
376 compatible = "qcom,sc8280xp-nspb-noc";
377 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_voter>;
381 system_noc: interconnect-system-noc {
382 compatible = "qcom,sc8280xp-system-noc";
383 #interconnect-cells = <2>;
384 qcom,bcm-voters = <&apps_bcm_voter>;
393 cpu0_opp_table: opp-table-cpu0 {
394 compatible = "operating-points-v2";
395 opp-shared;
397 opp-300000000 {
398 opp-hz = /bits/ 64 <300000000>;
399 opp-peak-kBps = <(300000 * 32)>;
401 opp-403200000 {
402 opp-hz = /bits/ 64 <403200000>;
403 opp-peak-kBps = <(384000 * 32)>;
405 opp-499200000 {
406 opp-hz = /bits/ 64 <499200000>;
407 opp-peak-kBps = <(480000 * 32)>;
409 opp-595200000 {
410 opp-hz = /bits/ 64 <595200000>;
411 opp-peak-kBps = <(576000 * 32)>;
413 opp-691200000 {
414 opp-hz = /bits/ 64 <691200000>;
415 opp-peak-kBps = <(672000 * 32)>;
417 opp-806400000 {
418 opp-hz = /bits/ 64 <806400000>;
419 opp-peak-kBps = <(768000 * 32)>;
421 opp-902400000 {
422 opp-hz = /bits/ 64 <902400000>;
423 opp-peak-kBps = <(864000 * 32)>;
425 opp-1017600000 {
426 opp-hz = /bits/ 64 <1017600000>;
427 opp-peak-kBps = <(960000 * 32)>;
429 opp-1113600000 {
430 opp-hz = /bits/ 64 <1113600000>;
431 opp-peak-kBps = <(1075200 * 32)>;
433 opp-1209600000 {
434 opp-hz = /bits/ 64 <1209600000>;
435 opp-peak-kBps = <(1171200 * 32)>;
437 opp-1324800000 {
438 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <(1267200 * 32)>;
441 opp-1440000000 {
442 opp-hz = /bits/ 64 <1440000000>;
443 opp-peak-kBps = <(1363200 * 32)>;
445 opp-1555200000 {
446 opp-hz = /bits/ 64 <1555200000>;
447 opp-peak-kBps = <(1536000 * 32)>;
449 opp-1670400000 {
450 opp-hz = /bits/ 64 <1670400000>;
451 opp-peak-kBps = <(1612800 * 32)>;
453 opp-1785600000 {
454 opp-hz = /bits/ 64 <1785600000>;
455 opp-peak-kBps = <(1689600 * 32)>;
457 opp-1881600000 {
458 opp-hz = /bits/ 64 <1881600000>;
459 opp-peak-kBps = <(1689600 * 32)>;
461 opp-1996800000 {
462 opp-hz = /bits/ 64 <1996800000>;
463 opp-peak-kBps = <(1689600 * 32)>;
465 opp-2112000000 {
466 opp-hz = /bits/ 64 <2112000000>;
467 opp-peak-kBps = <(1689600 * 32)>;
469 opp-2227200000 {
470 opp-hz = /bits/ 64 <2227200000>;
471 opp-peak-kBps = <(1689600 * 32)>;
473 opp-2342400000 {
474 opp-hz = /bits/ 64 <2342400000>;
475 opp-peak-kBps = <(1689600 * 32)>;
477 opp-2438400000 {
478 opp-hz = /bits/ 64 <2438400000>;
479 opp-peak-kBps = <(1689600 * 32)>;
483 cpu4_opp_table: opp-table-cpu4 {
484 compatible = "operating-points-v2";
485 opp-shared;
487 opp-825600000 {
488 opp-hz = /bits/ 64 <825600000>;
489 opp-peak-kBps = <(768000 * 32)>;
491 opp-940800000 {
492 opp-hz = /bits/ 64 <940800000>;
493 opp-peak-kBps = <(864000 * 32)>;
495 opp-1056000000 {
496 opp-hz = /bits/ 64 <1056000000>;
497 opp-peak-kBps = <(960000 * 32)>;
499 opp-1171200000 {
500 opp-hz = /bits/ 64 <1171200000>;
501 opp-peak-kBps = <(1171200 * 32)>;
503 opp-1286400000 {
504 opp-hz = /bits/ 64 <1286400000>;
505 opp-peak-kBps = <(1267200 * 32)>;
507 opp-1401600000 {
508 opp-hz = /bits/ 64 <1401600000>;
509 opp-peak-kBps = <(1363200 * 32)>;
511 opp-1516800000 {
512 opp-hz = /bits/ 64 <1516800000>;
513 opp-peak-kBps = <(1459200 * 32)>;
515 opp-1632000000 {
516 opp-hz = /bits/ 64 <1632000000>;
517 opp-peak-kBps = <(1612800 * 32)>;
519 opp-1747200000 {
520 opp-hz = /bits/ 64 <1747200000>;
521 opp-peak-kBps = <(1689600 * 32)>;
523 opp-1862400000 {
524 opp-hz = /bits/ 64 <1862400000>;
525 opp-peak-kBps = <(1689600 * 32)>;
527 opp-1977600000 {
528 opp-hz = /bits/ 64 <1977600000>;
529 opp-peak-kBps = <(1689600 * 32)>;
531 opp-2073600000 {
532 opp-hz = /bits/ 64 <2073600000>;
533 opp-peak-kBps = <(1689600 * 32)>;
535 opp-2169600000 {
536 opp-hz = /bits/ 64 <2169600000>;
537 opp-peak-kBps = <(1689600 * 32)>;
539 opp-2284800000 {
540 opp-hz = /bits/ 64 <2284800000>;
541 opp-peak-kBps = <(1689600 * 32)>;
543 opp-2400000000 {
544 opp-hz = /bits/ 64 <2400000000>;
545 opp-peak-kBps = <(1689600 * 32)>;
547 opp-2496000000 {
548 opp-hz = /bits/ 64 <2496000000>;
549 opp-peak-kBps = <(1689600 * 32)>;
551 opp-2592000000 {
552 opp-hz = /bits/ 64 <2592000000>;
553 opp-peak-kBps = <(1689600 * 32)>;
555 opp-2688000000 {
556 opp-hz = /bits/ 64 <2688000000>;
557 opp-peak-kBps = <(1689600 * 32)>;
559 opp-2803200000 {
560 opp-hz = /bits/ 64 <2803200000>;
561 opp-peak-kBps = <(1689600 * 32)>;
563 opp-2899200000 {
564 opp-hz = /bits/ 64 <2899200000>;
565 opp-peak-kBps = <(1689600 * 32)>;
567 opp-2995200000 {
568 opp-hz = /bits/ 64 <2995200000>;
569 opp-peak-kBps = <(1689600 * 32)>;
573 qup_opp_table_100mhz: opp-table-qup100mhz {
574 compatible = "operating-points-v2";
576 opp-75000000 {
577 opp-hz = /bits/ 64 <75000000>;
578 required-opps = <&rpmhpd_opp_low_svs>;
581 opp-100000000 {
582 opp-hz = /bits/ 64 <100000000>;
583 required-opps = <&rpmhpd_opp_svs>;
588 compatible = "arm,armv8-pmuv3";
593 compatible = "arm,psci-1.0";
596 cpu_pd0: power-domain-cpu0 {
597 #power-domain-cells = <0>;
598 power-domains = <&cluster_pd>;
599 domain-idle-states = <&little_cpu_sleep_0>;
602 cpu_pd1: power-domain-cpu1 {
603 #power-domain-cells = <0>;
604 power-domains = <&cluster_pd>;
605 domain-idle-states = <&little_cpu_sleep_0>;
608 cpu_pd2: power-domain-cpu2 {
609 #power-domain-cells = <0>;
610 power-domains = <&cluster_pd>;
611 domain-idle-states = <&little_cpu_sleep_0>;
614 cpu_pd3: power-domain-cpu3 {
615 #power-domain-cells = <0>;
616 power-domains = <&cluster_pd>;
617 domain-idle-states = <&little_cpu_sleep_0>;
620 cpu_pd4: power-domain-cpu4 {
621 #power-domain-cells = <0>;
622 power-domains = <&cluster_pd>;
623 domain-idle-states = <&big_cpu_sleep_0>;
626 cpu_pd5: power-domain-cpu5 {
627 #power-domain-cells = <0>;
628 power-domains = <&cluster_pd>;
629 domain-idle-states = <&big_cpu_sleep_0>;
632 cpu_pd6: power-domain-cpu6 {
633 #power-domain-cells = <0>;
634 power-domains = <&cluster_pd>;
635 domain-idle-states = <&big_cpu_sleep_0>;
638 cpu_pd7: power-domain-cpu7 {
639 #power-domain-cells = <0>;
640 power-domains = <&cluster_pd>;
641 domain-idle-states = <&big_cpu_sleep_0>;
644 cluster_pd: power-domain-cpu-cluster0 {
645 #power-domain-cells = <0>;
646 domain-idle-states = <&cluster_sleep_0>;
650 reserved-memory {
651 #address-cells = <2>;
652 #size-cells = <2>;
655 reserved-region@80000000 {
657 no-map;
660 cmd_db: cmd-db-region@80860000 {
661 compatible = "qcom,cmd-db";
663 no-map;
666 reserved-region@80880000 {
668 no-map;
671 smem_mem: smem-region@80900000 {
674 no-map;
678 reserved-region@80b00000 {
680 no-map;
683 reserved-region@83b00000 {
685 no-map;
688 reserved-region@85b00000 {
690 no-map;
693 pil_adsp_mem: adsp-region@86c00000 {
695 no-map;
698 pil_nsp0_mem: cdsp0-region@8a100000 {
700 no-map;
703 pil_nsp1_mem: cdsp1-region@8c600000 {
705 no-map;
708 reserved-region@aeb00000 {
710 no-map;
714 smp2p-adsp {
717 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <2>;
726 smp2p_adsp_out: master-kernel {
727 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells = <1>;
731 smp2p_adsp_in: slave-kernel {
732 qcom,entry-name = "slave-kernel";
733 interrupt-controller;
734 #interrupt-cells = <2>;
738 smp2p-nsp0 {
741 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
747 qcom,local-pid = <0>;
748 qcom,remote-pid = <5>;
750 smp2p_nsp0_out: master-kernel {
751 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells = <1>;
755 smp2p_nsp0_in: slave-kernel {
756 qcom,entry-name = "slave-kernel";
757 interrupt-controller;
758 #interrupt-cells = <2>;
762 smp2p-nsp1 {
765 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
771 qcom,local-pid = <0>;
772 qcom,remote-pid = <12>;
774 smp2p_nsp1_out: master-kernel {
775 qcom,entry-name = "master-kernel";
776 #qcom,smem-state-cells = <1>;
779 smp2p_nsp1_in: slave-kernel {
780 qcom,entry-name = "slave-kernel";
781 interrupt-controller;
782 #interrupt-cells = <2>;
787 compatible = "simple-bus";
788 #address-cells = <2>;
789 #size-cells = <2>;
791 dma-ranges = <0 0 0 0 0x10 0>;
794 compatible = "qcom,sc8280xp-ethqos";
797 reg-names = "stmmaceth", "rgmii";
803 clock-names = "stmmaceth",
810 interrupt-names = "macirq", "eth_lpi";
813 power-domains = <&gcc EMAC_0_GDSC>;
817 rx-fifo-depth = <4096>;
818 tx-fifo-depth = <4096>;
823 gcc: clock-controller@100000 {
824 compatible = "qcom,gcc-sc8280xp";
826 #clock-cells = <1>;
827 #reset-cells = <1>;
828 #power-domain-cells = <1>;
862 power-domains = <&rpmhpd SC8280XP_CX>;
866 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
869 interrupt-controller;
870 #interrupt-cells = <3>;
871 #mbox-cells = <2>;
875 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom";
877 #address-cells = <1>;
878 #size-cells = <1>;
880 gpu_speed_bin: gpu-speed-bin@18b {
887 compatible = "qcom,geni-se-qup";
891 clock-names = "m-ahb", "s-ahb";
894 #address-cells = <2>;
895 #size-cells = <2>;
901 compatible = "qcom,geni-i2c";
903 #address-cells = <1>;
904 #size-cells = <0>;
906 clock-names = "se";
908 power-domains = <&rpmhpd SC8280XP_CX>;
912 interconnect-names = "qup-core", "qup-config", "qup-memory";
916 spi16: spi@880000 {
917 compatible = "qcom,geni-spi";
919 #address-cells = <1>;
920 #size-cells = <0>;
922 clock-names = "se";
924 power-domains = <&rpmhpd SC8280XP_CX>;
928 interconnect-names = "qup-core", "qup-config", "qup-memory";
933 compatible = "qcom,geni-i2c";
935 #address-cells = <1>;
936 #size-cells = <0>;
938 clock-names = "se";
940 power-domains = <&rpmhpd SC8280XP_CX>;
944 interconnect-names = "qup-core", "qup-config", "qup-memory";
948 spi17: spi@884000 {
949 compatible = "qcom,geni-spi";
951 #address-cells = <1>;
952 #size-cells = <0>;
954 clock-names = "se";
956 power-domains = <&rpmhpd SC8280XP_CX>;
960 interconnect-names = "qup-core", "qup-config", "qup-memory";
965 compatible = "qcom,geni-uart";
968 clock-names = "se";
970 operating-points-v2 = <&qup_opp_table_100mhz>;
971 power-domains = <&rpmhpd SC8280XP_CX>;
974 interconnect-names = "qup-core", "qup-config";
979 compatible = "qcom,geni-i2c";
981 #address-cells = <1>;
982 #size-cells = <0>;
984 clock-names = "se";
986 power-domains = <&rpmhpd SC8280XP_CX>;
990 interconnect-names = "qup-core", "qup-config", "qup-memory";
994 spi18: spi@888000 {
995 compatible = "qcom,geni-spi";
997 #address-cells = <1>;
998 #size-cells = <0>;
1000 clock-names = "se";
1002 power-domains = <&rpmhpd SC8280XP_CX>;
1006 interconnect-names = "qup-core", "qup-config", "qup-memory";
1011 compatible = "qcom,geni-uart";
1014 clock-names = "se";
1016 operating-points-v2 = <&qup_opp_table_100mhz>;
1017 power-domains = <&rpmhpd SC8280XP_CX>;
1020 interconnect-names = "qup-core", "qup-config";
1022 pinctrl-0 = <&qup_uart18_default>;
1023 pinctrl-names = "default";
1029 compatible = "qcom,geni-i2c";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1034 clock-names = "se";
1036 power-domains = <&rpmhpd SC8280XP_CX>;
1040 interconnect-names = "qup-core", "qup-config", "qup-memory";
1044 spi19: spi@88c000 {
1045 compatible = "qcom,geni-spi";
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1050 clock-names = "se";
1052 power-domains = <&rpmhpd SC8280XP_CX>;
1056 interconnect-names = "qup-core", "qup-config", "qup-memory";
1061 compatible = "qcom,geni-i2c";
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1066 clock-names = "se";
1068 power-domains = <&rpmhpd SC8280XP_CX>;
1072 interconnect-names = "qup-core", "qup-config", "qup-memory";
1076 spi20: spi@890000 {
1077 compatible = "qcom,geni-spi";
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1082 clock-names = "se";
1084 power-domains = <&rpmhpd SC8280XP_CX>;
1088 interconnect-names = "qup-core", "qup-config", "qup-memory";
1093 compatible = "qcom,geni-i2c";
1095 clock-names = "se";
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 power-domains = <&rpmhpd SC8280XP_CX>;
1104 interconnect-names = "qup-core", "qup-config", "qup-memory";
1108 spi21: spi@894000 {
1109 compatible = "qcom,geni-spi";
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1114 clock-names = "se";
1116 power-domains = <&rpmhpd SC8280XP_CX>;
1120 interconnect-names = "qup-core", "qup-config", "qup-memory";
1125 compatible = "qcom,geni-i2c";
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129 clock-names = "se";
1132 power-domains = <&rpmhpd SC8280XP_CX>;
1136 interconnect-names = "qup-core", "qup-config", "qup-memory";
1140 spi22: spi@898000 {
1141 compatible = "qcom,geni-spi";
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1146 clock-names = "se";
1148 power-domains = <&rpmhpd SC8280XP_CX>;
1152 interconnect-names = "qup-core", "qup-config", "qup-memory";
1157 compatible = "qcom,geni-i2c";
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1161 clock-names = "se";
1164 power-domains = <&rpmhpd SC8280XP_CX>;
1168 interconnect-names = "qup-core", "qup-config", "qup-memory";
1172 spi23: spi@89c000 {
1173 compatible = "qcom,geni-spi";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1178 clock-names = "se";
1180 power-domains = <&rpmhpd SC8280XP_CX>;
1184 interconnect-names = "qup-core", "qup-config", "qup-memory";
1190 compatible = "qcom,geni-se-qup";
1194 clock-names = "m-ahb", "s-ahb";
1197 #address-cells = <2>;
1198 #size-cells = <2>;
1204 compatible = "qcom,geni-i2c";
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1208 clock-names = "se";
1211 power-domains = <&rpmhpd SC8280XP_CX>;
1215 interconnect-names = "qup-core", "qup-config", "qup-memory";
1219 spi0: spi@980000 {
1220 compatible = "qcom,geni-spi";
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1225 clock-names = "se";
1227 power-domains = <&rpmhpd SC8280XP_CX>;
1231 interconnect-names = "qup-core", "qup-config", "qup-memory";
1236 compatible = "qcom,geni-i2c";
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1240 clock-names = "se";
1243 power-domains = <&rpmhpd SC8280XP_CX>;
1247 interconnect-names = "qup-core", "qup-config", "qup-memory";
1251 spi1: spi@984000 {
1252 compatible = "qcom,geni-spi";
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1257 clock-names = "se";
1259 power-domains = <&rpmhpd SC8280XP_CX>;
1263 interconnect-names = "qup-core", "qup-config", "qup-memory";
1268 compatible = "qcom,geni-i2c";
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1272 clock-names = "se";
1275 power-domains = <&rpmhpd SC8280XP_CX>;
1279 interconnect-names = "qup-core", "qup-config", "qup-memory";
1283 spi2: spi@988000 {
1284 compatible = "qcom,geni-spi";
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1289 clock-names = "se";
1291 power-domains = <&rpmhpd SC8280XP_CX>;
1295 interconnect-names = "qup-core", "qup-config", "qup-memory";
1300 compatible = "qcom,geni-uart";
1303 clock-names = "se";
1305 operating-points-v2 = <&qup_opp_table_100mhz>;
1306 power-domains = <&rpmhpd SC8280XP_CX>;
1309 interconnect-names = "qup-core", "qup-config";
1314 compatible = "qcom,geni-i2c";
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1318 clock-names = "se";
1321 power-domains = <&rpmhpd SC8280XP_CX>;
1325 interconnect-names = "qup-core", "qup-config", "qup-memory";
1329 spi3: spi@98c000 {
1330 compatible = "qcom,geni-spi";
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1335 clock-names = "se";
1337 power-domains = <&rpmhpd SC8280XP_CX>;
1341 interconnect-names = "qup-core", "qup-config", "qup-memory";
1346 compatible = "qcom,geni-i2c";
1348 clock-names = "se";
1351 #address-cells = <1>;
1352 #size-cells = <0>;
1353 power-domains = <&rpmhpd SC8280XP_CX>;
1357 interconnect-names = "qup-core", "qup-config", "qup-memory";
1361 spi4: spi@990000 {
1362 compatible = "qcom,geni-spi";
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1367 clock-names = "se";
1369 power-domains = <&rpmhpd SC8280XP_CX>;
1373 interconnect-names = "qup-core", "qup-config", "qup-memory";
1378 compatible = "qcom,geni-i2c";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1382 clock-names = "se";
1385 power-domains = <&rpmhpd SC8280XP_CX>;
1389 interconnect-names = "qup-core", "qup-config", "qup-memory";
1393 spi5: spi@994000 {
1394 compatible = "qcom,geni-spi";
1396 #address-cells = <1>;
1397 #size-cells = <0>;
1399 clock-names = "se";
1401 power-domains = <&rpmhpd SC8280XP_CX>;
1405 interconnect-names = "qup-core", "qup-config", "qup-memory";
1410 compatible = "qcom,geni-i2c";
1412 #address-cells = <1>;
1413 #size-cells = <0>;
1414 clock-names = "se";
1417 power-domains = <&rpmhpd SC8280XP_CX>;
1421 interconnect-names = "qup-core", "qup-config", "qup-memory";
1425 spi6: spi@998000 {
1426 compatible = "qcom,geni-spi";
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1431 clock-names = "se";
1433 power-domains = <&rpmhpd SC8280XP_CX>;
1437 interconnect-names = "qup-core", "qup-config", "qup-memory";
1442 compatible = "qcom,geni-i2c";
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1446 clock-names = "se";
1449 power-domains = <&rpmhpd SC8280XP_CX>;
1453 interconnect-names = "qup-core", "qup-config", "qup-memory";
1457 spi7: spi@99c000 {
1458 compatible = "qcom,geni-spi";
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1463 clock-names = "se";
1465 power-domains = <&rpmhpd SC8280XP_CX>;
1469 interconnect-names = "qup-core", "qup-config", "qup-memory";
1475 compatible = "qcom,geni-se-qup";
1479 clock-names = "m-ahb", "s-ahb";
1482 #address-cells = <2>;
1483 #size-cells = <2>;
1489 compatible = "qcom,geni-i2c";
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1494 clock-names = "se";
1496 power-domains = <&rpmhpd SC8280XP_CX>;
1500 interconnect-names = "qup-core", "qup-config", "qup-memory";
1504 spi8: spi@a80000 {
1505 compatible = "qcom,geni-spi";
1507 #address-cells = <1>;
1508 #size-cells = <0>;
1510 clock-names = "se";
1512 power-domains = <&rpmhpd SC8280XP_CX>;
1516 interconnect-names = "qup-core", "qup-config", "qup-memory";
1521 compatible = "qcom,geni-i2c";
1523 #address-cells = <1>;
1524 #size-cells = <0>;
1526 clock-names = "se";
1528 power-domains = <&rpmhpd SC8280XP_CX>;
1532 interconnect-names = "qup-core", "qup-config", "qup-memory";
1536 spi9: spi@a84000 {
1537 compatible = "qcom,geni-spi";
1539 #address-cells = <1>;
1540 #size-cells = <0>;
1542 clock-names = "se";
1544 power-domains = <&rpmhpd SC8280XP_CX>;
1548 interconnect-names = "qup-core", "qup-config", "qup-memory";
1553 compatible = "qcom,geni-i2c";
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1558 clock-names = "se";
1560 power-domains = <&rpmhpd SC8280XP_CX>;
1564 interconnect-names = "qup-core", "qup-config", "qup-memory";
1568 spi10: spi@a88000 {
1569 compatible = "qcom,geni-spi";
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1574 clock-names = "se";
1576 power-domains = <&rpmhpd SC8280XP_CX>;
1580 interconnect-names = "qup-core", "qup-config", "qup-memory";
1585 compatible = "qcom,geni-i2c";
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1590 clock-names = "se";
1592 power-domains = <&rpmhpd SC8280XP_CX>;
1596 interconnect-names = "qup-core", "qup-config", "qup-memory";
1600 spi11: spi@a8c000 {
1601 compatible = "qcom,geni-spi";
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1606 clock-names = "se";
1608 power-domains = <&rpmhpd SC8280XP_CX>;
1612 interconnect-names = "qup-core", "qup-config", "qup-memory";
1617 compatible = "qcom,geni-i2c";
1619 #address-cells = <1>;
1620 #size-cells = <0>;
1622 clock-names = "se";
1624 power-domains = <&rpmhpd SC8280XP_CX>;
1628 interconnect-names = "qup-core", "qup-config", "qup-memory";
1632 spi12: spi@a90000 {
1633 compatible = "qcom,geni-spi";
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1638 clock-names = "se";
1640 power-domains = <&rpmhpd SC8280XP_CX>;
1644 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 compatible = "qcom,geni-i2c";
1651 #address-cells = <1>;
1652 #size-cells = <0>;
1654 clock-names = "se";
1656 power-domains = <&rpmhpd SC8280XP_CX>;
1660 interconnect-names = "qup-core", "qup-config", "qup-memory";
1664 spi13: spi@a94000 {
1665 compatible = "qcom,geni-spi";
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1670 clock-names = "se";
1672 power-domains = <&rpmhpd SC8280XP_CX>;
1676 interconnect-names = "qup-core", "qup-config", "qup-memory";
1681 compatible = "qcom,geni-i2c";
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1686 clock-names = "se";
1688 power-domains = <&rpmhpd SC8280XP_CX>;
1692 interconnect-names = "qup-core", "qup-config", "qup-memory";
1696 spi14: spi@a98000 {
1697 compatible = "qcom,geni-spi";
1699 #address-cells = <1>;
1700 #size-cells = <0>;
1702 clock-names = "se";
1704 power-domains = <&rpmhpd SC8280XP_CX>;
1708 interconnect-names = "qup-core", "qup-config", "qup-memory";
1713 compatible = "qcom,geni-i2c";
1715 #address-cells = <1>;
1716 #size-cells = <0>;
1718 clock-names = "se";
1720 power-domains = <&rpmhpd SC8280XP_CX>;
1724 interconnect-names = "qup-core", "qup-config", "qup-memory";
1728 spi15: spi@a9c000 {
1729 compatible = "qcom,geni-spi";
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1734 clock-names = "se";
1736 power-domains = <&rpmhpd SC8280XP_CX>;
1740 interconnect-names = "qup-core", "qup-config", "qup-memory";
1746 compatible = "qcom,prng-ee";
1749 clock-names = "core";
1754 compatible = "qcom,pcie-sc8280xp";
1761 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1762 #address-cells = <3>;
1763 #size-cells = <2>;
1766 bus-range = <0x00 0xff>;
1768 dma-coherent;
1770 linux,pci-domain = <6>;
1771 num-lanes = <1>;
1773 msi-map = <0x0 &its 0xe0000 0x10000>;
1779 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1781 #interrupt-cells = <1>;
1782 interrupt-map-mask = <0 0 0 0x7>;
1783 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1797 clock-names = "aux",
1807 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1808 assigned-clock-rates = <19200000>;
1812 interconnect-names = "pcie-mem", "cpu-pcie";
1815 reset-names = "pci";
1817 power-domains = <&gcc PCIE_4_GDSC>;
1818 required-opps = <&rpmhpd_opp_nom>;
1821 phy-names = "pciephy";
1828 bus-range = <0x01 0xff>;
1830 #address-cells = <3>;
1831 #size-cells = <2>;
1837 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1846 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1849 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1850 assigned-clock-rates = <100000000>;
1852 power-domains = <&gcc PCIE_4_GDSC>;
1855 reset-names = "phy";
1857 #clock-cells = <0>;
1858 clock-output-names = "pcie_4_pipe_clk";
1860 #phy-cells = <0>;
1867 compatible = "qcom,pcie-sc8280xp";
1874 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1875 #address-cells = <3>;
1876 #size-cells = <2>;
1879 bus-range = <0x00 0xff>;
1881 dma-coherent;
1883 linux,pci-domain = <5>;
1884 num-lanes = <2>;
1886 msi-map = <0x0 &its 0xd0000 0x10000>;
1892 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1894 #interrupt-cells = <1>;
1895 interrupt-map-mask = <0 0 0 0x7>;
1896 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1909 clock-names = "aux",
1918 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1919 assigned-clock-rates = <19200000>;
1923 interconnect-names = "pcie-mem", "cpu-pcie";
1926 reset-names = "pci";
1928 power-domains = <&gcc PCIE_3B_GDSC>;
1929 required-opps = <&rpmhpd_opp_nom>;
1932 phy-names = "pciephy";
1939 bus-range = <0x01 0xff>;
1941 #address-cells = <3>;
1942 #size-cells = <2>;
1948 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1957 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1960 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1961 assigned-clock-rates = <100000000>;
1963 power-domains = <&gcc PCIE_3B_GDSC>;
1966 reset-names = "phy";
1968 #clock-cells = <0>;
1969 clock-output-names = "pcie_3b_pipe_clk";
1971 #phy-cells = <0>;
1978 compatible = "qcom,pcie-sc8280xp";
1985 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1986 #address-cells = <3>;
1987 #size-cells = <2>;
1990 bus-range = <0x00 0xff>;
1992 dma-coherent;
1994 linux,pci-domain = <4>;
1995 num-lanes = <4>;
1997 msi-map = <0x0 &its 0xc0000 0x10000>;
2003 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2005 #interrupt-cells = <1>;
2006 interrupt-map-mask = <0 0 0 0x7>;
2007 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
2020 clock-names = "aux",
2029 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2030 assigned-clock-rates = <19200000>;
2034 interconnect-names = "pcie-mem", "cpu-pcie";
2037 reset-names = "pci";
2039 power-domains = <&gcc PCIE_3A_GDSC>;
2040 required-opps = <&rpmhpd_opp_nom>;
2043 phy-names = "pciephy";
2050 bus-range = <0x01 0xff>;
2052 #address-cells = <3>;
2053 #size-cells = <2>;
2059 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2069 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2072 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2073 assigned-clock-rates = <100000000>;
2075 power-domains = <&gcc PCIE_3A_GDSC>;
2078 reset-names = "phy";
2080 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2082 #clock-cells = <0>;
2083 clock-output-names = "pcie_3a_pipe_clk";
2085 #phy-cells = <0>;
2092 compatible = "qcom,pcie-sc8280xp";
2099 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2100 #address-cells = <3>;
2101 #size-cells = <2>;
2104 bus-range = <0x00 0xff>;
2106 dma-coherent;
2108 linux,pci-domain = <3>;
2109 num-lanes = <2>;
2111 msi-map = <0x0 &its 0xb0000 0x10000>;
2117 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2119 #interrupt-cells = <1>;
2120 interrupt-map-mask = <0 0 0 0x7>;
2121 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2134 clock-names = "aux",
2143 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2144 assigned-clock-rates = <19200000>;
2148 interconnect-names = "pcie-mem", "cpu-pcie";
2151 reset-names = "pci";
2153 power-domains = <&gcc PCIE_2B_GDSC>;
2154 required-opps = <&rpmhpd_opp_nom>;
2157 phy-names = "pciephy";
2164 bus-range = <0x01 0xff>;
2166 #address-cells = <3>;
2167 #size-cells = <2>;
2173 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2182 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2185 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2186 assigned-clock-rates = <100000000>;
2188 power-domains = <&gcc PCIE_2B_GDSC>;
2191 reset-names = "phy";
2193 #clock-cells = <0>;
2194 clock-output-names = "pcie_2b_pipe_clk";
2196 #phy-cells = <0>;
2203 compatible = "qcom,pcie-sc8280xp";
2210 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2211 #address-cells = <3>;
2212 #size-cells = <2>;
2215 bus-range = <0x00 0xff>;
2217 dma-coherent;
2219 linux,pci-domain = <2>;
2220 num-lanes = <4>;
2222 msi-map = <0x0 &its 0xa0000 0x10000>;
2228 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2230 #interrupt-cells = <1>;
2231 interrupt-map-mask = <0 0 0 0x7>;
2232 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2245 clock-names = "aux",
2254 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2255 assigned-clock-rates = <19200000>;
2259 interconnect-names = "pcie-mem", "cpu-pcie";
2262 reset-names = "pci";
2264 power-domains = <&gcc PCIE_2A_GDSC>;
2265 required-opps = <&rpmhpd_opp_nom>;
2268 phy-names = "pciephy";
2275 bus-range = <0x01 0xff>;
2277 #address-cells = <3>;
2278 #size-cells = <2>;
2284 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2294 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2297 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2298 assigned-clock-rates = <100000000>;
2300 power-domains = <&gcc PCIE_2A_GDSC>;
2303 reset-names = "phy";
2305 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2307 #clock-cells = <0>;
2308 clock-output-names = "pcie_2a_pipe_clk";
2310 #phy-cells = <0>;
2316 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2317 "jedec,ufs-2.0";
2321 phy-names = "ufsphy";
2322 lanes-per-direction = <2>;
2323 #reset-cells = <1>;
2325 reset-names = "rst";
2327 power-domains = <&gcc UFS_PHY_GDSC>;
2328 required-opps = <&rpmhpd_opp_nom>;
2331 dma-coherent;
2341 clock-names = "core_clk",
2349 freq-table-hz = <75000000 300000000>,
2361 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2367 clock-names = "ref",
2371 power-domains = <&gcc UFS_PHY_GDSC>;
2374 reset-names = "ufsphy";
2376 #phy-cells = <0>;
2382 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2383 "jedec,ufs-2.0";
2387 phy-names = "ufsphy";
2388 lanes-per-direction = <2>;
2389 #reset-cells = <1>;
2391 reset-names = "rst";
2393 power-domains = <&gcc UFS_CARD_GDSC>;
2396 dma-coherent;
2406 clock-names = "core_clk",
2414 freq-table-hz = <75000000 300000000>,
2426 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2432 clock-names = "ref",
2436 power-domains = <&gcc UFS_CARD_GDSC>;
2439 reset-names = "ufsphy";
2441 #phy-cells = <0>;
2447 compatible = "qcom,tcsr-mutex";
2449 #hwlock-cells = <1>;
2453 compatible = "qcom,sc8280xp-tcsr", "syscon";
2458 compatible = "qcom,adreno-690.0", "qcom,adreno";
2463 reg-names = "kgsl_3d0_reg_memory",
2468 operating-points-v2 = <&gpu_opp_table>;
2472 interconnect-names = "gfx-mem";
2473 #cooling-cells = <2>;
2477 gpu_opp_table: opp-table {
2478 compatible = "operating-points-v2";
2480 opp-270000000 {
2481 opp-hz = /bits/ 64 <270000000>;
2482 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2483 opp-peak-kBps = <451000>;
2486 opp-410000000 {
2487 opp-hz = /bits/ 64 <410000000>;
2488 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2489 opp-peak-kBps = <1555000>;
2492 opp-500000000 {
2493 opp-hz = /bits/ 64 <500000000>;
2494 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2495 opp-peak-kBps = <1555000>;
2498 opp-547000000 {
2499 opp-hz = /bits/ 64 <547000000>;
2500 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2501 opp-peak-kBps = <1555000>;
2504 opp-606000000 {
2505 opp-hz = /bits/ 64 <606000000>;
2506 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2507 opp-peak-kBps = <2736000>;
2510 opp-640000000 {
2511 opp-hz = /bits/ 64 <640000000>;
2512 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2513 opp-peak-kBps = <2736000>;
2516 opp-655000000 {
2517 opp-hz = /bits/ 64 <655000000>;
2518 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2519 opp-peak-kBps = <2736000>;
2522 opp-690000000 {
2523 opp-hz = /bits/ 64 <690000000>;
2524 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2525 opp-peak-kBps = <2736000>;
2531 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2535 reg-names = "gmu", "rscc", "gmu_pdc";
2538 interrupt-names = "hfi", "gmu";
2546 clock-names = "gmu",
2553 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2555 power-domain-names = "cx",
2558 operating-points-v2 = <&gmu_opp_table>;
2560 gmu_opp_table: opp-table {
2561 compatible = "operating-points-v2";
2563 opp-200000000 {
2564 opp-hz = /bits/ 64 <200000000>;
2565 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2568 opp-500000000 {
2569 opp-hz = /bits/ 64 <500000000>;
2570 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2575 gpucc: clock-controller@3d90000 {
2576 compatible = "qcom,sc8280xp-gpucc";
2581 clock-names = "bi_tcxo",
2585 power-domains = <&rpmhpd SC8280XP_GFX>;
2586 #clock-cells = <1>;
2587 #reset-cells = <1>;
2588 #power-domain-cells = <1>;
2592 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2593 "qcom,smmu-500", "arm,mmu-500";
2595 #iommu-cells = <2>;
2596 #global-interrupts = <2>;
2619 clock-names = "gcc_gpu_memnoc_gfx_clk",
2627 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2628 dma-coherent;
2632 compatible = "qcom,sc8280xp-usb-hs-phy",
2633 "qcom,usb-snps-hs-5nm-phy";
2636 clock-names = "ref";
2639 #phy-cells = <0>;
2645 compatible = "qcom,sc8280xp-usb-hs-phy",
2646 "qcom,usb-snps-hs-5nm-phy";
2649 clock-names = "ref";
2652 #phy-cells = <0>;
2658 compatible = "qcom,sc8280xp-usb-hs-phy",
2659 "qcom,usb-snps-hs-5nm-phy";
2662 clock-names = "ref";
2665 #phy-cells = <0>;
2671 compatible = "qcom,sc8280xp-usb-hs-phy",
2672 "qcom,usb-snps-hs-5nm-phy";
2675 clock-names = "ref";
2678 #phy-cells = <0>;
2684 compatible = "qcom,sc8280xp-usb-hs-phy",
2685 "qcom,usb-snps-hs-5nm-phy";
2688 clock-names = "ref";
2691 #phy-cells = <0>;
2697 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2704 clock-names = "aux", "ref", "com_aux", "pipe";
2708 reset-names = "phy", "phy_phy";
2710 power-domains = <&gcc USB30_MP_GDSC>;
2712 #clock-cells = <0>;
2713 clock-output-names = "usb2_phy0_pipe_clk";
2715 #phy-cells = <0>;
2721 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2728 clock-names = "aux", "ref", "com_aux", "pipe";
2732 reset-names = "phy", "phy_phy";
2734 power-domains = <&gcc USB30_MP_GDSC>;
2736 #clock-cells = <0>;
2737 clock-output-names = "usb2_phy1_pipe_clk";
2739 #phy-cells = <0>;
2745 compatible = "qcom,sc8280xp-adsp-pas";
2748 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2754 interrupt-names = "wdog", "fatal", "ready",
2755 "handover", "stop-ack", "shutdown-ack";
2758 clock-names = "xo";
2760 power-domains = <&rpmhpd SC8280XP_LCX>,
2762 power-domain-names = "lcx", "lmx";
2764 memory-region = <&pil_adsp_mem>;
2768 qcom,smem-states = <&smp2p_adsp_out 0>;
2769 qcom,smem-state-names = "stop";
2773 remoteproc_adsp_glink: glink-edge {
2774 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2781 qcom,remote-pid = <2>;
2785 qcom,glink-channels = "adsp_apps";
2788 #address-cells = <1>;
2789 #size-cells = <0>;
2794 #sound-dai-cells = <0>;
2795 qcom,protection-domain = "avs/audio",
2798 compatible = "qcom,q6apm-dais";
2803 compatible = "qcom,q6apm-lpass-dais";
2804 #sound-dai-cells = <1>;
2811 qcom,protection-domain = "avs/audio",
2813 q6prmcc: clock-controller {
2814 compatible = "qcom,q6prm-lpass-clocks";
2815 #clock-cells = <2>;
2823 compatible = "qcom,sc8280xp-lpass-rx-macro";
2830 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2831 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2833 assigned-clock-rates = <19200000>, <19200000>;
2835 clock-output-names = "mclk";
2836 #clock-cells = <0>;
2837 #sound-dai-cells = <1>;
2839 pinctrl-names = "default";
2840 pinctrl-0 = <&rx_swr_default>;
2846 compatible = "qcom,soundwire-v1.6.0";
2850 clock-names = "iface";
2852 reset-names = "swr_audio_cgcr";
2855 qcom,din-ports = <0>;
2856 qcom,dout-ports = <5>;
2858 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2859 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2860 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2861 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2862 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2863 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2864 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2865 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2866 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2868 #sound-dai-cells = <1>;
2869 #address-cells = <2>;
2870 #size-cells = <0>;
2876 compatible = "qcom,sc8280xp-lpass-tx-macro";
2878 pinctrl-names = "default";
2879 pinctrl-0 = <&tx_swr_default>;
2886 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2887 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2889 assigned-clock-rates = <19200000>, <19200000>;
2890 clock-output-names = "mclk";
2892 #clock-cells = <0>;
2893 #sound-dai-cells = <1>;
2899 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2906 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2907 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2909 assigned-clock-rates = <19200000>, <19200000>;
2911 #clock-cells = <0>;
2912 clock-output-names = "mclk";
2913 #sound-dai-cells = <1>;
2915 pinctrl-names = "default";
2916 pinctrl-0 = <&wsa_swr_default>;
2923 compatible = "qcom,soundwire-v1.6.0";
2926 clock-names = "iface";
2928 reset-names = "swr_audio_cgcr";
2931 qcom,din-ports = <2>;
2932 qcom,dout-ports = <6>;
2934 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2935 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2936 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2937 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2938 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2939 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2940 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2941 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2942 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2944 #sound-dai-cells = <1>;
2945 #address-cells = <2>;
2946 #size-cells = <0>;
2951 lpass_audiocc: clock-controller@32a9000 {
2952 compatible = "qcom,sc8280xp-lpassaudiocc";
2954 #clock-cells = <1>;
2955 #reset-cells = <1>;
2959 compatible = "qcom,soundwire-v1.6.0";
2963 interrupt-names = "core", "wakeup";
2966 clock-names = "iface";
2968 reset-names = "swr_audio_cgcr";
2970 #sound-dai-cells = <1>;
2971 #address-cells = <2>;
2972 #size-cells = <0>;
2974 qcom,din-ports = <4>;
2975 qcom,dout-ports = <0>;
2976 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2977 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2978 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2979 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2980 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2981 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2982 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2983 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2984 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2990 compatible = "qcom,sc8280xp-lpass-va-macro";
2996 clock-names = "mclk", "macro", "dcodec", "npl";
2997 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2998 assigned-clock-rates = <19200000>;
3000 #clock-cells = <0>;
3001 clock-output-names = "fsgen";
3002 #sound-dai-cells = <1>;
3008 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
3011 gpio-controller;
3012 #gpio-cells = <2>;
3013 gpio-ranges = <&lpass_tlmm 0 0 19>;
3017 clock-names = "core", "audio";
3021 tx_swr_default: tx-swr-default-state {
3022 clk-pins {
3025 drive-strength = <2>;
3026 slew-rate = <1>;
3027 bias-disable;
3030 data-pins {
3033 drive-strength = <2>;
3034 slew-rate = <1>;
3035 bias-bus-hold;
3039 rx_swr_default: rx-swr-default-state {
3040 clk-pins {
3043 drive-strength = <2>;
3044 slew-rate = <1>;
3045 bias-disable;
3048 data-pins {
3051 drive-strength = <2>;
3052 slew-rate = <1>;
3053 bias-bus-hold;
3057 dmic01_default: dmic01-default-state {
3058 clk-pins {
3061 drive-strength = <8>;
3062 output-high;
3065 data-pins {
3068 drive-strength = <8>;
3069 input-enable;
3073 dmic01_sleep: dmic01-sleep-state {
3074 clk-pins {
3077 drive-strength = <2>;
3078 bias-disable;
3079 output-low;
3082 data-pins {
3085 drive-strength = <2>;
3086 bias-pull-down;
3087 input-enable;
3091 dmic23_default: dmic23-default-state {
3092 clk-pins {
3095 drive-strength = <8>;
3096 output-high;
3099 data-pins {
3102 drive-strength = <8>;
3103 input-enable;
3107 dmic23_sleep: dmic23-sleep-state {
3108 clk-pins {
3111 drive-strength = <2>;
3112 bias-disable;
3113 output-low;
3116 data-pins {
3119 drive-strength = <2>;
3120 bias-pull-down;
3121 input-enable;
3125 wsa_swr_default: wsa-swr-default-state {
3126 clk-pins {
3129 drive-strength = <2>;
3130 slew-rate = <1>;
3131 bias-disable;
3134 data-pins {
3137 drive-strength = <2>;
3138 slew-rate = <1>;
3139 bias-bus-hold;
3143 wsa2_swr_default: wsa2-swr-default-state {
3144 clk-pins {
3147 drive-strength = <2>;
3148 slew-rate = <1>;
3149 bias-disable;
3152 data-pins {
3155 drive-strength = <2>;
3156 slew-rate = <1>;
3157 bias-bus-hold;
3162 lpasscc: clock-controller@33e0000 {
3163 compatible = "qcom,sc8280xp-lpasscc";
3165 #clock-cells = <1>;
3166 #reset-cells = <1>;
3170 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3175 interrupt-names = "hc_irq", "pwr_irq";
3180 clock-names = "iface", "core", "xo";
3184 interconnect-names = "sdhc-ddr","cpu-sdhc";
3186 power-domains = <&rpmhpd SC8280XP_CX>;
3187 operating-points-v2 = <&sdc2_opp_table>;
3188 bus-width = <4>;
3189 dma-coherent;
3193 sdc2_opp_table: opp-table {
3194 compatible = "operating-points-v2";
3196 opp-100000000 {
3197 opp-hz = /bits/ 64 <100000000>;
3198 required-opps = <&rpmhpd_opp_low_svs>;
3199 opp-peak-kBps = <1800000 400000>;
3200 opp-avg-kBps = <100000 0>;
3203 opp-202000000 {
3204 opp-hz = /bits/ 64 <202000000>;
3205 required-opps = <&rpmhpd_opp_svs_l1>;
3206 opp-peak-kBps = <5400000 1600000>;
3207 opp-avg-kBps = <200000 0>;
3213 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3220 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3222 power-domains = <&gcc USB30_PRIM_GDSC>;
3226 reset-names = "phy", "common";
3228 #clock-cells = <1>;
3229 #phy-cells = <1>;
3234 #address-cells = <1>;
3235 #size-cells = <0>;
3247 remote-endpoint = <&usb_0_dwc3_ss>;
3260 compatible = "qcom,sc8280xp-usb-hs-phy",
3261 "qcom,usb-snps-hs-5nm-phy";
3263 #phy-cells = <0>;
3266 clock-names = "ref";
3274 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3281 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3283 power-domains = <&gcc USB30_SEC_GDSC>;
3287 reset-names = "phy", "common";
3289 #clock-cells = <1>;
3290 #phy-cells = <1>;
3295 #address-cells = <1>;
3296 #size-cells = <0>;
3308 remote-endpoint = <&usb_1_dwc3_ss>;
3321 compatible = "qcom,sc8280xp-dp-phy";
3329 clock-names = "aux", "cfg_ahb";
3330 power-domains = <&rpmhpd SC8280XP_MX>;
3332 #clock-cells = <1>;
3333 #phy-cells = <0>;
3339 compatible = "qcom,sc8280xp-dp-phy";
3347 clock-names = "aux", "cfg_ahb";
3348 power-domains = <&rpmhpd SC8280XP_MX>;
3350 #clock-cells = <1>;
3351 #phy-cells = <0>;
3357 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3364 operating-points-v2 = <&llcc_bwmon_opp_table>;
3366 llcc_bwmon_opp_table: opp-table {
3367 compatible = "operating-points-v2";
3369 opp-0 {
3370 opp-peak-kBps = <762000>;
3372 opp-1 {
3373 opp-peak-kBps = <1720000>;
3375 opp-2 {
3376 opp-peak-kBps = <2086000>;
3378 opp-3 {
3379 opp-peak-kBps = <2597000>;
3381 opp-4 {
3382 opp-peak-kBps = <2929000>;
3384 opp-5 {
3385 opp-peak-kBps = <3879000>;
3387 opp-6 {
3388 opp-peak-kBps = <5161000>;
3390 opp-7 {
3391 opp-peak-kBps = <5931000>;
3393 opp-8 {
3394 opp-peak-kBps = <6515000>;
3396 opp-9 {
3397 opp-peak-kBps = <7980000>;
3399 opp-10 {
3400 opp-peak-kBps = <8136000>;
3402 opp-11 {
3403 opp-peak-kBps = <10437000>;
3405 opp-12 {
3406 opp-peak-kBps = <12191000>;
3412 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3418 operating-points-v2 = <&cpu_bwmon_opp_table>;
3420 cpu_bwmon_opp_table: opp-table {
3421 compatible = "operating-points-v2";
3423 opp-0 {
3424 opp-peak-kBps = <2288000>;
3426 opp-1 {
3427 opp-peak-kBps = <4577000>;
3429 opp-2 {
3430 opp-peak-kBps = <7110000>;
3432 opp-3 {
3433 opp-peak-kBps = <9155000>;
3435 opp-4 {
3436 opp-peak-kBps = <12298000>;
3438 opp-5 {
3439 opp-peak-kBps = <14236000>;
3441 opp-6 {
3442 opp-peak-kBps = <15258001>;
3447 system-cache-controller@9200000 {
3448 compatible = "qcom,sc8280xp-llcc";
3454 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3461 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
3463 #address-cells = <2>;
3464 #size-cells = <2>;
3476 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3479 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3481 assigned-clock-rates = <19200000>, <200000000>;
3483 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3502 interrupt-names = "pwr_event_1", "pwr_event_2",
3512 power-domains = <&gcc USB30_MP_GDSC>;
3513 required-opps = <&rpmhpd_opp_nom>;
3519 interconnect-names = "usb-ddr", "apps-usb";
3521 wakeup-source;
3534 phy-names = "usb2-0", "usb3-0",
3535 "usb2-1", "usb3-1",
3536 "usb2-2",
3537 "usb2-3";
3539 snps,dis-u1-entry-quirk;
3540 snps,dis-u2-entry-quirk;
3545 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3547 #address-cells = <2>;
3548 #size-cells = <2>;
3560 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3563 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3565 assigned-clock-rates = <19200000>, <200000000>;
3567 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3572 interrupt-names = "pwr_event",
3578 power-domains = <&gcc USB30_PRIM_GDSC>;
3579 required-opps = <&rpmhpd_opp_nom>;
3585 interconnect-names = "usb-ddr", "apps-usb";
3587 wakeup-source;
3597 phy-names = "usb2-phy", "usb3-phy";
3598 snps,dis-u1-entry-quirk;
3599 snps,dis-u2-entry-quirk;
3602 #address-cells = <1>;
3603 #size-cells = <0>;
3616 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
3624 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3626 #address-cells = <2>;
3627 #size-cells = <2>;
3639 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3642 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3644 assigned-clock-rates = <19200000>, <200000000>;
3646 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3651 interrupt-names = "pwr_event",
3657 power-domains = <&gcc USB30_SEC_GDSC>;
3658 required-opps = <&rpmhpd_opp_nom>;
3664 interconnect-names = "usb-ddr", "apps-usb";
3666 wakeup-source;
3676 phy-names = "usb2-phy", "usb3-phy";
3677 snps,dis-u1-entry-quirk;
3678 snps,dis-u2-entry-quirk;
3681 #address-cells = <1>;
3682 #size-cells = <0>;
3695 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3703 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3712 clock-names = "camnoc_axi",
3717 power-domains = <&camcc TITAN_TOP_GDSC>;
3719 pinctrl-0 = <&cci0_default>;
3720 pinctrl-1 = <&cci0_sleep>;
3721 pinctrl-names = "default", "sleep";
3723 #address-cells = <1>;
3724 #size-cells = <0>;
3728 cci0_i2c0: i2c-bus@0 {
3730 clock-frequency = <1000000>;
3731 #address-cells = <1>;
3732 #size-cells = <0>;
3735 cci0_i2c1: i2c-bus@1 {
3737 clock-frequency = <1000000>;
3738 #address-cells = <1>;
3739 #size-cells = <0>;
3744 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3753 clock-names = "camnoc_axi",
3758 power-domains = <&camcc TITAN_TOP_GDSC>;
3760 pinctrl-0 = <&cci1_default>;
3761 pinctrl-1 = <&cci1_sleep>;
3762 pinctrl-names = "default", "sleep";
3764 #address-cells = <1>;
3765 #size-cells = <0>;
3769 cci1_i2c0: i2c-bus@0 {
3771 clock-frequency = <1000000>;
3772 #address-cells = <1>;
3773 #size-cells = <0>;
3776 cci1_i2c1: i2c-bus@1 {
3778 clock-frequency = <1000000>;
3779 #address-cells = <1>;
3780 #size-cells = <0>;
3785 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3794 clock-names = "camnoc_axi",
3798 power-domains = <&camcc TITAN_TOP_GDSC>;
3800 pinctrl-0 = <&cci2_default>;
3801 pinctrl-1 = <&cci2_sleep>;
3802 pinctrl-names = "default", "sleep";
3804 #address-cells = <1>;
3805 #size-cells = <0>;
3809 cci2_i2c0: i2c-bus@0 {
3811 clock-frequency = <1000000>;
3812 #address-cells = <1>;
3813 #size-cells = <0>;
3816 cci2_i2c1: i2c-bus@1 {
3818 clock-frequency = <1000000>;
3819 #address-cells = <1>;
3820 #size-cells = <0>;
3825 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3834 clock-names = "camnoc_axi",
3839 power-domains = <&camcc TITAN_TOP_GDSC>;
3841 pinctrl-0 = <&cci3_default>;
3842 pinctrl-1 = <&cci3_sleep>;
3843 pinctrl-names = "default", "sleep";
3845 #address-cells = <1>;
3846 #size-cells = <0>;
3850 cci3_i2c0: i2c-bus@0 {
3852 clock-frequency = <1000000>;
3853 #address-cells = <1>;
3854 #size-cells = <0>;
3857 cci3_i2c1: i2c-bus@1 {
3859 clock-frequency = <1000000>;
3860 #address-cells = <1>;
3861 #size-cells = <0>;
3866 compatible = "qcom,sc8280xp-camss";
3888 reg-names = "csiphy2",
3929 interrupt-names = "csid1_lite",
3950 power-domains = <&camcc IFE_0_GDSC>,
3955 power-domain-names = "ife0",
4001 clock-names = "camnoc_axi",
4063 interconnect-names = "cam_ahb",
4071 #address-cells = <1>;
4072 #size-cells = <0>;
4076 #address-cells = <1>;
4077 #size-cells = <0>;
4082 #address-cells = <1>;
4083 #size-cells = <0>;
4088 #address-cells = <1>;
4089 #size-cells = <0>;
4094 #address-cells = <1>;
4095 #size-cells = <0>;
4100 camcc: clock-controller@ad00000 {
4101 compatible = "qcom,sc8280xp-camcc";
4107 power-domains = <&rpmhpd SC8280XP_MMCX>;
4108 required-opps = <&rpmhpd_opp_low_svs>;
4109 #clock-cells = <1>;
4110 #reset-cells = <1>;
4111 #power-domain-cells = <1>;
4114 mdss0: display-subsystem@ae00000 {
4115 compatible = "qcom,sc8280xp-mdss";
4117 reg-names = "mdss";
4122 clock-names = "iface",
4128 interconnect-names = "mdp0-mem", "mdp1-mem";
4130 power-domains = <&dispcc0 MDSS_GDSC>;
4133 interrupt-controller;
4134 #interrupt-cells = <1>;
4135 #address-cells = <2>;
4136 #size-cells = <2>;
4141 mdss0_mdp: display-controller@ae01000 {
4142 compatible = "qcom,sc8280xp-dpu";
4145 reg-names = "mdp", "vbif";
4153 clock-names = "bus",
4159 interrupt-parent = <&mdss0>;
4161 power-domains = <&rpmhpd SC8280XP_MMCX>;
4163 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4164 assigned-clock-rates = <19200000>;
4165 operating-points-v2 = <&mdss0_mdp_opp_table>;
4168 #address-cells = <1>;
4169 #size-cells = <0>;
4174 remote-endpoint = <&mdss0_dp0_in>;
4181 remote-endpoint = <&mdss0_dp1_in>;
4188 remote-endpoint = <&mdss0_dp3_in>;
4195 remote-endpoint = <&mdss0_dp2_in>;
4200 mdss0_mdp_opp_table: opp-table {
4201 compatible = "operating-points-v2";
4203 opp-200000000 {
4204 opp-hz = /bits/ 64 <200000000>;
4205 required-opps = <&rpmhpd_opp_low_svs>;
4208 opp-300000000 {
4209 opp-hz = /bits/ 64 <300000000>;
4210 required-opps = <&rpmhpd_opp_svs>;
4213 opp-375000000 {
4214 opp-hz = /bits/ 64 <375000000>;
4215 required-opps = <&rpmhpd_opp_svs_l1>;
4218 opp-500000000 {
4219 opp-hz = /bits/ 64 <500000000>;
4220 required-opps = <&rpmhpd_opp_nom>;
4222 opp-600000000 {
4223 opp-hz = /bits/ 64 <600000000>;
4224 required-opps = <&rpmhpd_opp_turbo_l1>;
4229 mdss0_dp0: displayport-controller@ae90000 {
4230 compatible = "qcom,sc8280xp-dp";
4236 interrupt-parent = <&mdss0>;
4243 clock-names = "core_iface", "core_aux",
4248 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4250 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4254 phy-names = "dp";
4256 #sound-dai-cells = <0>;
4258 operating-points-v2 = <&mdss0_dp0_opp_table>;
4259 power-domains = <&rpmhpd SC8280XP_MMCX>;
4264 #address-cells = <1>;
4265 #size-cells = <0>;
4271 remote-endpoint = <&mdss0_intf0_out>;
4283 mdss0_dp0_opp_table: opp-table {
4284 compatible = "operating-points-v2";
4286 opp-160000000 {
4287 opp-hz = /bits/ 64 <160000000>;
4288 required-opps = <&rpmhpd_opp_low_svs>;
4291 opp-270000000 {
4292 opp-hz = /bits/ 64 <270000000>;
4293 required-opps = <&rpmhpd_opp_svs>;
4296 opp-540000000 {
4297 opp-hz = /bits/ 64 <540000000>;
4298 required-opps = <&rpmhpd_opp_svs_l1>;
4301 opp-810000000 {
4302 opp-hz = /bits/ 64 <810000000>;
4303 required-opps = <&rpmhpd_opp_nom>;
4308 mdss0_dp1: displayport-controller@ae98000 {
4309 compatible = "qcom,sc8280xp-dp";
4315 interrupt-parent = <&mdss0>;
4322 clock-names = "core_iface", "core_aux",
4326 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4328 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4332 phy-names = "dp";
4334 #sound-dai-cells = <0>;
4336 operating-points-v2 = <&mdss0_dp1_opp_table>;
4337 power-domains = <&rpmhpd SC8280XP_MMCX>;
4342 #address-cells = <1>;
4343 #size-cells = <0>;
4349 remote-endpoint = <&mdss0_intf4_out>;
4361 mdss0_dp1_opp_table: opp-table {
4362 compatible = "operating-points-v2";
4364 opp-160000000 {
4365 opp-hz = /bits/ 64 <160000000>;
4366 required-opps = <&rpmhpd_opp_low_svs>;
4369 opp-270000000 {
4370 opp-hz = /bits/ 64 <270000000>;
4371 required-opps = <&rpmhpd_opp_svs>;
4374 opp-540000000 {
4375 opp-hz = /bits/ 64 <540000000>;
4376 required-opps = <&rpmhpd_opp_svs_l1>;
4379 opp-810000000 {
4380 opp-hz = /bits/ 64 <810000000>;
4381 required-opps = <&rpmhpd_opp_nom>;
4386 mdss0_dp2: displayport-controller@ae9a000 {
4387 compatible = "qcom,sc8280xp-dp";
4399 clock-names = "core_iface", "core_aux",
4402 interrupt-parent = <&mdss0>;
4405 phy-names = "dp";
4406 power-domains = <&rpmhpd SC8280XP_MMCX>;
4408 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4410 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4411 operating-points-v2 = <&mdss0_dp2_opp_table>;
4413 #sound-dai-cells = <0>;
4418 #address-cells = <1>;
4419 #size-cells = <0>;
4424 remote-endpoint = <&mdss0_intf6_out>;
4433 mdss0_dp2_opp_table: opp-table {
4434 compatible = "operating-points-v2";
4436 opp-160000000 {
4437 opp-hz = /bits/ 64 <160000000>;
4438 required-opps = <&rpmhpd_opp_low_svs>;
4441 opp-270000000 {
4442 opp-hz = /bits/ 64 <270000000>;
4443 required-opps = <&rpmhpd_opp_svs>;
4446 opp-540000000 {
4447 opp-hz = /bits/ 64 <540000000>;
4448 required-opps = <&rpmhpd_opp_svs_l1>;
4451 opp-810000000 {
4452 opp-hz = /bits/ 64 <810000000>;
4453 required-opps = <&rpmhpd_opp_nom>;
4458 mdss0_dp3: displayport-controller@aea0000 {
4459 compatible = "qcom,sc8280xp-dp";
4471 clock-names = "core_iface", "core_aux",
4474 interrupt-parent = <&mdss0>;
4477 phy-names = "dp";
4478 power-domains = <&rpmhpd SC8280XP_MMCX>;
4480 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4482 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4483 operating-points-v2 = <&mdss0_dp3_opp_table>;
4485 #sound-dai-cells = <0>;
4490 #address-cells = <1>;
4491 #size-cells = <0>;
4496 remote-endpoint = <&mdss0_intf5_out>;
4505 mdss0_dp3_opp_table: opp-table {
4506 compatible = "operating-points-v2";
4508 opp-160000000 {
4509 opp-hz = /bits/ 64 <160000000>;
4510 required-opps = <&rpmhpd_opp_low_svs>;
4513 opp-270000000 {
4514 opp-hz = /bits/ 64 <270000000>;
4515 required-opps = <&rpmhpd_opp_svs>;
4518 opp-540000000 {
4519 opp-hz = /bits/ 64 <540000000>;
4520 required-opps = <&rpmhpd_opp_svs_l1>;
4523 opp-810000000 {
4524 opp-hz = /bits/ 64 <810000000>;
4525 required-opps = <&rpmhpd_opp_nom>;
4532 compatible = "qcom,sc8280xp-dp-phy";
4540 clock-names = "aux", "cfg_ahb";
4541 power-domains = <&rpmhpd SC8280XP_MX>;
4543 #clock-cells = <1>;
4544 #phy-cells = <0>;
4550 compatible = "qcom,sc8280xp-dp-phy";
4558 clock-names = "aux", "cfg_ahb";
4559 power-domains = <&rpmhpd SC8280XP_MX>;
4561 #clock-cells = <1>;
4562 #phy-cells = <0>;
4567 dispcc0: clock-controller@af00000 {
4568 compatible = "qcom,sc8280xp-dispcc0";
4586 power-domains = <&rpmhpd SC8280XP_MMCX>;
4588 #clock-cells = <1>;
4589 #power-domain-cells = <1>;
4590 #reset-cells = <1>;
4595 pdc: interrupt-controller@b220000 {
4596 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4598 qcom,pdc-ranges = <0 480 40>,
4655 #interrupt-cells = <2>;
4656 interrupt-parent = <&intc>;
4657 interrupt-controller;
4660 tsens2: thermal-sensor@c251000 {
4661 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4665 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>,
4667 interrupt-names = "uplow", "critical";
4668 #thermal-sensor-cells = <1>;
4671 tsens3: thermal-sensor@c252000 {
4672 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4676 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>,
4678 interrupt-names = "uplow", "critical";
4679 #thermal-sensor-cells = <1>;
4682 tsens0: thermal-sensor@c263000 {
4683 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4687 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4689 interrupt-names = "uplow", "critical";
4690 #thermal-sensor-cells = <1>;
4700 tsens1: thermal-sensor@c265000 {
4701 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4705 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4707 interrupt-names = "uplow", "critical";
4708 #thermal-sensor-cells = <1>;
4711 aoss_qmp: power-management@c300000 {
4712 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4714 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4717 #clock-cells = <0>;
4721 compatible = "qcom,rpmh-stats";
4727 compatible = "qcom,spmi-pmic-arb";
4733 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4734 interrupt-names = "periph_irq";
4735 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4738 #address-cells = <2>;
4739 #size-cells = <0>;
4740 interrupt-controller;
4741 #interrupt-cells = <4>;
4745 compatible = "qcom,sc8280xp-tlmm";
4748 gpio-controller;
4749 #gpio-cells = <2>;
4750 interrupt-controller;
4751 #interrupt-cells = <2>;
4752 gpio-ranges = <&tlmm 0 0 230>;
4753 wakeup-parent = <&pdc>;
4755 cci0_default: cci0-default-state {
4756 cci0_i2c0_default: cci0-i2c0-default-pins {
4760 drive-strength = <2>;
4761 bias-pull-up;
4764 cci0_i2c1_default: cci0-i2c1-default-pins {
4768 drive-strength = <2>;
4769 bias-pull-up;
4773 cci0_sleep: cci0-sleep-state {
4774 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4778 drive-strength = <2>;
4779 bias-pull-down;
4782 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4786 drive-strength = <2>;
4787 bias-pull-down;
4791 cci1_default: cci1-default-state {
4792 cci1_i2c0_default: cci1-i2c0-default-pins {
4796 drive-strength = <2>;
4797 bias-pull-up;
4800 cci1_i2c1_default: cci1-i2c1-default-pins {
4804 drive-strength = <2>;
4805 bias-pull-up;
4809 cci1_sleep: cci1-sleep-state {
4810 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4814 drive-strength = <2>;
4815 bias-pull-down;
4818 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4822 drive-strength = <2>;
4823 bias-pull-down;
4827 cci2_default: cci2-default-state {
4828 cci2_i2c0_default: cci2-i2c0-default-pins {
4832 drive-strength = <2>;
4833 bias-pull-up;
4836 cci2_i2c1_default: cci2-i2c1-default-pins {
4840 drive-strength = <2>;
4841 bias-pull-up;
4845 cci2_sleep: cci2-sleep-state {
4846 cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
4850 drive-strength = <2>;
4851 bias-pull-down;
4854 cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
4858 drive-strength = <2>;
4859 bias-pull-down;
4863 cci3_default: cci3-default-state {
4864 cci3_i2c0_default: cci3-i2c0-default-pins {
4868 drive-strength = <2>;
4869 bias-pull-up;
4872 cci3_i2c1_default: cci3-i2c1-default-pins {
4876 drive-strength = <2>;
4877 bias-pull-up;
4881 cci3_sleep: cci3-sleep-state {
4882 cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
4886 drive-strength = <2>;
4887 bias-pull-down;
4890 cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
4894 drive-strength = <2>;
4895 bias-pull-down;
4899 qup_uart18_default: qup-uart18-default-state {
4900 cts-pins {
4903 drive-strength = <2>;
4904 bias-disable;
4907 rts-pins {
4910 drive-strength = <2>;
4911 bias-disable;
4914 tx-pins {
4917 drive-strength = <2>;
4918 bias-disable;
4921 rx-pins {
4924 drive-strength = <2>;
4925 bias-disable;
4931 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4933 #iommu-cells = <2>;
4934 #global-interrupts = <2>;
5065 dma-coherent;
5068 intc: interrupt-controller@17a00000 {
5069 compatible = "arm,gic-v3";
5070 interrupt-controller;
5071 #interrupt-cells = <3>;
5075 #redistributor-regions = <1>;
5076 redistributor-stride = <0 0x20000>;
5078 #address-cells = <2>;
5079 #size-cells = <2>;
5082 its: msi-controller@17a40000 {
5083 compatible = "arm,gic-v3-its";
5085 msi-controller;
5086 #msi-cells = <1>;
5091 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5098 compatible = "arm,armv7-timer-mem";
5100 #address-cells = <1>;
5101 #size-cells = <1>;
5105 frame-number = <0>;
5113 frame-number = <1>;
5120 frame-number = <2>;
5127 frame-number = <3>;
5134 frame-number = <4>;
5141 frame-number = <5>;
5148 frame-number = <6>;
5156 compatible = "qcom,rpmh-rsc";
5160 reg-names = "drv-0", "drv-1", "drv-2";
5164 qcom,tcs-offset = <0xd00>;
5165 qcom,drv-id = <2>;
5166 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5169 power-domains = <&cluster_pd>;
5171 apps_bcm_voter: bcm-voter {
5172 compatible = "qcom,bcm-voter";
5175 rpmhcc: clock-controller {
5176 compatible = "qcom,sc8280xp-rpmh-clk";
5177 #clock-cells = <1>;
5178 clock-names = "xo";
5182 rpmhpd: power-controller {
5183 compatible = "qcom,sc8280xp-rpmhpd";
5184 #power-domain-cells = <1>;
5185 operating-points-v2 = <&rpmhpd_opp_table>;
5187 rpmhpd_opp_table: opp-table {
5188 compatible = "operating-points-v2";
5191 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5195 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5199 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5203 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5207 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5211 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5215 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5219 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5223 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5227 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5234 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5238 clock-names = "xo", "alternate";
5240 #interconnect-cells = <1>;
5244 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5247 reg-names = "freq-domain0", "freq-domain1";
5251 interrupt-names = "dcvsh-irq-0",
5252 "dcvsh-irq-1";
5255 clock-names = "xo", "alternate";
5257 #freq-domain-cells = <1>;
5258 #clock-cells = <1>;
5262 compatible = "qcom,sc8280xp-nsp0-pas";
5265 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5270 interrupt-names = "wdog", "fatal", "ready",
5271 "handover", "stop-ack";
5274 clock-names = "xo";
5276 power-domains = <&rpmhpd SC8280XP_NSP>;
5277 power-domain-names = "nsp";
5279 memory-region = <&pil_nsp0_mem>;
5281 qcom,smem-states = <&smp2p_nsp0_out 0>;
5282 qcom,smem-state-names = "stop";
5288 glink-edge {
5289 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5296 qcom,remote-pid = <5>;
5300 qcom,glink-channels = "fastrpcglink-apps-dsp";
5302 #address-cells = <1>;
5303 #size-cells = <0>;
5305 compute-cb@1 {
5306 compatible = "qcom,fastrpc-compute-cb";
5311 compute-cb@2 {
5312 compatible = "qcom,fastrpc-compute-cb";
5317 compute-cb@3 {
5318 compatible = "qcom,fastrpc-compute-cb";
5323 compute-cb@4 {
5324 compatible = "qcom,fastrpc-compute-cb";
5329 compute-cb@5 {
5330 compatible = "qcom,fastrpc-compute-cb";
5335 compute-cb@6 {
5336 compatible = "qcom,fastrpc-compute-cb";
5341 compute-cb@7 {
5342 compatible = "qcom,fastrpc-compute-cb";
5347 compute-cb@8 {
5348 compatible = "qcom,fastrpc-compute-cb";
5353 compute-cb@9 {
5354 compatible = "qcom,fastrpc-compute-cb";
5359 compute-cb@10 {
5360 compatible = "qcom,fastrpc-compute-cb";
5365 compute-cb@11 {
5366 compatible = "qcom,fastrpc-compute-cb";
5371 compute-cb@12 {
5372 compatible = "qcom,fastrpc-compute-cb";
5377 compute-cb@13 {
5378 compatible = "qcom,fastrpc-compute-cb";
5383 compute-cb@14 {
5384 compatible = "qcom,fastrpc-compute-cb";
5393 compatible = "qcom,sc8280xp-nsp1-pas";
5396 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
5401 interrupt-names = "wdog", "fatal", "ready",
5402 "handover", "stop-ack";
5405 clock-names = "xo";
5407 power-domains = <&rpmhpd SC8280XP_NSP>;
5408 power-domain-names = "nsp";
5410 memory-region = <&pil_nsp1_mem>;
5412 qcom,smem-states = <&smp2p_nsp1_out 0>;
5413 qcom,smem-state-names = "stop";
5419 glink-edge {
5420 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5427 qcom,remote-pid = <12>;
5431 mdss1: display-subsystem@22000000 {
5432 compatible = "qcom,sc8280xp-mdss";
5434 reg-names = "mdss";
5439 clock-names = "iface",
5444 interconnect-names = "mdp0-mem", "mdp1-mem";
5448 power-domains = <&dispcc1 MDSS_GDSC>;
5451 interrupt-controller;
5452 #interrupt-cells = <1>;
5453 #address-cells = <2>;
5454 #size-cells = <2>;
5459 mdss1_mdp: display-controller@22001000 {
5460 compatible = "qcom,sc8280xp-dpu";
5463 reg-names = "mdp", "vbif";
5471 clock-names = "bus",
5477 interrupt-parent = <&mdss1>;
5479 power-domains = <&rpmhpd SC8280XP_MMCX>;
5481 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5482 assigned-clock-rates = <19200000>;
5483 operating-points-v2 = <&mdss1_mdp_opp_table>;
5486 #address-cells = <1>;
5487 #size-cells = <0>;
5492 remote-endpoint = <&mdss1_dp0_in>;
5499 remote-endpoint = <&mdss1_dp1_in>;
5506 remote-endpoint = <&mdss1_dp3_in>;
5513 remote-endpoint = <&mdss1_dp2_in>;
5518 mdss1_mdp_opp_table: opp-table {
5519 compatible = "operating-points-v2";
5521 opp-200000000 {
5522 opp-hz = /bits/ 64 <200000000>;
5523 required-opps = <&rpmhpd_opp_low_svs>;
5526 opp-300000000 {
5527 opp-hz = /bits/ 64 <300000000>;
5528 required-opps = <&rpmhpd_opp_svs>;
5531 opp-375000000 {
5532 opp-hz = /bits/ 64 <375000000>;
5533 required-opps = <&rpmhpd_opp_svs_l1>;
5536 opp-500000000 {
5537 opp-hz = /bits/ 64 <500000000>;
5538 required-opps = <&rpmhpd_opp_nom>;
5540 opp-600000000 {
5541 opp-hz = /bits/ 64 <600000000>;
5542 required-opps = <&rpmhpd_opp_turbo_l1>;
5547 mdss1_dp0: displayport-controller@22090000 {
5548 compatible = "qcom,sc8280xp-dp";
5560 clock-names = "core_iface", "core_aux",
5563 interrupt-parent = <&mdss1>;
5566 phy-names = "dp";
5567 power-domains = <&rpmhpd SC8280XP_MMCX>;
5569 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5571 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5572 operating-points-v2 = <&mdss1_dp0_opp_table>;
5574 #sound-dai-cells = <0>;
5579 #address-cells = <1>;
5580 #size-cells = <0>;
5585 remote-endpoint = <&mdss1_intf0_out>;
5594 mdss1_dp0_opp_table: opp-table {
5595 compatible = "operating-points-v2";
5597 opp-160000000 {
5598 opp-hz = /bits/ 64 <160000000>;
5599 required-opps = <&rpmhpd_opp_low_svs>;
5602 opp-270000000 {
5603 opp-hz = /bits/ 64 <270000000>;
5604 required-opps = <&rpmhpd_opp_svs>;
5607 opp-540000000 {
5608 opp-hz = /bits/ 64 <540000000>;
5609 required-opps = <&rpmhpd_opp_svs_l1>;
5612 opp-810000000 {
5613 opp-hz = /bits/ 64 <810000000>;
5614 required-opps = <&rpmhpd_opp_nom>;
5619 mdss1_dp1: displayport-controller@22098000 {
5620 compatible = "qcom,sc8280xp-dp";
5632 clock-names = "core_iface", "core_aux",
5635 interrupt-parent = <&mdss1>;
5638 phy-names = "dp";
5639 power-domains = <&rpmhpd SC8280XP_MMCX>;
5641 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5643 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5644 operating-points-v2 = <&mdss1_dp1_opp_table>;
5646 #sound-dai-cells = <0>;
5651 #address-cells = <1>;
5652 #size-cells = <0>;
5657 remote-endpoint = <&mdss1_intf4_out>;
5666 mdss1_dp1_opp_table: opp-table {
5667 compatible = "operating-points-v2";
5669 opp-160000000 {
5670 opp-hz = /bits/ 64 <160000000>;
5671 required-opps = <&rpmhpd_opp_low_svs>;
5674 opp-270000000 {
5675 opp-hz = /bits/ 64 <270000000>;
5676 required-opps = <&rpmhpd_opp_svs>;
5679 opp-540000000 {
5680 opp-hz = /bits/ 64 <540000000>;
5681 required-opps = <&rpmhpd_opp_svs_l1>;
5684 opp-810000000 {
5685 opp-hz = /bits/ 64 <810000000>;
5686 required-opps = <&rpmhpd_opp_nom>;
5691 mdss1_dp2: displayport-controller@2209a000 {
5692 compatible = "qcom,sc8280xp-dp";
5704 clock-names = "core_iface", "core_aux",
5707 interrupt-parent = <&mdss1>;
5710 phy-names = "dp";
5711 power-domains = <&rpmhpd SC8280XP_MMCX>;
5713 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5715 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5716 operating-points-v2 = <&mdss1_dp2_opp_table>;
5718 #sound-dai-cells = <0>;
5723 #address-cells = <1>;
5724 #size-cells = <0>;
5729 remote-endpoint = <&mdss1_intf6_out>;
5738 mdss1_dp2_opp_table: opp-table {
5739 compatible = "operating-points-v2";
5741 opp-160000000 {
5742 opp-hz = /bits/ 64 <160000000>;
5743 required-opps = <&rpmhpd_opp_low_svs>;
5746 opp-270000000 {
5747 opp-hz = /bits/ 64 <270000000>;
5748 required-opps = <&rpmhpd_opp_svs>;
5751 opp-540000000 {
5752 opp-hz = /bits/ 64 <540000000>;
5753 required-opps = <&rpmhpd_opp_svs_l1>;
5756 opp-810000000 {
5757 opp-hz = /bits/ 64 <810000000>;
5758 required-opps = <&rpmhpd_opp_nom>;
5763 mdss1_dp3: displayport-controller@220a0000 {
5764 compatible = "qcom,sc8280xp-dp";
5776 clock-names = "core_iface", "core_aux",
5779 interrupt-parent = <&mdss1>;
5782 phy-names = "dp";
5783 power-domains = <&rpmhpd SC8280XP_MMCX>;
5785 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5787 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5788 operating-points-v2 = <&mdss1_dp3_opp_table>;
5790 #sound-dai-cells = <0>;
5795 #address-cells = <1>;
5796 #size-cells = <0>;
5801 remote-endpoint = <&mdss1_intf5_out>;
5810 mdss1_dp3_opp_table: opp-table {
5811 compatible = "operating-points-v2";
5813 opp-160000000 {
5814 opp-hz = /bits/ 64 <160000000>;
5815 required-opps = <&rpmhpd_opp_low_svs>;
5818 opp-270000000 {
5819 opp-hz = /bits/ 64 <270000000>;
5820 required-opps = <&rpmhpd_opp_svs>;
5823 opp-540000000 {
5824 opp-hz = /bits/ 64 <540000000>;
5825 required-opps = <&rpmhpd_opp_svs_l1>;
5828 opp-810000000 {
5829 opp-hz = /bits/ 64 <810000000>;
5830 required-opps = <&rpmhpd_opp_nom>;
5837 compatible = "qcom,sc8280xp-dp-phy";
5845 clock-names = "aux", "cfg_ahb";
5846 power-domains = <&rpmhpd SC8280XP_MX>;
5848 #clock-cells = <1>;
5849 #phy-cells = <0>;
5855 compatible = "qcom,sc8280xp-dp-phy";
5863 clock-names = "aux", "cfg_ahb";
5864 power-domains = <&rpmhpd SC8280XP_MX>;
5866 #clock-cells = <1>;
5867 #phy-cells = <0>;
5872 dispcc1: clock-controller@22100000 {
5873 compatible = "qcom,sc8280xp-dispcc1";
5891 power-domains = <&rpmhpd SC8280XP_MMCX>;
5893 #clock-cells = <1>;
5894 #power-domain-cells = <1>;
5895 #reset-cells = <1>;
5901 compatible = "qcom,sc8280xp-ethqos";
5904 reg-names = "stmmaceth", "rgmii";
5910 clock-names = "stmmaceth",
5917 interrupt-names = "macirq", "eth_lpi";
5920 power-domains = <&gcc EMAC_1_GDSC>;
5924 rx-fifo-depth = <4096>;
5925 tx-fifo-depth = <4096>;
5934 thermal-zones {
5935 cpu0-thermal {
5936 polling-delay-passive = <250>;
5938 thermal-sensors = <&tsens0 1>;
5941 cpu-crit {
5949 cpu1-thermal {
5950 polling-delay-passive = <250>;
5952 thermal-sensors = <&tsens0 2>;
5955 cpu-crit {
5963 cpu2-thermal {
5964 polling-delay-passive = <250>;
5966 thermal-sensors = <&tsens0 3>;
5969 cpu-crit {
5977 cpu3-thermal {
5978 polling-delay-passive = <250>;
5980 thermal-sensors = <&tsens0 4>;
5983 cpu-crit {
5991 cpu4-thermal {
5992 polling-delay-passive = <250>;
5994 thermal-sensors = <&tsens0 5>;
5997 cpu-crit {
6005 cpu5-thermal {
6006 polling-delay-passive = <250>;
6008 thermal-sensors = <&tsens0 6>;
6011 cpu-crit {
6019 cpu6-thermal {
6020 polling-delay-passive = <250>;
6022 thermal-sensors = <&tsens0 7>;
6025 cpu-crit {
6033 cpu7-thermal {
6034 polling-delay-passive = <250>;
6036 thermal-sensors = <&tsens0 8>;
6039 cpu-crit {
6047 cluster0-thermal {
6048 polling-delay-passive = <250>;
6050 thermal-sensors = <&tsens0 9>;
6053 cpu-crit {
6061 gpu-thermal {
6062 polling-delay-passive = <250>;
6064 thermal-sensors = <&tsens2 2>;
6066 cooling-maps {
6069 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6074 gpu_alert0: trip-point0 {
6080 trip-point1 {
6088 mem-thermal {
6089 polling-delay-passive = <250>;
6091 thermal-sensors = <&tsens1 15>;
6094 trip-point0 {
6104 compatible = "arm,armv8-timer";