Lines Matching full:mc_virt
310 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
357 mc_virt: interconnect-mc-virt { label
911 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
927 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
943 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
959 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
989 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1005 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1039 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1055 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1071 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1087 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1103 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1119 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1135 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1151 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1167 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1183 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1214 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1246 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1262 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1278 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1294 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1324 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1340 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1356 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1372 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1388 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1404 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1420 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1436 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1452 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1468 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1499 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1515 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1531 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1547 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1563 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1579 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1595 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1611 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1627 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1643 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1659 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1675 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1691 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1707 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1723 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1739 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1810 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1921 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
2032 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2146 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2257 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2471 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3182 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3362 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3517 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
3583 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3662 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
4060 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
4061 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
4062 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
4126 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
4127 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
5284 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5415 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5442 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5443 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;