Lines Matching +full:0 +full:x0c40a000
33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
101 reg = <0x0 0x200>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
124 reg = <0x0 0x300>;
125 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
147 reg = <0x0 0x400>;
170 reg = <0x0 0x500>;
193 reg = <0x0 0x600>;
216 reg = <0x0 0x700>;
275 little_cpu_sleep_0: cpu-sleep-0-0 {
278 arm,psci-suspend-param = <0x40000004>;
285 big_cpu_sleep_0: cpu-sleep-1-0 {
288 arm,psci-suspend-param = <0x40000004>;
297 cluster_sleep_0: cluster-sleep-0 {
299 arm,psci-suspend-param = <0x4100c344>;
310 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
311 qcom,dload-mode = <&tcsr 0x13000>;
390 reg = <0x0 0x80000000 0x0 0x0>;
597 #power-domain-cells = <0>;
603 #power-domain-cells = <0>;
609 #power-domain-cells = <0>;
615 #power-domain-cells = <0>;
621 #power-domain-cells = <0>;
627 #power-domain-cells = <0>;
633 #power-domain-cells = <0>;
639 #power-domain-cells = <0>;
645 #power-domain-cells = <0>;
656 reg = <0 0x80000000 0 0x860000>;
662 reg = <0 0x80860000 0 0x20000>;
667 reg = <0 0x80880000 0 0x80000>;
673 reg = <0 0x80900000 0 0x200000>;
679 reg = <0 0x80b00000 0 0x100000>;
684 reg = <0 0x83b00000 0 0x1700000>;
689 reg = <0 0x85b00000 0 0xc00000>;
694 reg = <0 0x86c00000 0 0x2000000>;
699 reg = <0 0x8a100000 0 0x1e00000>;
704 reg = <0 0x8c600000 0 0x1e00000>;
709 reg = <0 0xaeb00000 0 0x16600000>;
723 qcom,local-pid = <0>;
747 qcom,local-pid = <0>;
771 qcom,local-pid = <0>;
786 soc: soc@0 {
790 ranges = <0 0 0 0 0x10 0>;
791 dma-ranges = <0 0 0 0 0x10 0>;
795 reg = <0x0 0x00020000 0x0 0x10000>,
796 <0x0 0x00036000 0x0 0x100>;
812 iommus = <&apps_smmu 0x4c0 0xf>;
825 reg = <0x0 0x00100000 0x0 0x1f0000>;
831 <0>,
832 <0>,
833 <0>,
834 <0>,
835 <0>,
836 <0>,
838 <0>,
839 <0>,
840 <0>,
841 <0>,
842 <0>,
843 <0>,
844 <0>,
846 <0>,
847 <0>,
848 <0>,
849 <0>,
850 <0>,
851 <0>,
852 <0>,
853 <0>,
854 <0>,
860 <0>,
861 <0>;
867 reg = <0 0x00408000 0 0x1000>;
876 reg = <0 0x00784000 0 0x3000>;
881 reg = <0x18b 0x1>;
888 reg = <0 0x008c0000 0 0x2000>;
892 iommus = <&apps_smmu 0xa3 0>;
902 reg = <0 0x00880000 0 0x4000>;
904 #size-cells = <0>;
909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
910 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
911 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
918 reg = <0 0x00880000 0 0x4000>;
920 #size-cells = <0>;
925 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
927 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
934 reg = <0 0x00884000 0 0x4000>;
936 #size-cells = <0>;
941 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
942 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
943 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
950 reg = <0 0x00884000 0 0x4000>;
952 #size-cells = <0>;
957 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
959 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
966 reg = <0 0x00884000 0 0x4000>;
972 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
980 reg = <0 0x00888000 0 0x4000>;
982 #size-cells = <0>;
987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
989 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
996 reg = <0 0x00888000 0 0x4000>;
998 #size-cells = <0>;
1003 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1005 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1012 reg = <0 0x00888000 0 0x4000>;
1018 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1019 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1022 pinctrl-0 = <&qup_uart18_default>;
1030 reg = <0 0x0088c000 0 0x4000>;
1032 #size-cells = <0>;
1037 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1038 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1039 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1046 reg = <0 0x0088c000 0 0x4000>;
1048 #size-cells = <0>;
1053 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1054 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1055 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1062 reg = <0 0x00890000 0 0x4000>;
1064 #size-cells = <0>;
1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1071 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1078 reg = <0 0x00890000 0 0x4000>;
1080 #size-cells = <0>;
1085 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1086 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1087 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1094 reg = <0 0x00894000 0 0x4000>;
1099 #size-cells = <0>;
1101 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1102 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1103 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1110 reg = <0 0x00894000 0 0x4000>;
1112 #size-cells = <0>;
1117 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1118 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1119 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1126 reg = <0 0x00898000 0 0x4000>;
1128 #size-cells = <0>;
1133 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1134 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1135 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1142 reg = <0 0x00898000 0 0x4000>;
1144 #size-cells = <0>;
1149 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1150 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1151 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1158 reg = <0 0x0089c000 0 0x4000>;
1160 #size-cells = <0>;
1165 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1166 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1167 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1174 reg = <0 0x0089c000 0 0x4000>;
1176 #size-cells = <0>;
1181 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1182 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1183 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1191 reg = <0 0x009c0000 0 0x6000>;
1195 iommus = <&apps_smmu 0x563 0>;
1205 reg = <0 0x00980000 0 0x4000>;
1207 #size-cells = <0>;
1212 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1213 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1214 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1221 reg = <0 0x00980000 0 0x4000>;
1223 #size-cells = <0>;
1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1229 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1230 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1237 reg = <0 0x00984000 0 0x4000>;
1239 #size-cells = <0>;
1244 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1245 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1246 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1253 reg = <0 0x00984000 0 0x4000>;
1255 #size-cells = <0>;
1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1261 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1262 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1269 reg = <0 0x00988000 0 0x4000>;
1271 #size-cells = <0>;
1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1277 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1278 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1285 reg = <0 0x00988000 0 0x4000>;
1287 #size-cells = <0>;
1292 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1293 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1294 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1301 reg = <0 0x00988000 0 0x4000>;
1307 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1308 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1315 reg = <0 0x0098c000 0 0x4000>;
1317 #size-cells = <0>;
1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1323 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1324 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 reg = <0 0x0098c000 0 0x4000>;
1333 #size-cells = <0>;
1338 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1339 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1340 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1347 reg = <0 0x00990000 0 0x4000>;
1352 #size-cells = <0>;
1354 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1355 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1356 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1363 reg = <0 0x00990000 0 0x4000>;
1365 #size-cells = <0>;
1370 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1371 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1372 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1379 reg = <0 0x00994000 0 0x4000>;
1381 #size-cells = <0>;
1386 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1387 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1388 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1395 reg = <0 0x00994000 0 0x4000>;
1397 #size-cells = <0>;
1402 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1403 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1404 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1411 reg = <0 0x00998000 0 0x4000>;
1413 #size-cells = <0>;
1418 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1419 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1420 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1427 reg = <0 0x00998000 0 0x4000>;
1429 #size-cells = <0>;
1434 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1435 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1436 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1443 reg = <0 0x0099c000 0 0x4000>;
1445 #size-cells = <0>;
1450 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1451 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1452 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1459 reg = <0 0x0099c000 0 0x4000>;
1461 #size-cells = <0>;
1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1467 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1468 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1476 reg = <0 0x00ac0000 0 0x6000>;
1480 iommus = <&apps_smmu 0x83 0>;
1490 reg = <0 0x00a80000 0 0x4000>;
1492 #size-cells = <0>;
1497 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1498 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1499 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 reg = <0 0x00a80000 0 0x4000>;
1508 #size-cells = <0>;
1513 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1514 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1515 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1522 reg = <0 0x00a84000 0 0x4000>;
1524 #size-cells = <0>;
1529 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1530 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1531 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1538 reg = <0 0x00a84000 0 0x4000>;
1540 #size-cells = <0>;
1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1546 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1547 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1554 reg = <0 0x00a88000 0 0x4000>;
1556 #size-cells = <0>;
1561 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1562 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1563 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1570 reg = <0 0x00a88000 0 0x4000>;
1572 #size-cells = <0>;
1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1578 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1579 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 reg = <0 0x00a8c000 0 0x4000>;
1588 #size-cells = <0>;
1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1594 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1595 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1602 reg = <0 0x00a8c000 0 0x4000>;
1604 #size-cells = <0>;
1609 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1610 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1611 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1618 reg = <0 0x00a90000 0 0x4000>;
1620 #size-cells = <0>;
1625 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1626 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1627 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1634 reg = <0 0x00a90000 0 0x4000>;
1636 #size-cells = <0>;
1641 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1642 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1643 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1650 reg = <0 0x00a94000 0 0x4000>;
1652 #size-cells = <0>;
1657 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1658 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1659 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 reg = <0 0x00a94000 0 0x4000>;
1668 #size-cells = <0>;
1673 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1674 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1675 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1682 reg = <0 0x00a98000 0 0x4000>;
1684 #size-cells = <0>;
1689 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1690 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1691 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1698 reg = <0 0x00a98000 0 0x4000>;
1700 #size-cells = <0>;
1705 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1706 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1707 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1714 reg = <0 0x00a9c000 0 0x4000>;
1716 #size-cells = <0>;
1721 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1722 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1723 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1730 reg = <0 0x00a9c000 0 0x4000>;
1732 #size-cells = <0>;
1737 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1738 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1739 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1747 reg = <0 0x010d3000 0 0x1000>;
1755 reg = <0x0 0x01c00000 0x0 0x3000>,
1756 <0x0 0x30000000 0x0 0xf1d>,
1757 <0x0 0x30000f20 0x0 0xa8>,
1758 <0x0 0x30001000 0x0 0x1000>,
1759 <0x0 0x30100000 0x0 0x100000>,
1760 <0x0 0x01c03000 0x0 0x1000>;
1764 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1765 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1766 bus-range = <0x00 0xff>;
1773 msi-map = <0x0 &its 0xe0000 0x10000>;
1782 interrupt-map-mask = <0 0 0 0x7>;
1783 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1784 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1785 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1786 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1810 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1811 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1825 pcie4_port0: pcie@0 {
1827 reg = <0x0 0x0 0x0 0x0 0x0>;
1828 bus-range = <0x01 0xff>;
1838 reg = <0x0 0x01c06000 0x0 0x2000>;
1857 #clock-cells = <0>;
1860 #phy-cells = <0>;
1868 reg = <0x0 0x01c08000 0x0 0x3000>,
1869 <0x0 0x32000000 0x0 0xf1d>,
1870 <0x0 0x32000f20 0x0 0xa8>,
1871 <0x0 0x32001000 0x0 0x1000>,
1872 <0x0 0x32100000 0x0 0x100000>,
1873 <0x0 0x01c0b000 0x0 0x1000>;
1877 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1878 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1879 bus-range = <0x00 0xff>;
1886 msi-map = <0x0 &its 0xd0000 0x10000>;
1895 interrupt-map-mask = <0 0 0 0x7>;
1896 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1897 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1898 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1899 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1921 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1922 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1936 pcie3b_port0: pcie@0 {
1938 reg = <0x0 0x0 0x0 0x0 0x0>;
1939 bus-range = <0x01 0xff>;
1949 reg = <0x0 0x01c0e000 0x0 0x2000>;
1968 #clock-cells = <0>;
1971 #phy-cells = <0>;
1979 reg = <0x0 0x01c10000 0x0 0x3000>,
1980 <0x0 0x34000000 0x0 0xf1d>,
1981 <0x0 0x34000f20 0x0 0xa8>,
1982 <0x0 0x34001000 0x0 0x1000>,
1983 <0x0 0x34100000 0x0 0x100000>,
1984 <0x0 0x01c13000 0x0 0x1000>;
1988 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1989 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1990 bus-range = <0x00 0xff>;
1997 msi-map = <0x0 &its 0xc0000 0x10000>;
2006 interrupt-map-mask = <0 0 0 0x7>;
2007 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
2008 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
2009 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
2010 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
2032 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2033 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
2047 pcie3a_port0: pcie@0 {
2049 reg = <0x0 0x0 0x0 0x0 0x0>;
2050 bus-range = <0x01 0xff>;
2060 reg = <0x0 0x01c14000 0x0 0x2000>,
2061 <0x0 0x01c16000 0x0 0x2000>;
2080 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2082 #clock-cells = <0>;
2085 #phy-cells = <0>;
2093 reg = <0x0 0x01c18000 0x0 0x3000>,
2094 <0x0 0x38000000 0x0 0xf1d>,
2095 <0x0 0x38000f20 0x0 0xa8>,
2096 <0x0 0x38001000 0x0 0x1000>,
2097 <0x0 0x38100000 0x0 0x100000>,
2098 <0x0 0x01c1b000 0x0 0x1000>;
2102 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2103 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2104 bus-range = <0x00 0xff>;
2111 msi-map = <0x0 &its 0xb0000 0x10000>;
2120 interrupt-map-mask = <0 0 0 0x7>;
2121 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2122 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2123 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2124 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2146 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2161 pcie2b_port0: pcie@0 {
2163 reg = <0x0 0x0 0x0 0x0 0x0>;
2164 bus-range = <0x01 0xff>;
2174 reg = <0x0 0x01c1e000 0x0 0x2000>;
2193 #clock-cells = <0>;
2196 #phy-cells = <0>;
2204 reg = <0x0 0x01c20000 0x0 0x3000>,
2205 <0x0 0x3c000000 0x0 0xf1d>,
2206 <0x0 0x3c000f20 0x0 0xa8>,
2207 <0x0 0x3c001000 0x0 0x1000>,
2208 <0x0 0x3c100000 0x0 0x100000>,
2209 <0x0 0x01c23000 0x0 0x1000>;
2213 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2214 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2215 bus-range = <0x00 0xff>;
2222 msi-map = <0x0 &its 0xa0000 0x10000>;
2231 interrupt-map-mask = <0 0 0 0x7>;
2232 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2233 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2234 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2235 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2257 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2258 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2272 pcie2a_port0: pcie@0 {
2274 reg = <0x0 0x0 0x0 0x0 0x0>;
2275 bus-range = <0x01 0xff>;
2285 reg = <0x0 0x01c24000 0x0 0x2000>,
2286 <0x0 0x01c26000 0x0 0x2000>;
2305 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2307 #clock-cells = <0>;
2310 #phy-cells = <0>;
2318 reg = <0 0x01d84000 0 0x3000>;
2330 iommus = <&apps_smmu 0xe0 0x0>;
2350 <0 0>,
2351 <0 0>,
2353 <0 0>,
2354 <0 0>,
2355 <0 0>,
2356 <0 0>;
2362 reg = <0 0x01d87000 0 0x1000>;
2373 resets = <&ufs_mem_hc 0>;
2376 #phy-cells = <0>;
2384 reg = <0 0x01da4000 0 0x3000>;
2395 iommus = <&apps_smmu 0x4a0 0x0>;
2415 <0 0>,
2416 <0 0>,
2418 <0 0>,
2419 <0 0>,
2420 <0 0>,
2421 <0 0>;
2427 reg = <0 0x01da7000 0 0x1000>;
2438 resets = <&ufs_card_hc 0>;
2441 #phy-cells = <0>;
2448 reg = <0x0 0x01f40000 0x0 0x20000>;
2454 reg = <0x0 0x01fc0000 0x0 0x30000>;
2460 reg = <0 0x03d00000 0 0x40000>,
2461 <0 0x03d9e000 0 0x1000>,
2462 <0 0x03d61000 0 0x800>;
2467 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2471 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2532 reg = <0 0x03d6a000 0 0x34000>,
2533 <0 0x03de0000 0 0x10000>,
2534 <0 0x0b290000 0 0x10000>;
2557 iommus = <&gpu_smmu 5 0xc00>;
2577 reg = <0 0x03d90000 0 0x9000>;
2594 reg = <0 0x03da0000 0 0x20000>;
2634 reg = <0 0x088e5000 0 0x400>;
2639 #phy-cells = <0>;
2647 reg = <0 0x088e7000 0 0x400>;
2652 #phy-cells = <0>;
2660 reg = <0 0x088e8000 0 0x400>;
2665 #phy-cells = <0>;
2673 reg = <0 0x088e9000 0 0x400>;
2678 #phy-cells = <0>;
2686 reg = <0 0x088ea000 0 0x400>;
2691 #phy-cells = <0>;
2698 reg = <0 0x088ef000 0 0x2000>;
2712 #clock-cells = <0>;
2715 #phy-cells = <0>;
2722 reg = <0 0x088f1000 0 0x2000>;
2736 #clock-cells = <0>;
2739 #phy-cells = <0>;
2746 reg = <0 0x03000000 0 0x10000>;
2749 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2768 qcom,smem-states = <&smp2p_adsp_out 0>;
2789 #size-cells = <0>;
2794 #sound-dai-cells = <0>;
2799 iommus = <&apps_smmu 0x0c01 0x0>;
2824 reg = <0 0x03200000 0 0x1000>;
2836 #clock-cells = <0>;
2840 pinctrl-0 = <&rx_swr_default>;
2847 reg = <0 0x03210000 0 0x2000>;
2855 qcom,din-ports = <0>;
2858 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2859 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2860 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2861 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2862 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2863 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2864 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2865 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2866 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2870 #size-cells = <0>;
2877 reg = <0 0x03220000 0 0x1000>;
2879 pinctrl-0 = <&tx_swr_default>;
2892 #clock-cells = <0>;
2900 reg = <0 0x03240000 0 0x1000>;
2911 #clock-cells = <0>;
2916 pinctrl-0 = <&wsa_swr_default>;
2922 reg = <0 0x03250000 0 0x2000>;
2934 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2935 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2936 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2937 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2938 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2939 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2940 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2941 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2942 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2946 #size-cells = <0>;
2953 reg = <0 0x032a9000 0 0x1000>;
2960 reg = <0 0x03330000 0 0x2000>;
2972 #size-cells = <0>;
2975 qcom,dout-ports = <0>;
2976 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2977 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2978 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2979 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2980 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2981 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2982 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2983 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2984 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2991 reg = <0 0x03370000 0 0x1000>;
3000 #clock-cells = <0>;
3009 reg = <0 0x33c0000 0x0 0x20000>,
3010 <0 0x3550000 0x0 0x10000>;
3013 gpio-ranges = <&lpass_tlmm 0 0 19>;
3164 reg = <0 0x033e0000 0 0x12000>;
3171 reg = <0 0x08804000 0 0x1000>;
3182 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3183 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3185 iommus = <&apps_smmu 0x4e0 0x0>;
3200 opp-avg-kBps = <100000 0>;
3207 opp-avg-kBps = <200000 0>;
3214 reg = <0 0x088eb000 0 0x4000>;
3235 #size-cells = <0>;
3237 port@0 {
3238 reg = <0>;
3262 reg = <0 0x08902000 0 0x400>;
3263 #phy-cells = <0>;
3275 reg = <0 0x08903000 0 0x4000>;
3296 #size-cells = <0>;
3298 port@0 {
3299 reg = <0>;
3322 reg = <0 0x08909a00 0 0x19c>,
3323 <0 0x08909200 0 0xec>,
3324 <0 0x08909600 0 0xec>,
3325 <0 0x08909000 0 0x1c8>;
3333 #phy-cells = <0>;
3340 reg = <0 0x0890ca00 0 0x19c>,
3341 <0 0x0890c200 0 0xec>,
3342 <0 0x0890c600 0 0xec>,
3343 <0 0x0890c000 0 0x1c8>;
3351 #phy-cells = <0>;
3358 reg = <0 0x09091000 0 0x1000>;
3369 opp-0 {
3413 reg = <0 0x090b6400 0 0x600>;
3423 opp-0 {
3449 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3450 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3451 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3452 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3453 <0 0x09600000 0 0x58000>;
3462 reg = <0 0x0a4f8800 0 0x400>;
3517 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
3518 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
3527 reg = <0 0x0a400000 0 0xcd00>;
3529 iommus = <&apps_smmu 0x800 0x0>;
3534 phy-names = "usb2-0", "usb3-0",
3546 reg = <0 0x0a6f8800 0 0x400>;
3583 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3584 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3593 reg = <0 0x0a600000 0 0xcd00>;
3595 iommus = <&apps_smmu 0x820 0x0>;
3603 #size-cells = <0>;
3605 port@0 {
3606 reg = <0>;
3625 reg = <0 0x0a8f8800 0 0x400>;
3662 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3663 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3672 reg = <0 0x0a800000 0 0xcd00>;
3674 iommus = <&apps_smmu 0x860 0x0>;
3682 #size-cells = <0>;
3684 port@0 {
3685 reg = <0>;
3704 reg = <0 0x0ac4a000 0 0x1000>;
3719 pinctrl-0 = <&cci0_default>;
3724 #size-cells = <0>;
3728 cci0_i2c0: i2c-bus@0 {
3729 reg = <0>;
3732 #size-cells = <0>;
3739 #size-cells = <0>;
3745 reg = <0 0x0ac4b000 0 0x1000>;
3760 pinctrl-0 = <&cci1_default>;
3765 #size-cells = <0>;
3769 cci1_i2c0: i2c-bus@0 {
3770 reg = <0>;
3773 #size-cells = <0>;
3780 #size-cells = <0>;
3786 reg = <0 0x0ac4c000 0 0x1000>;
3800 pinctrl-0 = <&cci2_default>;
3805 #size-cells = <0>;
3809 cci2_i2c0: i2c-bus@0 {
3810 reg = <0>;
3813 #size-cells = <0>;
3820 #size-cells = <0>;
3826 reg = <0 0x0ac4d000 0 0x1000>;
3841 pinctrl-0 = <&cci3_default>;
3846 #size-cells = <0>;
3850 cci3_i2c0: i2c-bus@0 {
3851 reg = <0>;
3854 #size-cells = <0>;
3861 #size-cells = <0>;
3868 reg = <0 0x0ac5a000 0 0x2000>,
3869 <0 0x0ac5c000 0 0x2000>,
3870 <0 0x0ac65000 0 0x2000>,
3871 <0 0x0ac67000 0 0x2000>,
3872 <0 0x0acaf000 0 0x4000>,
3873 <0 0x0acb3000 0 0x1000>,
3874 <0 0x0acb6000 0 0x4000>,
3875 <0 0x0acba000 0 0x1000>,
3876 <0 0x0acbd000 0 0x4000>,
3877 <0 0x0acc1000 0 0x1000>,
3878 <0 0x0acc4000 0 0x4000>,
3879 <0 0x0acc8000 0 0x1000>,
3880 <0 0x0accb000 0 0x4000>,
3881 <0 0x0accf000 0 0x1000>,
3882 <0 0x0acd2000 0 0x4000>,
3883 <0 0x0acd6000 0 0x1000>,
3884 <0 0x0acd9000 0 0x4000>,
3885 <0 0x0acdd000 0 0x1000>,
3886 <0 0x0ace0000 0 0x4000>,
3887 <0 0x0ace4000 0 0x1000>;
4042 iommus = <&apps_smmu 0x2000 0x4e0>,
4043 <&apps_smmu 0x2020 0x4e0>,
4044 <&apps_smmu 0x2040 0x4e0>,
4045 <&apps_smmu 0x2060 0x4e0>,
4046 <&apps_smmu 0x2080 0x4e0>,
4047 <&apps_smmu 0x20e0 0x4e0>,
4048 <&apps_smmu 0x20c0 0x4e0>,
4049 <&apps_smmu 0x20a0 0x4e0>,
4050 <&apps_smmu 0x2400 0x4e0>,
4051 <&apps_smmu 0x2420 0x4e0>,
4052 <&apps_smmu 0x2440 0x4e0>,
4053 <&apps_smmu 0x2460 0x4e0>,
4054 <&apps_smmu 0x2480 0x4e0>,
4055 <&apps_smmu 0x24e0 0x4e0>,
4056 <&apps_smmu 0x24c0 0x4e0>,
4057 <&apps_smmu 0x24a0 0x4e0>;
4059 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
4060 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
4061 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
4062 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
4072 #size-cells = <0>;
4074 port@0 {
4075 reg = <0>;
4077 #size-cells = <0>;
4083 #size-cells = <0>;
4089 #size-cells = <0>;
4095 #size-cells = <0>;
4102 reg = <0 0x0ad00000 0 0x20000>;
4116 reg = <0 0x0ae00000 0 0x1000>;
4126 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
4127 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
4129 iommus = <&apps_smmu 0x1000 0x402>;
4143 reg = <0 0x0ae01000 0 0x8f000>,
4144 <0 0x0aeb0000 0 0x2008>;
4160 interrupts = <0>;
4169 #size-cells = <0>;
4171 port@0 {
4172 reg = <0>;
4231 reg = <0 0xae90000 0 0x200>,
4232 <0 0xae90200 0 0x200>,
4233 <0 0xae90400 0 0x600>,
4234 <0 0xae91000 0 0x400>,
4235 <0 0xae91400 0 0x400>;
4256 #sound-dai-cells = <0>;
4265 #size-cells = <0>;
4267 port@0 {
4268 reg = <0>;
4310 reg = <0 0xae98000 0 0x200>,
4311 <0 0xae98200 0 0x200>,
4312 <0 0xae98400 0 0x600>,
4313 <0 0xae99000 0 0x400>,
4314 <0 0xae99400 0 0x400>;
4334 #sound-dai-cells = <0>;
4343 #size-cells = <0>;
4345 port@0 {
4346 reg = <0>;
4388 reg = <0 0xae9a000 0 0x200>,
4389 <0 0xae9a200 0 0x200>,
4390 <0 0xae9a400 0 0x600>,
4391 <0 0xae9b000 0 0x400>,
4392 <0 0xae9b400 0 0x400>;
4410 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4413 #sound-dai-cells = <0>;
4419 #size-cells = <0>;
4421 port@0 {
4422 reg = <0>;
4460 reg = <0 0xaea0000 0 0x200>,
4461 <0 0xaea0200 0 0x200>,
4462 <0 0xaea0400 0 0x600>,
4463 <0 0xaea1000 0 0x400>,
4464 <0 0xaea1400 0 0x400>;
4482 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4485 #sound-dai-cells = <0>;
4491 #size-cells = <0>;
4493 port@0 {
4494 reg = <0>;
4533 reg = <0 0x0aec2a00 0 0x19c>,
4534 <0 0x0aec2200 0 0xec>,
4535 <0 0x0aec2600 0 0xec>,
4536 <0 0x0aec2000 0 0x1c8>;
4544 #phy-cells = <0>;
4551 reg = <0 0x0aec5a00 0 0x19c>,
4552 <0 0x0aec5200 0 0xec>,
4553 <0 0x0aec5600 0 0xec>,
4554 <0 0x0aec5000 0 0x1c8>;
4562 #phy-cells = <0>;
4569 reg = <0 0x0af00000 0 0x20000>;
4578 <&mdss0_dp2_phy 0>,
4580 <&mdss0_dp3_phy 0>,
4582 <0>,
4583 <0>,
4584 <0>,
4585 <0>;
4597 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4598 qcom,pdc-ranges = <0 480 40>,
4662 reg = <0 0x0c251000 0 0x1ff>,
4663 <0 0x0c224000 0 0x8>;
4673 reg = <0 0x0c252000 0 0x1ff>,
4674 <0 0x0c225000 0 0x8>;
4684 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4685 <0 0x0c222000 0 0x8>; /* SROT */
4695 reg = <0 0x0c264000 0 0x4>;
4702 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4703 <0 0x0c223000 0 0x8>; /* SROT */
4713 reg = <0 0x0c300000 0 0x400>;
4717 #clock-cells = <0>;
4722 reg = <0 0x0c3f0000 0 0x400>;
4728 reg = <0 0x0c440000 0 0x1100>,
4729 <0 0x0c600000 0 0x2000000>,
4730 <0 0x0e600000 0 0x100000>,
4731 <0 0x0e700000 0 0xa0000>,
4732 <0 0x0c40a000 0 0x26000>;
4736 qcom,ee = <0>;
4737 qcom,channel = <0>;
4739 #size-cells = <0>;
4746 reg = <0 0x0f100000 0 0x300000>;
4752 gpio-ranges = <&tlmm 0 0 230>;
4932 reg = <0 0x15000000 0 0x100000>;
5072 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5073 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5076 redistributor-stride = <0 0x20000>;
5084 reg = <0 0x17a40000 0 0x20000>;
5092 reg = <0 0x17c10000 0 0x1000>;
5094 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5099 reg = <0x0 0x17c20000 0x0 0x1000>;
5102 ranges = <0x0 0x0 0x0 0x20000000>;
5105 frame-number = <0>;
5108 reg = <0x17c21000 0x1000>,
5109 <0x17c22000 0x1000>;
5115 reg = <0x17c23000 0x1000>;
5122 reg = <0x17c25000 0x1000>;
5129 reg = <0x17c26000 0x1000>;
5136 reg = <0x17c29000 0x1000>;
5143 reg = <0x17c2b000 0x1000>;
5150 reg = <0x17c2d000 0x1000>;
5157 reg = <0x0 0x18200000 0x0 0x10000>,
5158 <0x0 0x18210000 0x0 0x10000>,
5159 <0x0 0x18220000 0x0 0x10000>;
5160 reg-names = "drv-0", "drv-1", "drv-2";
5164 qcom,tcs-offset = <0xd00>;
5235 reg = <0 0x18590000 0 0x1000>;
5245 reg = <0 0x18591000 0 0x1000>,
5246 <0 0x18592000 0 0x1000>;
5251 interrupt-names = "dcvsh-irq-0",
5263 reg = <0 0x1b300000 0 0x10000>;
5266 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
5281 qcom,smem-states = <&smp2p_nsp0_out 0>;
5284 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5303 #size-cells = <0>;
5308 iommus = <&apps_smmu 0x3181 0x0420>;
5314 iommus = <&apps_smmu 0x3182 0x0420>;
5320 iommus = <&apps_smmu 0x3183 0x0420>;
5326 iommus = <&apps_smmu 0x3184 0x0420>;
5332 iommus = <&apps_smmu 0x3185 0x0420>;
5338 iommus = <&apps_smmu 0x3186 0x0420>;
5344 iommus = <&apps_smmu 0x3187 0x0420>;
5350 iommus = <&apps_smmu 0x3188 0x0420>;
5356 iommus = <&apps_smmu 0x318b 0x0420>;
5362 iommus = <&apps_smmu 0x318b 0x0420>;
5368 iommus = <&apps_smmu 0x318c 0x0420>;
5374 iommus = <&apps_smmu 0x318d 0x0420>;
5380 iommus = <&apps_smmu 0x318e 0x0420>;
5386 iommus = <&apps_smmu 0x318f 0x0420>;
5394 reg = <0 0x21300000 0 0x10000>;
5397 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5412 qcom,smem-states = <&smp2p_nsp1_out 0>;
5415 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5433 reg = <0 0x22000000 0 0x1000>;
5442 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5443 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
5447 iommus = <&apps_smmu 0x1800 0x402>;
5461 reg = <0 0x22001000 0 0x8f000>,
5462 <0 0x220b0000 0 0x2008>;
5478 interrupts = <0>;
5487 #size-cells = <0>;
5489 port@0 {
5490 reg = <0>;
5549 reg = <0 0x22090000 0 0x200>,
5550 <0 0x22090200 0 0x200>,
5551 <0 0x22090400 0 0x600>,
5552 <0 0x22091000 0 0x400>,
5553 <0 0x22091400 0 0x400>;
5571 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5574 #sound-dai-cells = <0>;
5580 #size-cells = <0>;
5582 port@0 {
5583 reg = <0>;
5621 reg = <0 0x22098000 0 0x200>,
5622 <0 0x22098200 0 0x200>,
5623 <0 0x22098400 0 0x600>,
5624 <0 0x22099000 0 0x400>,
5625 <0 0x22099400 0 0x400>;
5643 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5646 #sound-dai-cells = <0>;
5652 #size-cells = <0>;
5654 port@0 {
5655 reg = <0>;
5693 reg = <0 0x2209a000 0 0x200>,
5694 <0 0x2209a200 0 0x200>,
5695 <0 0x2209a400 0 0x600>,
5696 <0 0x2209b000 0 0x400>,
5697 <0 0x2209b400 0 0x400>;
5715 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5718 #sound-dai-cells = <0>;
5724 #size-cells = <0>;
5726 port@0 {
5727 reg = <0>;
5765 reg = <0 0x220a0000 0 0x200>,
5766 <0 0x220a0200 0 0x200>,
5767 <0 0x220a0400 0 0x600>,
5768 <0 0x220a1000 0 0x400>,
5769 <0 0x220a1400 0 0x400>;
5787 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5790 #sound-dai-cells = <0>;
5796 #size-cells = <0>;
5798 port@0 {
5799 reg = <0>;
5838 reg = <0 0x220c2a00 0 0x19c>,
5839 <0 0x220c2200 0 0xec>,
5840 <0 0x220c2600 0 0xec>,
5841 <0 0x220c2000 0 0x1c8>;
5849 #phy-cells = <0>;
5856 reg = <0 0x220c5a00 0 0x19c>,
5857 <0 0x220c5200 0 0xec>,
5858 <0 0x220c5600 0 0xec>,
5859 <0 0x220c5000 0 0x1c8>;
5867 #phy-cells = <0>;
5874 reg = <0 0x22100000 0 0x20000>;
5878 <0>,
5879 <&mdss1_dp0_phy 0>,
5881 <&mdss1_dp1_phy 0>,
5883 <&mdss1_dp2_phy 0>,
5885 <&mdss1_dp3_phy 0>,
5887 <0>,
5888 <0>,
5889 <0>,
5890 <0>;
5902 reg = <0x0 0x23000000 0x0 0x10000>,
5903 <0x0 0x23016000 0x0 0x100>;
5919 iommus = <&apps_smmu 0x40 0xf>;