Lines Matching +full:spi +full:- +full:qup +full:- +full:v2
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8180x.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/phy/phy-qcom-qmp.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #include <dt-bindings/thermal/thermal.h>
21 interrupt-parent = <&intc>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 xo_board_clk: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <38400000>;
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32764>;
37 clock-output-names = "sleep_clk";
42 #address-cells = <2>;
43 #size-cells = <0>;
49 enable-method = "psci";
50 capacity-dmips-mhz = <602>;
51 next-level-cache = <&l2_0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
53 operating-points-v2 = <&cpu0_opp_table>;
56 power-domains = <&cpu_pd0>;
57 power-domain-names = "psci";
58 #cooling-cells = <2>;
61 l2_0: l2-cache {
63 cache-level = <2>;
64 cache-unified;
65 next-level-cache = <&l3_0>;
66 l3_0: l3-cache {
68 cache-level = <3>;
69 cache-unified;
78 enable-method = "psci";
79 capacity-dmips-mhz = <602>;
80 next-level-cache = <&l2_100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
82 operating-points-v2 = <&cpu0_opp_table>;
85 power-domains = <&cpu_pd1>;
86 power-domain-names = "psci";
87 #cooling-cells = <2>;
90 l2_100: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&l3_0>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <602>;
105 next-level-cache = <&l2_200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 operating-points-v2 = <&cpu0_opp_table>;
110 power-domains = <&cpu_pd2>;
111 power-domain-names = "psci";
112 #cooling-cells = <2>;
115 l2_200: l2-cache {
117 cache-level = <2>;
118 cache-unified;
119 next-level-cache = <&l3_0>;
127 enable-method = "psci";
128 capacity-dmips-mhz = <602>;
129 next-level-cache = <&l2_300>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 operating-points-v2 = <&cpu0_opp_table>;
134 power-domains = <&cpu_pd3>;
135 power-domain-names = "psci";
136 #cooling-cells = <2>;
139 l2_300: l2-cache {
141 cache-unified;
142 cache-level = <2>;
143 next-level-cache = <&l3_0>;
151 enable-method = "psci";
152 capacity-dmips-mhz = <1024>;
153 next-level-cache = <&l2_400>;
154 qcom,freq-domain = <&cpufreq_hw 1>;
155 operating-points-v2 = <&cpu4_opp_table>;
158 power-domains = <&cpu_pd4>;
159 power-domain-names = "psci";
160 #cooling-cells = <2>;
163 l2_400: l2-cache {
165 cache-unified;
166 cache-level = <2>;
167 next-level-cache = <&l3_0>;
175 enable-method = "psci";
176 capacity-dmips-mhz = <1024>;
177 next-level-cache = <&l2_500>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu4_opp_table>;
182 power-domains = <&cpu_pd5>;
183 power-domain-names = "psci";
184 #cooling-cells = <2>;
187 l2_500: l2-cache {
189 cache-unified;
190 cache-level = <2>;
191 next-level-cache = <&l3_0>;
199 enable-method = "psci";
200 capacity-dmips-mhz = <1024>;
201 next-level-cache = <&l2_600>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 operating-points-v2 = <&cpu4_opp_table>;
206 power-domains = <&cpu_pd6>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
211 l2_600: l2-cache {
213 cache-unified;
214 cache-level = <2>;
215 next-level-cache = <&l3_0>;
223 enable-method = "psci";
224 capacity-dmips-mhz = <1024>;
225 next-level-cache = <&l2_700>;
226 qcom,freq-domain = <&cpufreq_hw 1>;
227 operating-points-v2 = <&cpu4_opp_table>;
230 power-domains = <&cpu_pd7>;
231 power-domain-names = "psci";
232 #cooling-cells = <2>;
235 l2_700: l2-cache {
237 cache-unified;
238 cache-level = <2>;
239 next-level-cache = <&l3_0>;
243 cpu-map {
279 idle-states {
280 entry-method = "psci";
282 little_cpu_sleep_0: cpu-sleep-0-0 {
283 compatible = "arm,idle-state";
284 arm,psci-suspend-param = <0x40000004>;
285 entry-latency-us = <355>;
286 exit-latency-us = <909>;
287 min-residency-us = <3934>;
288 local-timer-stop;
291 big_cpu_sleep_0: cpu-sleep-1-0 {
292 compatible = "arm,idle-state";
293 arm,psci-suspend-param = <0x40000004>;
294 entry-latency-us = <2411>;
295 exit-latency-us = <1461>;
296 min-residency-us = <4488>;
297 local-timer-stop;
301 domain-idle-states {
302 cluster_sleep_apss_off: cluster-sleep-0 {
303 compatible = "domain-idle-state";
304 arm,psci-suspend-param = <0x41000044>;
305 entry-latency-us = <3300>;
306 exit-latency-us = <3300>;
307 min-residency-us = <6000>;
310 cluster_sleep_aoss_sleep: cluster-sleep-1 {
311 compatible = "domain-idle-state";
312 arm,psci-suspend-param = <0x4100a344>;
313 entry-latency-us = <3263>;
314 exit-latency-us = <6562>;
315 min-residency-us = <9987>;
320 cpu0_opp_table: opp-table-cpu0 {
321 compatible = "operating-points-v2";
322 opp-shared;
324 opp-300000000 {
325 opp-hz = /bits/ 64 <300000000>;
326 opp-peak-kBps = <800000 9600000>;
329 opp-422400000 {
330 opp-hz = /bits/ 64 <422400000>;
331 opp-peak-kBps = <800000 9600000>;
334 opp-537600000 {
335 opp-hz = /bits/ 64 <537600000>;
336 opp-peak-kBps = <800000 12902400>;
339 opp-652800000 {
340 opp-hz = /bits/ 64 <652800000>;
341 opp-peak-kBps = <800000 12902400>;
344 opp-768000000 {
345 opp-hz = /bits/ 64 <768000000>;
346 opp-peak-kBps = <800000 15974400>;
349 opp-883200000 {
350 opp-hz = /bits/ 64 <883200000>;
351 opp-peak-kBps = <1804000 19660800>;
354 opp-998400000 {
355 opp-hz = /bits/ 64 <998400000>;
356 opp-peak-kBps = <1804000 19660800>;
359 opp-1113600000 {
360 opp-hz = /bits/ 64 <1113600000>;
361 opp-peak-kBps = <1804000 22732800>;
364 opp-1228800000 {
365 opp-hz = /bits/ 64 <1228800000>;
366 opp-peak-kBps = <1804000 22732800>;
369 opp-1363200000 {
370 opp-hz = /bits/ 64 <1363200000>;
371 opp-peak-kBps = <2188000 25804800>;
374 opp-1478400000 {
375 opp-hz = /bits/ 64 <1478400000>;
376 opp-peak-kBps = <2188000 31948800>;
379 opp-1574400000 {
380 opp-hz = /bits/ 64 <1574400000>;
381 opp-peak-kBps = <3072000 31948800>;
384 opp-1670400000 {
385 opp-hz = /bits/ 64 <1670400000>;
386 opp-peak-kBps = <3072000 31948800>;
389 opp-1766400000 {
390 opp-hz = /bits/ 64 <1766400000>;
391 opp-peak-kBps = <3072000 31948800>;
395 cpu4_opp_table: opp-table-cpu4 {
396 compatible = "operating-points-v2";
397 opp-shared;
399 opp-825600000 {
400 opp-hz = /bits/ 64 <825600000>;
401 opp-peak-kBps = <1804000 15974400>;
404 opp-940800000 {
405 opp-hz = /bits/ 64 <940800000>;
406 opp-peak-kBps = <2188000 19660800>;
409 opp-1056000000 {
410 opp-hz = /bits/ 64 <1056000000>;
411 opp-peak-kBps = <2188000 22732800>;
414 opp-1171200000 {
415 opp-hz = /bits/ 64 <1171200000>;
416 opp-peak-kBps = <3072000 25804800>;
419 opp-1286400000 {
420 opp-hz = /bits/ 64 <1286400000>;
421 opp-peak-kBps = <3072000 31948800>;
424 opp-1420800000 {
425 opp-hz = /bits/ 64 <1420800000>;
426 opp-peak-kBps = <4068000 31948800>;
429 opp-1536000000 {
430 opp-hz = /bits/ 64 <1536000000>;
431 opp-peak-kBps = <4068000 31948800>;
434 opp-1651200000 {
435 opp-hz = /bits/ 64 <1651200000>;
436 opp-peak-kBps = <4068000 40550400>;
439 opp-1766400000 {
440 opp-hz = /bits/ 64 <1766400000>;
441 opp-peak-kBps = <4068000 40550400>;
444 opp-1881600000 {
445 opp-hz = /bits/ 64 <1881600000>;
446 opp-peak-kBps = <4068000 43008000>;
449 opp-1996800000 {
450 opp-hz = /bits/ 64 <1996800000>;
451 opp-peak-kBps = <6220000 43008000>;
454 opp-2131200000 {
455 opp-hz = /bits/ 64 <2131200000>;
456 opp-peak-kBps = <6220000 49152000>;
459 opp-2246400000 {
460 opp-hz = /bits/ 64 <2246400000>;
461 opp-peak-kBps = <7216000 49152000>;
464 opp-2361600000 {
465 opp-hz = /bits/ 64 <2361600000>;
466 opp-peak-kBps = <8368000 49152000>;
469 opp-2457600000 {
470 opp-hz = /bits/ 64 <2457600000>;
471 opp-peak-kBps = <8368000 51609600>;
474 opp-2553600000 {
475 opp-hz = /bits/ 64 <2553600000>;
476 opp-peak-kBps = <8368000 51609600>;
479 opp-2649600000 {
480 opp-hz = /bits/ 64 <2649600000>;
481 opp-peak-kBps = <8368000 51609600>;
484 opp-2745600000 {
485 opp-hz = /bits/ 64 <2745600000>;
486 opp-peak-kBps = <8368000 51609600>;
489 opp-2841600000 {
490 opp-hz = /bits/ 64 <2841600000>;
491 opp-peak-kBps = <8368000 51609600>;
494 opp-2918400000 {
495 opp-hz = /bits/ 64 <2918400000>;
496 opp-peak-kBps = <8368000 51609600>;
499 opp-2995200000 {
500 opp-hz = /bits/ 64 <2995200000>;
501 opp-peak-kBps = <8368000 51609600>;
507 compatible = "qcom,scm-sc8180x", "qcom,scm";
511 camnoc_virt: interconnect-camnoc-virt {
512 compatible = "qcom,sc8180x-camnoc-virt";
513 #interconnect-cells = <2>;
514 qcom,bcm-voters = <&apps_bcm_voter>;
517 mc_virt: interconnect-mc-virt {
518 compatible = "qcom,sc8180x-mc-virt";
519 #interconnect-cells = <2>;
520 qcom,bcm-voters = <&apps_bcm_voter>;
523 qup_virt: interconnect-qup-virt {
524 compatible = "qcom,sc8180x-qup-virt";
525 #interconnect-cells = <2>;
526 qcom,bcm-voters = <&apps_bcm_voter>;
536 compatible = "arm,armv8-pmuv3";
541 compatible = "arm,psci-1.0";
544 cpu_pd0: power-domain-cpu0 {
545 #power-domain-cells = <0>;
546 power-domains = <&cluster_pd>;
547 domain-idle-states = <&little_cpu_sleep_0>;
550 cpu_pd1: power-domain-cpu1 {
551 #power-domain-cells = <0>;
552 power-domains = <&cluster_pd>;
553 domain-idle-states = <&little_cpu_sleep_0>;
556 cpu_pd2: power-domain-cpu2 {
557 #power-domain-cells = <0>;
558 power-domains = <&cluster_pd>;
559 domain-idle-states = <&little_cpu_sleep_0>;
562 cpu_pd3: power-domain-cpu3 {
563 #power-domain-cells = <0>;
564 power-domains = <&cluster_pd>;
565 domain-idle-states = <&little_cpu_sleep_0>;
568 cpu_pd4: power-domain-cpu4 {
569 #power-domain-cells = <0>;
570 power-domains = <&cluster_pd>;
571 domain-idle-states = <&big_cpu_sleep_0>;
574 cpu_pd5: power-domain-cpu5 {
575 #power-domain-cells = <0>;
576 power-domains = <&cluster_pd>;
577 domain-idle-states = <&big_cpu_sleep_0>;
580 cpu_pd6: power-domain-cpu6 {
581 #power-domain-cells = <0>;
582 power-domains = <&cluster_pd>;
583 domain-idle-states = <&big_cpu_sleep_0>;
586 cpu_pd7: power-domain-cpu7 {
587 #power-domain-cells = <0>;
588 power-domains = <&cluster_pd>;
589 domain-idle-states = <&big_cpu_sleep_0>;
592 cluster_pd: power-domain-cpu-cluster0 {
593 #power-domain-cells = <0>;
594 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
598 reserved-memory {
599 #address-cells = <2>;
600 #size-cells = <2>;
605 no-map;
610 no-map;
615 no-map;
618 aop_cmd_db: cmd-db@85f20000 {
619 compatible = "qcom,cmd-db";
621 no-map;
626 no-map;
632 no-map;
638 no-map;
643 no-map;
648 no-map;
653 no-map;
658 no-map;
662 smp2p-cdsp {
670 qcom,local-pid = <0>;
671 qcom,remote-pid = <5>;
673 cdsp_smp2p_out: master-kernel {
674 qcom,entry-name = "master-kernel";
675 #qcom,smem-state-cells = <1>;
678 cdsp_smp2p_in: slave-kernel {
679 qcom,entry-name = "slave-kernel";
681 interrupt-controller;
682 #interrupt-cells = <2>;
686 smp2p-lpass {
694 qcom,local-pid = <0>;
695 qcom,remote-pid = <2>;
697 adsp_smp2p_out: master-kernel {
698 qcom,entry-name = "master-kernel";
699 #qcom,smem-state-cells = <1>;
702 adsp_smp2p_in: slave-kernel {
703 qcom,entry-name = "slave-kernel";
705 interrupt-controller;
706 #interrupt-cells = <2>;
710 smp2p-mpss {
718 qcom,local-pid = <0>;
719 qcom,remote-pid = <1>;
721 modem_smp2p_out: master-kernel {
722 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells = <1>;
726 modem_smp2p_in: slave-kernel {
727 qcom,entry-name = "slave-kernel";
729 interrupt-controller;
730 #interrupt-cells = <2>;
733 modem_smp2p_ipa_out: ipa-ap-to-modem {
734 qcom,entry-name = "ipa";
735 #qcom,smem-state-cells = <1>;
738 modem_smp2p_ipa_in: ipa-modem-to-ap {
739 qcom,entry-name = "ipa";
740 interrupt-controller;
741 #interrupt-cells = <2>;
744 modem_smp2p_wlan_in: wlan-wpss-to-ap {
745 qcom,entry-name = "wlan";
746 interrupt-controller;
747 #interrupt-cells = <2>;
751 smp2p-slpi {
759 qcom,local-pid = <0>;
760 qcom,remote-pid = <3>;
762 slpi_smp2p_out: master-kernel {
763 qcom,entry-name = "master-kernel";
764 #qcom,smem-state-cells = <1>;
767 slpi_smp2p_in: slave-kernel {
768 qcom,entry-name = "slave-kernel";
770 interrupt-controller;
771 #interrupt-cells = <2>;
776 compatible = "simple-bus";
777 #address-cells = <2>;
778 #size-cells = <2>;
780 dma-ranges = <0 0 0 0 0x10 0>;
782 gcc: clock-controller@100000 {
783 compatible = "qcom,gcc-sc8180x";
785 #clock-cells = <1>;
786 #reset-cells = <1>;
787 #power-domain-cells = <1>;
791 clock-names = "bi_tcxo",
794 power-domains = <&rpmhpd SC8180X_CX>;
798 compatible = "qcom,geni-se-qup";
802 clock-names = "m-ahb", "s-ahb";
803 #address-cells = <2>;
804 #size-cells = <2>;
810 compatible = "qcom,geni-i2c";
813 clock-names = "se";
818 interconnect-names = "qup-core", "qup-config", "qup-memory";
819 #address-cells = <1>;
820 #size-cells = <0>;
824 spi0: spi@880000 {
825 compatible = "qcom,geni-spi";
828 clock-names = "se";
832 interconnect-names = "qup-core", "qup-config";
833 #address-cells = <1>;
834 #size-cells = <0>;
839 compatible = "qcom,geni-uart";
842 clock-names = "se";
846 interconnect-names = "qup-core", "qup-config";
851 compatible = "qcom,geni-i2c";
854 clock-names = "se";
859 interconnect-names = "qup-core", "qup-config", "qup-memory";
860 #address-cells = <1>;
861 #size-cells = <0>;
865 spi1: spi@884000 {
866 compatible = "qcom,geni-spi";
869 clock-names = "se";
873 interconnect-names = "qup-core", "qup-config";
874 #address-cells = <1>;
875 #size-cells = <0>;
880 compatible = "qcom,geni-uart";
883 clock-names = "se";
887 interconnect-names = "qup-core", "qup-config";
892 compatible = "qcom,geni-i2c";
895 clock-names = "se";
900 interconnect-names = "qup-core", "qup-config", "qup-memory";
901 #address-cells = <1>;
902 #size-cells = <0>;
906 spi2: spi@888000 {
907 compatible = "qcom,geni-spi";
910 clock-names = "se";
914 interconnect-names = "qup-core", "qup-config";
915 #address-cells = <1>;
916 #size-cells = <0>;
921 compatible = "qcom,geni-uart";
924 clock-names = "se";
928 interconnect-names = "qup-core", "qup-config";
933 compatible = "qcom,geni-i2c";
936 clock-names = "se";
941 interconnect-names = "qup-core", "qup-config", "qup-memory";
942 #address-cells = <1>;
943 #size-cells = <0>;
947 spi3: spi@88c000 {
948 compatible = "qcom,geni-spi";
951 clock-names = "se";
955 interconnect-names = "qup-core", "qup-config";
956 #address-cells = <1>;
957 #size-cells = <0>;
962 compatible = "qcom,geni-uart";
965 clock-names = "se";
969 interconnect-names = "qup-core", "qup-config";
974 compatible = "qcom,geni-i2c";
977 clock-names = "se";
982 interconnect-names = "qup-core", "qup-config", "qup-memory";
983 #address-cells = <1>;
984 #size-cells = <0>;
988 spi4: spi@890000 {
989 compatible = "qcom,geni-spi";
992 clock-names = "se";
996 interconnect-names = "qup-core", "qup-config";
997 #address-cells = <1>;
998 #size-cells = <0>;
1003 compatible = "qcom,geni-uart";
1006 clock-names = "se";
1010 interconnect-names = "qup-core", "qup-config";
1015 compatible = "qcom,geni-i2c";
1018 clock-names = "se";
1023 interconnect-names = "qup-core", "qup-config", "qup-memory";
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1029 spi5: spi@894000 {
1030 compatible = "qcom,geni-spi";
1033 clock-names = "se";
1037 interconnect-names = "qup-core", "qup-config";
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1044 compatible = "qcom,geni-uart";
1047 clock-names = "se";
1051 interconnect-names = "qup-core", "qup-config";
1056 compatible = "qcom,geni-i2c";
1059 clock-names = "se";
1064 interconnect-names = "qup-core", "qup-config", "qup-memory";
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1070 spi6: spi@898000 {
1071 compatible = "qcom,geni-spi";
1074 clock-names = "se";
1078 interconnect-names = "qup-core", "qup-config";
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1085 compatible = "qcom,geni-uart";
1088 clock-names = "se";
1092 interconnect-names = "qup-core", "qup-config";
1097 compatible = "qcom,geni-i2c";
1100 clock-names = "se";
1105 interconnect-names = "qup-core", "qup-config", "qup-memory";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1111 spi7: spi@89c000 {
1112 compatible = "qcom,geni-spi";
1115 clock-names = "se";
1119 interconnect-names = "qup-core", "qup-config";
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1126 compatible = "qcom,geni-uart";
1129 clock-names = "se";
1133 interconnect-names = "qup-core", "qup-config";
1139 compatible = "qcom,geni-se-qup";
1143 clock-names = "m-ahb", "s-ahb";
1144 #address-cells = <2>;
1145 #size-cells = <2>;
1151 compatible = "qcom,geni-i2c";
1154 clock-names = "se";
1159 interconnect-names = "qup-core", "qup-config", "qup-memory";
1160 #address-cells = <1>;
1161 #size-cells = <0>;
1165 spi8: spi@a80000 {
1166 compatible = "qcom,geni-spi";
1169 clock-names = "se";
1173 interconnect-names = "qup-core", "qup-config";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1180 compatible = "qcom,geni-uart";
1183 clock-names = "se";
1187 interconnect-names = "qup-core", "qup-config";
1192 compatible = "qcom,geni-i2c";
1195 clock-names = "se";
1200 interconnect-names = "qup-core", "qup-config", "qup-memory";
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1206 spi9: spi@a84000 {
1207 compatible = "qcom,geni-spi";
1210 clock-names = "se";
1214 interconnect-names = "qup-core", "qup-config";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 compatible = "qcom,geni-debug-uart";
1224 clock-names = "se";
1228 interconnect-names = "qup-core", "qup-config";
1233 compatible = "qcom,geni-i2c";
1236 clock-names = "se";
1241 interconnect-names = "qup-core", "qup-config", "qup-memory";
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1247 spi10: spi@a88000 {
1248 compatible = "qcom,geni-spi";
1251 clock-names = "se";
1255 interconnect-names = "qup-core", "qup-config";
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1262 compatible = "qcom,geni-uart";
1265 clock-names = "se";
1269 interconnect-names = "qup-core", "qup-config";
1274 compatible = "qcom,geni-i2c";
1277 clock-names = "se";
1282 interconnect-names = "qup-core", "qup-config", "qup-memory";
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1288 spi11: spi@a8c000 {
1289 compatible = "qcom,geni-spi";
1292 clock-names = "se";
1296 interconnect-names = "qup-core", "qup-config";
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1303 compatible = "qcom,geni-uart";
1306 clock-names = "se";
1310 interconnect-names = "qup-core", "qup-config";
1315 compatible = "qcom,geni-i2c";
1318 clock-names = "se";
1323 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1329 spi12: spi@a90000 {
1330 compatible = "qcom,geni-spi";
1333 clock-names = "se";
1337 interconnect-names = "qup-core", "qup-config";
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1344 compatible = "qcom,geni-uart";
1347 clock-names = "se";
1351 interconnect-names = "qup-core", "qup-config";
1356 compatible = "qcom,geni-i2c";
1359 clock-names = "se";
1364 interconnect-names = "qup-core", "qup-config", "qup-memory";
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1370 spi16: spi@a94000 {
1371 compatible = "qcom,geni-spi";
1374 clock-names = "se";
1378 interconnect-names = "qup-core", "qup-config";
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1385 compatible = "qcom,geni-uart";
1388 clock-names = "se";
1392 interconnect-names = "qup-core", "qup-config";
1398 compatible = "qcom,geni-se-qup";
1402 clock-names = "m-ahb", "s-ahb";
1403 #address-cells = <2>;
1404 #size-cells = <2>;
1410 compatible = "qcom,geni-i2c";
1413 clock-names = "se";
1418 interconnect-names = "qup-core", "qup-config", "qup-memory";
1419 #address-cells = <1>;
1420 #size-cells = <0>;
1424 spi17: spi@c80000 {
1425 compatible = "qcom,geni-spi";
1428 clock-names = "se";
1432 interconnect-names = "qup-core", "qup-config";
1433 #address-cells = <1>;
1434 #size-cells = <0>;
1439 compatible = "qcom,geni-uart";
1442 clock-names = "se";
1446 interconnect-names = "qup-core", "qup-config";
1451 compatible = "qcom,geni-i2c";
1454 clock-names = "se";
1459 interconnect-names = "qup-core", "qup-config", "qup-memory";
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1465 spi18: spi@c84000 {
1466 compatible = "qcom,geni-spi";
1469 clock-names = "se";
1473 interconnect-names = "qup-core", "qup-config";
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1480 compatible = "qcom,geni-uart";
1483 clock-names = "se";
1487 interconnect-names = "qup-core", "qup-config";
1492 compatible = "qcom,geni-i2c";
1495 clock-names = "se";
1500 interconnect-names = "qup-core", "qup-config", "qup-memory";
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1506 spi19: spi@c88000 {
1507 compatible = "qcom,geni-spi";
1510 clock-names = "se";
1514 interconnect-names = "qup-core", "qup-config";
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1521 compatible = "qcom,geni-uart";
1524 clock-names = "se";
1528 interconnect-names = "qup-core", "qup-config";
1533 compatible = "qcom,geni-i2c";
1536 clock-names = "se";
1541 interconnect-names = "qup-core", "qup-config", "qup-memory";
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1547 spi13: spi@c8c000 {
1548 compatible = "qcom,geni-spi";
1551 clock-names = "se";
1555 interconnect-names = "qup-core", "qup-config";
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1562 compatible = "qcom,geni-uart";
1565 clock-names = "se";
1569 interconnect-names = "qup-core", "qup-config";
1574 compatible = "qcom,geni-i2c";
1577 clock-names = "se";
1582 interconnect-names = "qup-core", "qup-config", "qup-memory";
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1588 spi14: spi@c90000 {
1589 compatible = "qcom,geni-spi";
1592 clock-names = "se";
1596 interconnect-names = "qup-core", "qup-config";
1597 #address-cells = <1>;
1598 #size-cells = <0>;
1603 compatible = "qcom,geni-uart";
1606 clock-names = "se";
1610 interconnect-names = "qup-core", "qup-config";
1615 compatible = "qcom,geni-i2c";
1618 clock-names = "se";
1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1629 spi15: spi@c94000 {
1630 compatible = "qcom,geni-spi";
1633 clock-names = "se";
1637 interconnect-names = "qup-core", "qup-config";
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1644 compatible = "qcom,geni-uart";
1647 clock-names = "se";
1651 interconnect-names = "qup-core", "qup-config";
1657 compatible = "qcom,sc8180x-config-noc";
1659 #interconnect-cells = <2>;
1660 qcom,bcm-voters = <&apps_bcm_voter>;
1664 compatible = "qcom,sc8180x-system-noc";
1666 #interconnect-cells = <2>;
1667 qcom,bcm-voters = <&apps_bcm_voter>;
1671 compatible = "qcom,sc8180x-aggre1-noc";
1673 #interconnect-cells = <2>;
1674 qcom,bcm-voters = <&apps_bcm_voter>;
1678 compatible = "qcom,sc8180x-aggre2-noc";
1680 #interconnect-cells = <2>;
1681 qcom,bcm-voters = <&apps_bcm_voter>;
1685 compatible = "qcom,sc8180x-compute-noc";
1687 #interconnect-cells = <2>;
1688 qcom,bcm-voters = <&apps_bcm_voter>;
1692 compatible = "qcom,sc8180x-mmss-noc";
1694 #interconnect-cells = <2>;
1695 qcom,bcm-voters = <&apps_bcm_voter>;
1699 compatible = "qcom,pcie-sc8180x";
1705 reg-names = "parf",
1711 linux,pci-domain = <0>;
1712 bus-range = <0x00 0xff>;
1713 num-lanes = <2>;
1715 #address-cells = <3>;
1716 #size-cells = <2>;
1729 interrupt-names = "msi0",
1737 #interrupt-cells = <1>;
1738 interrupt-map-mask = <0 0 0 0x7>;
1739 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1752 clock-names = "pipe",
1761 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1762 assigned-clock-rates = <19200000>;
1764 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1768 reset-names = "pci";
1770 power-domains = <&gcc PCIE_0_GDSC>;
1774 interconnect-names = "pcie-mem", "cpu-pcie";
1777 phy-names = "pciephy";
1778 dma-coherent;
1785 bus-range = <0x01 0xff>;
1787 #address-cells = <3>;
1788 #size-cells = <2>;
1794 compatible = "qcom,sc8180x-qmp-pcie-phy";
1801 clock-names = "aux",
1806 #clock-cells = <0>;
1807 clock-output-names = "pcie_0_pipe_clk";
1808 #phy-cells = <0>;
1811 reset-names = "phy";
1813 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1814 assigned-clock-rates = <100000000>;
1820 compatible = "qcom,pcie-sc8180x";
1826 reg-names = "parf",
1832 linux,pci-domain = <3>;
1833 bus-range = <0x00 0xff>;
1834 num-lanes = <2>;
1836 #address-cells = <3>;
1837 #size-cells = <2>;
1850 interrupt-names = "msi0",
1858 #interrupt-cells = <1>;
1859 interrupt-map-mask = <0 0 0 0x7>;
1860 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1873 clock-names = "pipe",
1882 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1883 assigned-clock-rates = <19200000>;
1885 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1889 reset-names = "pci";
1891 power-domains = <&gcc PCIE_3_GDSC>;
1895 interconnect-names = "pcie-mem", "cpu-pcie";
1898 phy-names = "pciephy";
1899 dma-coherent;
1906 bus-range = <0x01 0xff>;
1908 #address-cells = <3>;
1909 #size-cells = <2>;
1915 compatible = "qcom,sc8180x-qmp-pcie-phy";
1922 clock-names = "aux",
1927 #clock-cells = <0>;
1928 clock-output-names = "pcie_3_pipe_clk";
1930 #phy-cells = <0>;
1933 reset-names = "phy";
1935 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1936 assigned-clock-rates = <100000000>;
1942 compatible = "qcom,pcie-sc8180x";
1948 reg-names = "parf",
1954 linux,pci-domain = <1>;
1955 bus-range = <0x00 0xff>;
1956 num-lanes = <2>;
1958 #address-cells = <3>;
1959 #size-cells = <2>;
1972 interrupt-names = "msi0",
1980 #interrupt-cells = <1>;
1981 interrupt-map-mask = <0 0 0 0x7>;
1982 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1995 clock-names = "pipe",
2004 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2005 assigned-clock-rates = <19200000>;
2007 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2011 reset-names = "pci";
2013 power-domains = <&gcc PCIE_1_GDSC>;
2017 interconnect-names = "pcie-mem", "cpu-pcie";
2020 phy-names = "pciephy";
2021 dma-coherent;
2028 bus-range = <0x01 0xff>;
2030 #address-cells = <3>;
2031 #size-cells = <2>;
2037 compatible = "qcom,sc8180x-qmp-pcie-phy";
2044 clock-names = "aux",
2049 #clock-cells = <0>;
2050 clock-output-names = "pcie_1_pipe_clk";
2052 #phy-cells = <0>;
2055 reset-names = "phy";
2057 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2058 assigned-clock-rates = <100000000>;
2064 compatible = "qcom,pcie-sc8180x";
2070 reg-names = "parf",
2076 linux,pci-domain = <2>;
2077 bus-range = <0x00 0xff>;
2078 num-lanes = <4>;
2080 #address-cells = <3>;
2081 #size-cells = <2>;
2094 interrupt-names = "msi0",
2102 #interrupt-cells = <1>;
2103 interrupt-map-mask = <0 0 0 0x7>;
2104 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2117 clock-names = "pipe",
2126 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2127 assigned-clock-rates = <19200000>;
2129 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2133 reset-names = "pci";
2135 power-domains = <&gcc PCIE_2_GDSC>;
2139 interconnect-names = "pcie-mem", "cpu-pcie";
2142 phy-names = "pciephy";
2143 dma-coherent;
2150 bus-range = <0x01 0xff>;
2152 #address-cells = <3>;
2153 #size-cells = <2>;
2159 compatible = "qcom,sc8180x-qmp-pcie-phy";
2166 clock-names = "aux",
2171 #clock-cells = <0>;
2172 clock-output-names = "pcie_2_pipe_clk";
2174 #phy-cells = <0>;
2177 reset-names = "phy";
2179 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2180 assigned-clock-rates = <100000000>;
2186 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2187 "jedec,ufs-2.0";
2191 phy-names = "ufsphy";
2192 lanes-per-direction = <2>;
2193 #reset-cells = <1>;
2195 reset-names = "rst";
2207 clock-names = "core_clk",
2215 freq-table-hz = <37500000 300000000>,
2224 power-domains = <&gcc UFS_PHY_GDSC>;
2230 interconnect-names = "ufs-ddr", "cpu-ufs";
2235 ufs_mem_phy: phy-wrapper@1d87000 {
2236 compatible = "qcom,sc8180x-qmp-ufs-phy";
2242 clock-names = "ref",
2247 reset-names = "ufsphy";
2249 power-domains = <&gcc UFS_PHY_GDSC>;
2251 #phy-cells = <0>;
2257 compatible = "qcom,tcsr-mutex";
2259 #hwlock-cells = <1>;
2263 compatible = "qcom,adreno-680.1", "qcom,adreno";
2266 reg-names = "kgsl_3d0_reg_memory";
2272 operating-points-v2 = <&gpu_opp_table>;
2275 interconnect-names = "gfx-mem";
2278 #cooling-cells = <2>;
2282 gpu_opp_table: opp-table {
2283 compatible = "operating-points-v2";
2285 opp-514000000 {
2286 opp-hz = /bits/ 64 <514000000>;
2287 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2290 opp-500000000 {
2291 opp-hz = /bits/ 64 <500000000>;
2292 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2295 opp-461000000 {
2296 opp-hz = /bits/ 64 <461000000>;
2297 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2300 opp-405000000 {
2301 opp-hz = /bits/ 64 <405000000>;
2302 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2305 opp-315000000 {
2306 opp-hz = /bits/ 64 <315000000>;
2307 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2310 opp-256000000 {
2311 opp-hz = /bits/ 64 <256000000>;
2312 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2315 opp-177000000 {
2316 opp-hz = /bits/ 64 <177000000>;
2317 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2323 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2328 reg-names = "gmu",
2334 interrupt-names = "hfi", "gmu";
2341 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2343 power-domains = <&gpucc GPU_CX_GDSC>,
2345 power-domain-names = "cx", "gx";
2349 operating-points-v2 = <&gmu_opp_table>;
2351 gmu_opp_table: opp-table {
2352 compatible = "operating-points-v2";
2354 opp-200000000 {
2355 opp-hz = /bits/ 64 <200000000>;
2356 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2359 opp-500000000 {
2360 opp-hz = /bits/ 64 <500000000>;
2361 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2366 gpucc: clock-controller@2c90000 {
2367 compatible = "qcom,sc8180x-gpucc";
2372 clock-names = "bi_tcxo",
2375 #clock-cells = <1>;
2376 #reset-cells = <1>;
2377 #power-domain-cells = <1>;
2381 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2382 "qcom,smmu-500", "arm,mmu-500";
2384 #iommu-cells = <2>;
2385 #global-interrupts = <1>;
2398 clock-names = "ahb", "bus", "iface";
2400 power-domains = <&gpucc GPU_CX_GDSC>;
2404 compatible = "qcom,sc8180x-tlmm";
2408 reg-names = "west", "east", "south";
2410 gpio-controller;
2411 #gpio-cells = <2>;
2412 interrupt-controller;
2413 #interrupt-cells = <2>;
2414 gpio-ranges = <&tlmm 0 0 191>;
2415 wakeup-parent = <&pdc>;
2419 compatible = "qcom,sc8180x-mpss-pas";
2422 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2428 interrupt-names = "wdog", "fatal", "ready", "handover",
2429 "stop-ack", "shutdown-ack";
2432 clock-names = "xo";
2434 power-domains = <&rpmhpd SC8180X_CX>,
2436 power-domain-names = "cx", "mss";
2440 qcom,smem-states = <&modem_smp2p_out 0>;
2441 qcom,smem-state-names = "stop";
2443 glink-edge {
2446 qcom,remote-pid = <1>;
2452 compatible = "qcom,sc8180x-cdsp-pas";
2455 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2460 interrupt-names = "wdog", "fatal", "ready",
2461 "handover", "stop-ack";
2464 clock-names = "xo";
2466 power-domains = <&rpmhpd SC8180X_CX>;
2467 power-domain-names = "cx";
2471 qcom,smem-states = <&cdsp_smp2p_out 0>;
2472 qcom,smem-state-names = "stop";
2476 glink-edge {
2479 qcom,remote-pid = <5>;
2485 compatible = "qcom,sc8180x-usb-hs-phy",
2486 "qcom,usb-snps-hs-7nm-phy";
2489 clock-names = "ref";
2492 #phy-cells = <0>;
2498 compatible = "qcom,sc8180x-usb-hs-phy",
2499 "qcom,usb-snps-hs-7nm-phy";
2502 clock-names = "ref";
2505 #phy-cells = <0>;
2511 compatible = "qcom,sc8180x-usb-hs-phy",
2512 "qcom,usb-snps-hs-7nm-phy";
2514 #phy-cells = <0>;
2517 clock-names = "ref";
2525 compatible = "qcom,sc8180x-usb-hs-phy",
2526 "qcom,usb-snps-hs-7nm-phy";
2528 #phy-cells = <0>;
2531 clock-names = "ref";
2539 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2546 clock-names = "aux",
2553 reset-names = "phy", "common";
2555 #clock-cells = <1>;
2556 #phy-cells = <1>;
2561 #address-cells = <1>;
2562 #size-cells = <0>;
2574 remote-endpoint = <&usb_prim_dwc3_ss>;
2587 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2594 clock-names = "aux",
2601 reset-names = "phy", "phy_phy";
2603 power-domains = <&gcc USB30_MP_GDSC>;
2605 #clock-cells = <0>;
2606 clock-output-names = "usb2_phy0_pipe_clk";
2608 #phy-cells = <0>;
2614 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2621 clock-names = "aux",
2628 reset-names = "phy", "phy_phy";
2630 power-domains = <&gcc USB30_MP_GDSC>;
2632 #clock-cells = <0>;
2633 clock-output-names = "usb2_phy1_pipe_clk";
2635 #phy-cells = <0>;
2641 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2648 clock-names = "aux",
2654 reset-names = "phy", "common";
2656 #clock-cells = <1>;
2657 #phy-cells = <1>;
2662 #address-cells = <1>;
2663 #size-cells = <0>;
2675 remote-endpoint = <&usb_sec_dwc3_ss>;
2687 system-cache-controller@9200000 {
2688 compatible = "qcom,sc8180x-llcc";
2694 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2701 compatible = "qcom,sc8180x-gem-noc";
2703 #interconnect-cells = <2>;
2704 qcom,bcm-voters = <&apps_bcm_voter>;
2708 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
2710 #address-cells = <2>;
2711 #size-cells = <2>;
2713 dma-ranges;
2721 clock-names = "cfg_noc",
2730 interconnect-names = "usb-ddr", "apps-usb";
2732 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2734 assigned-clock-rates = <19200000>, <200000000>;
2736 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
2746 interrupt-names = "pwr_event_1", "pwr_event_2",
2752 power-domains = <&gcc USB30_MP_GDSC>;
2765 snps,dis-u1-entry-quirk;
2766 snps,dis-u2-entry-quirk;
2771 phy-names = "usb2-0",
2772 "usb3-0",
2773 "usb2-1",
2774 "usb3-1";
2780 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2782 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2787 interrupt-names = "pwr_event",
2799 clock-names = "cfg_noc",
2806 power-domains = <&gcc USB30_PRIM_GDSC>;
2810 interconnect-names = "usb-ddr", "apps-usb";
2812 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2814 assigned-clock-rates = <19200000>, <200000000>;
2816 #address-cells = <2>;
2817 #size-cells = <2>;
2819 dma-ranges;
2830 snps,dis-u1-entry-quirk;
2831 snps,dis-u2-entry-quirk;
2833 phy-names = "usb2-phy", "usb3-phy";
2836 #address-cells = <1>;
2837 #size-cells = <0>;
2850 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
2858 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2867 clock-names = "cfg_noc",
2874 power-domains = <&gcc USB30_SEC_GDSC>;
2876 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2881 interrupt-names = "pwr_event",
2887 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2889 assigned-clock-rates = <19200000>, <200000000>;
2893 interconnect-names = "usb-ddr", "apps-usb";
2895 #address-cells = <2>;
2896 #size-cells = <2>;
2898 dma-ranges;
2909 snps,dis-u1-entry-quirk;
2910 snps,dis-u2-entry-quirk;
2912 phy-names = "usb2-phy", "usb3-phy";
2915 #address-cells = <1>;
2916 #size-cells = <0>;
2929 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
2937 compatible = "qcom,sc8180x-mdss";
2939 reg-names = "mdss";
2941 power-domains = <&dispcc MDSS_GDSC>;
2947 clock-names = "iface",
2955 interrupt-controller;
2956 #interrupt-cells = <1>;
2964 interconnect-names = "mdp0-mem",
2965 "mdp1-mem",
2966 "cpu-cfg";
2970 #address-cells = <2>;
2971 #size-cells = <2>;
2977 compatible = "qcom,sc8180x-dpu";
2980 reg-names = "mdp", "vbif";
2988 clock-names = "iface",
2995 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2996 assigned-clock-rates = <19200000>;
2998 operating-points-v2 = <&mdp_opp_table>;
2999 power-domains = <&rpmhpd SC8180X_MMCX>;
3001 interrupt-parent = <&mdss>;
3005 #address-cells = <1>;
3006 #size-cells = <0>;
3011 remote-endpoint = <&dp0_in>;
3018 remote-endpoint = <&mdss_dsi0_in>;
3025 remote-endpoint = <&mdss_dsi1_in>;
3032 remote-endpoint = <&dp1_in>;
3039 remote-endpoint = <&edp_in>;
3044 mdp_opp_table: opp-table {
3045 compatible = "operating-points-v2";
3047 opp-200000000 {
3048 opp-hz = /bits/ 64 <200000000>;
3049 required-opps = <&rpmhpd_opp_low_svs>;
3052 opp-300000000 {
3053 opp-hz = /bits/ 64 <300000000>;
3054 required-opps = <&rpmhpd_opp_svs>;
3057 opp-345000000 {
3058 opp-hz = /bits/ 64 <345000000>;
3059 required-opps = <&rpmhpd_opp_svs_l1>;
3062 opp-460000000 {
3063 opp-hz = /bits/ 64 <460000000>;
3064 required-opps = <&rpmhpd_opp_nom>;
3070 compatible = "qcom,mdss-dsi-ctrl";
3072 reg-names = "dsi_ctrl";
3074 interrupt-parent = <&mdss>;
3083 clock-names = "byte",
3090 operating-points-v2 = <&dsi_opp_table>;
3091 power-domains = <&rpmhpd SC8180X_MMCX>;
3094 phy-names = "dsi";
3099 #address-cells = <1>;
3100 #size-cells = <0>;
3105 remote-endpoint = <&dpu_intf1_out>;
3116 dsi_opp_table: opp-table {
3117 compatible = "operating-points-v2";
3119 opp-187500000 {
3120 opp-hz = /bits/ 64 <187500000>;
3121 required-opps = <&rpmhpd_opp_low_svs>;
3124 opp-300000000 {
3125 opp-hz = /bits/ 64 <300000000>;
3126 required-opps = <&rpmhpd_opp_svs>;
3129 opp-358000000 {
3130 opp-hz = /bits/ 64 <358000000>;
3131 required-opps = <&rpmhpd_opp_svs_l1>;
3136 mdss_dsi0_phy: dsi-phy@ae94400 {
3137 compatible = "qcom,dsi-phy-7nm";
3141 reg-names = "dsi_phy",
3145 #clock-cells = <1>;
3146 #phy-cells = <0>;
3150 clock-names = "iface", "ref";
3156 compatible = "qcom,mdss-dsi-ctrl";
3158 reg-names = "dsi_ctrl";
3160 interrupt-parent = <&mdss>;
3169 clock-names = "byte",
3176 operating-points-v2 = <&dsi_opp_table>;
3177 power-domains = <&rpmhpd SC8180X_MMCX>;
3180 phy-names = "dsi";
3185 #address-cells = <1>;
3186 #size-cells = <0>;
3191 remote-endpoint = <&dpu_intf2_out>;
3203 mdss_dsi1_phy: dsi-phy@ae96400 {
3204 compatible = "qcom,dsi-phy-7nm";
3208 reg-names = "dsi_phy",
3212 #clock-cells = <1>;
3213 #phy-cells = <0>;
3217 clock-names = "iface", "ref";
3222 mdss_dp0: displayport-controller@ae90000 {
3223 compatible = "qcom,sc8180x-dp";
3229 interrupt-parent = <&mdss>;
3236 clock-names = "core_iface",
3242 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3244 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3248 phy-names = "dp";
3250 #sound-dai-cells = <0>;
3252 operating-points-v2 = <&dp0_opp_table>;
3253 power-domains = <&rpmhpd SC8180X_MMCX>;
3258 #address-cells = <1>;
3259 #size-cells = <0>;
3264 remote-endpoint = <&dpu_intf0_out>;
3275 dp0_opp_table: opp-table {
3276 compatible = "operating-points-v2";
3278 opp-160000000 {
3279 opp-hz = /bits/ 64 <160000000>;
3280 required-opps = <&rpmhpd_opp_low_svs>;
3283 opp-270000000 {
3284 opp-hz = /bits/ 64 <270000000>;
3285 required-opps = <&rpmhpd_opp_svs>;
3288 opp-540000000 {
3289 opp-hz = /bits/ 64 <540000000>;
3290 required-opps = <&rpmhpd_opp_svs_l1>;
3293 opp-810000000 {
3294 opp-hz = /bits/ 64 <810000000>;
3295 required-opps = <&rpmhpd_opp_nom>;
3300 mdss_dp1: displayport-controller@ae98000 {
3301 compatible = "qcom,sc8180x-dp";
3307 interrupt-parent = <&mdss>;
3314 clock-names = "core_iface",
3320 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3322 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3326 phy-names = "dp";
3328 #sound-dai-cells = <0>;
3330 operating-points-v2 = <&dp0_opp_table>;
3331 power-domains = <&rpmhpd SC8180X_MMCX>;
3336 #address-cells = <1>;
3337 #size-cells = <0>;
3342 remote-endpoint = <&dpu_intf4_out>;
3353 dp1_opp_table: opp-table {
3354 compatible = "operating-points-v2";
3356 opp-160000000 {
3357 opp-hz = /bits/ 64 <160000000>;
3358 required-opps = <&rpmhpd_opp_low_svs>;
3361 opp-270000000 {
3362 opp-hz = /bits/ 64 <270000000>;
3363 required-opps = <&rpmhpd_opp_svs>;
3366 opp-540000000 {
3367 opp-hz = /bits/ 64 <540000000>;
3368 required-opps = <&rpmhpd_opp_svs_l1>;
3371 opp-810000000 {
3372 opp-hz = /bits/ 64 <810000000>;
3373 required-opps = <&rpmhpd_opp_nom>;
3378 mdss_edp: displayport-controller@ae9a000 {
3379 compatible = "qcom,sc8180x-edp";
3384 interrupt-parent = <&mdss>;
3391 clock-names = "core_iface",
3397 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3399 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3402 phy-names = "dp";
3404 operating-points-v2 = <&edp_opp_table>;
3405 power-domains = <&rpmhpd SC8180X_MMCX>;
3410 #address-cells = <1>;
3411 #size-cells = <0>;
3416 remote-endpoint = <&dpu_intf5_out>;
3421 edp_opp_table: opp-table {
3422 compatible = "operating-points-v2";
3424 opp-160000000 {
3425 opp-hz = /bits/ 64 <160000000>;
3426 required-opps = <&rpmhpd_opp_low_svs>;
3429 opp-270000000 {
3430 opp-hz = /bits/ 64 <270000000>;
3431 required-opps = <&rpmhpd_opp_svs>;
3434 opp-540000000 {
3435 opp-hz = /bits/ 64 <540000000>;
3436 required-opps = <&rpmhpd_opp_svs_l1>;
3439 opp-810000000 {
3440 opp-hz = /bits/ 64 <810000000>;
3441 required-opps = <&rpmhpd_opp_nom>;
3448 compatible = "qcom,sc8180x-edp-phy";
3456 clock-names = "aux", "cfg_ahb";
3458 power-domains = <&rpmhpd SC8180X_MX>;
3460 #clock-cells = <1>;
3461 #phy-cells = <0>;
3464 dispcc: clock-controller@af00000 {
3465 compatible = "qcom,sc8180x-dispcc";
3478 clock-names = "bi_tcxo",
3489 power-domains = <&rpmhpd SC8180X_MMCX>;
3490 required-opps = <&rpmhpd_opp_low_svs>;
3491 #clock-cells = <1>;
3492 #reset-cells = <1>;
3493 #power-domain-cells = <1>;
3496 pdc: interrupt-controller@b220000 {
3497 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3499 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3500 #interrupt-cells = <2>;
3501 interrupt-parent = <&intc>;
3502 interrupt-controller;
3505 tsens0: thermal-sensor@c263000 {
3506 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3512 interrupt-names = "uplow", "critical";
3513 #thermal-sensor-cells = <1>;
3516 tsens1: thermal-sensor@c265000 {
3517 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3523 interrupt-names = "uplow", "critical";
3524 #thermal-sensor-cells = <1>;
3527 aoss_qmp: power-controller@c300000 {
3528 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3533 #clock-cells = <0>;
3537 compatible = "qcom,rpmh-stats";
3542 compatible = "qcom,spmi-pmic-arb";
3548 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3549 interrupt-names = "periph_irq";
3553 #address-cells = <2>;
3554 #size-cells = <0>;
3555 interrupt-controller;
3556 #interrupt-cells = <4>;
3560 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3562 #iommu-cells = <2>;
3563 #global-interrupts = <1>;
3671 dma-coherent;
3675 compatible = "qcom,sc8180x-adsp-pas";
3678 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3683 interrupt-names = "wdog", "fatal", "ready",
3684 "handover", "stop-ack";
3687 clock-names = "xo";
3689 power-domains = <&rpmhpd SC8180X_CX>;
3690 power-domain-names = "cx";
3694 qcom,smem-states = <&adsp_smp2p_out 0>;
3695 qcom,smem-state-names = "stop";
3699 remoteproc_adsp_glink: glink-edge {
3702 qcom,remote-pid = <2>;
3707 intc: interrupt-controller@17a00000 {
3708 compatible = "arm,gic-v3";
3709 interrupt-controller;
3710 #interrupt-cells = <3>;
3714 #redistributor-regions = <1>;
3715 redistributor-stride = <0 0x20000>;
3719 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
3721 #mbox-cells = <1>;
3725 compatible = "arm,armv7-timer-mem";
3728 #address-cells = <1>;
3729 #size-cells = <1>;
3735 frame-number = <0>;
3742 frame-number = <1>;
3749 frame-number = <2>;
3756 frame-number = <3>;
3763 frame-number = <4>;
3770 frame-number = <5>;
3777 frame-number = <6>;
3784 compatible = "qcom,rpmh-rsc";
3788 reg-names = "drv-0", "drv-1", "drv-2";
3792 qcom,tcs-offset = <0xd00>;
3793 qcom,drv-id = <2>;
3794 qcom,tcs-config = <ACTIVE_TCS 2>,
3799 power-domains = <&cluster_pd>;
3801 apps_bcm_voter: bcm-voter {
3802 compatible = "qcom,bcm-voter";
3805 rpmhcc: clock-controller {
3806 compatible = "qcom,sc8180x-rpmh-clk";
3807 #clock-cells = <1>;
3808 clock-names = "xo";
3812 rpmhpd: power-controller {
3813 compatible = "qcom,sc8180x-rpmhpd";
3814 #power-domain-cells = <1>;
3815 operating-points-v2 = <&rpmhpd_opp_table>;
3817 rpmhpd_opp_table: opp-table {
3818 compatible = "operating-points-v2";
3821 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3825 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3829 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3833 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3837 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3841 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3845 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3849 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3853 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3857 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3864 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3868 clock-names = "xo", "alternate";
3870 #interconnect-cells = <1>;
3874 compatible = "qcom,sc8180x-lmh";
3878 qcom,lmh-temp-arm-millicelsius = <65000>;
3879 qcom,lmh-temp-low-millicelsius = <94500>;
3880 qcom,lmh-temp-high-millicelsius = <95000>;
3881 interrupt-controller;
3882 #interrupt-cells = <1>;
3886 compatible = "qcom,sc8180x-lmh";
3890 qcom,lmh-temp-arm-millicelsius = <65000>;
3891 qcom,lmh-temp-low-millicelsius = <94500>;
3892 qcom,lmh-temp-high-millicelsius = <95000>;
3893 interrupt-controller;
3894 #interrupt-cells = <1>;
3898 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw";
3900 reg-names = "freq-domain0", "freq-domain1";
3903 clock-names = "xo", "alternate";
3905 #freq-domain-cells = <1>;
3906 #clock-cells = <1>;
3910 compatible = "qcom,wcn3990-wifi";
3912 reg-names = "membase";
3913 clock-names = "cxo_ref_clk_pin";
3928 qcom,msa-fixed-perm;
3933 thermal-zones {
3934 cpu0-thermal {
3935 polling-delay-passive = <250>;
3937 thermal-sensors = <&tsens0 1>;
3940 cpu-crit {
3948 cpu1-thermal {
3949 polling-delay-passive = <250>;
3951 thermal-sensors = <&tsens0 2>;
3954 cpu-crit {
3962 cpu2-thermal {
3963 polling-delay-passive = <250>;
3965 thermal-sensors = <&tsens0 3>;
3968 cpu-crit {
3976 cpu3-thermal {
3977 polling-delay-passive = <250>;
3979 thermal-sensors = <&tsens0 4>;
3982 cpu-crit {
3990 cpu4-top-thermal {
3991 polling-delay-passive = <250>;
3993 thermal-sensors = <&tsens0 7>;
3996 cpu-crit {
4004 cpu5-top-thermal {
4005 polling-delay-passive = <250>;
4007 thermal-sensors = <&tsens0 8>;
4010 cpu-crit {
4018 cpu6-top-thermal {
4019 polling-delay-passive = <250>;
4021 thermal-sensors = <&tsens0 9>;
4024 cpu-crit {
4032 cpu7-top-thermal {
4033 polling-delay-passive = <250>;
4035 thermal-sensors = <&tsens0 10>;
4038 cpu-crit {
4046 cpu4-bottom-thermal {
4047 polling-delay-passive = <250>;
4049 thermal-sensors = <&tsens0 11>;
4052 cpu-crit {
4060 cpu5-bottom-thermal {
4061 polling-delay-passive = <250>;
4063 thermal-sensors = <&tsens0 12>;
4066 cpu-crit {
4074 cpu6-bottom-thermal {
4075 polling-delay-passive = <250>;
4077 thermal-sensors = <&tsens0 13>;
4080 cpu-crit {
4088 cpu7-bottom-thermal {
4089 polling-delay-passive = <250>;
4091 thermal-sensors = <&tsens0 14>;
4094 cpu-crit {
4102 aoss0-thermal {
4103 polling-delay-passive = <250>;
4105 thermal-sensors = <&tsens0 0>;
4108 trip-point0 {
4116 cluster0-thermal {
4117 polling-delay-passive = <250>;
4119 thermal-sensors = <&tsens0 5>;
4122 cluster-crit {
4130 cluster1-thermal {
4131 polling-delay-passive = <250>;
4133 thermal-sensors = <&tsens0 6>;
4136 cluster-crit {
4144 gpu-top-thermal {
4145 polling-delay-passive = <250>;
4147 thermal-sensors = <&tsens0 15>;
4149 cooling-maps {
4152 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4157 gpu_top_alert0: trip-point0 {
4163 trip-point1 {
4169 trip-point2 {
4177 aoss1-thermal {
4178 polling-delay-passive = <250>;
4180 thermal-sensors = <&tsens1 0>;
4183 trip-point0 {
4191 wlan-thermal {
4192 polling-delay-passive = <250>;
4194 thermal-sensors = <&tsens1 1>;
4197 trip-point0 {
4205 video-thermal {
4206 polling-delay-passive = <250>;
4208 thermal-sensors = <&tsens1 2>;
4211 trip-point0 {
4219 mem-thermal {
4220 polling-delay-passive = <250>;
4222 thermal-sensors = <&tsens1 3>;
4225 trip-point0 {
4233 q6-hvx-thermal {
4234 polling-delay-passive = <250>;
4236 thermal-sensors = <&tsens1 4>;
4239 trip-point0 {
4247 camera-thermal {
4248 polling-delay-passive = <250>;
4250 thermal-sensors = <&tsens1 5>;
4253 trip-point0 {
4261 compute-thermal {
4262 polling-delay-passive = <250>;
4264 thermal-sensors = <&tsens1 6>;
4267 trip-point0 {
4275 mdm-dsp-thermal {
4276 polling-delay-passive = <250>;
4278 thermal-sensors = <&tsens1 7>;
4281 trip-point0 {
4289 npu-thermal {
4290 polling-delay-passive = <250>;
4292 thermal-sensors = <&tsens1 8>;
4295 trip-point0 {
4303 gpu-bottom-thermal {
4304 polling-delay-passive = <250>;
4306 thermal-sensors = <&tsens1 11>;
4308 cooling-maps {
4311 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4316 gpu_bottom_alert0: trip-point0 {
4322 trip-point1 {
4328 trip-point2 {
4338 compatible = "arm,armv8-timer";