Lines Matching +full:i2c +full:- +full:qup +full:- +full:v2
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sc7280.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/mailbox/qcom-ipcc.h>
23 #include <dt-bindings/phy/phy-qcom-qmp.h>
24 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/sound/qcom,lpass.h>
30 #include <dt-bindings/thermal/thermal.h>
33 interrupt-parent = <&intc>;
35 #address-cells = <2>;
36 #size-cells = <2>;
78 xo_board: xo-board {
79 compatible = "fixed-clock";
80 clock-frequency = <76800000>;
81 #clock-cells = <0>;
84 sleep_clk: sleep-clk {
85 compatible = "fixed-clock";
86 clock-frequency = <32764>;
87 #clock-cells = <0>;
91 reserved-memory {
92 #address-cells = <2>;
93 #size-cells = <2>;
96 wlan_ce_mem: wlan-ce@4cd000 {
97 no-map;
103 no-map;
108 no-map;
113 no-map;
116 aop_cmd_db_mem: aop-cmd-db@80860000 {
118 compatible = "qcom,cmd-db";
119 no-map;
122 reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
124 no-map;
127 sec_apps_mem: sec-apps@808ff000 {
129 no-map;
134 no-map;
138 no-map;
142 wlan_fw_mem: wlan-fw@80c00000 {
144 no-map;
149 no-map;
154 no-map;
159 no-map;
162 ipa_fw_mem: ipa-fw@8b700000 {
164 no-map;
169 no-map;
174 no-map;
179 no-map;
183 compatible = "qcom,rmtfs-mem";
185 no-map;
187 qcom,client-id = <1>;
193 #address-cells = <2>;
194 #size-cells = <0>;
201 enable-method = "psci";
202 power-domains = <&cpu_pd0>;
203 power-domain-names = "psci";
204 next-level-cache = <&l2_0>;
205 operating-points-v2 = <&cpu0_opp_table>;
206 capacity-dmips-mhz = <1024>;
207 dynamic-power-coefficient = <100>;
210 qcom,freq-domain = <&cpufreq_hw 0>;
211 #cooling-cells = <2>;
212 l2_0: l2-cache {
214 cache-level = <2>;
215 cache-unified;
216 next-level-cache = <&l3_0>;
217 l3_0: l3-cache {
219 cache-level = <3>;
220 cache-unified;
230 enable-method = "psci";
231 power-domains = <&cpu_pd1>;
232 power-domain-names = "psci";
233 next-level-cache = <&l2_100>;
234 operating-points-v2 = <&cpu0_opp_table>;
235 capacity-dmips-mhz = <1024>;
236 dynamic-power-coefficient = <100>;
239 qcom,freq-domain = <&cpufreq_hw 0>;
240 #cooling-cells = <2>;
241 l2_100: l2-cache {
243 cache-level = <2>;
244 cache-unified;
245 next-level-cache = <&l3_0>;
254 enable-method = "psci";
255 power-domains = <&cpu_pd2>;
256 power-domain-names = "psci";
257 next-level-cache = <&l2_200>;
258 operating-points-v2 = <&cpu0_opp_table>;
259 capacity-dmips-mhz = <1024>;
260 dynamic-power-coefficient = <100>;
263 qcom,freq-domain = <&cpufreq_hw 0>;
264 #cooling-cells = <2>;
265 l2_200: l2-cache {
267 cache-level = <2>;
268 cache-unified;
269 next-level-cache = <&l3_0>;
278 enable-method = "psci";
279 power-domains = <&cpu_pd3>;
280 power-domain-names = "psci";
281 next-level-cache = <&l2_300>;
282 operating-points-v2 = <&cpu0_opp_table>;
283 capacity-dmips-mhz = <1024>;
284 dynamic-power-coefficient = <100>;
287 qcom,freq-domain = <&cpufreq_hw 0>;
288 #cooling-cells = <2>;
289 l2_300: l2-cache {
291 cache-level = <2>;
292 cache-unified;
293 next-level-cache = <&l3_0>;
302 enable-method = "psci";
303 power-domains = <&cpu_pd4>;
304 power-domain-names = "psci";
305 next-level-cache = <&l2_400>;
306 operating-points-v2 = <&cpu4_opp_table>;
307 capacity-dmips-mhz = <1946>;
308 dynamic-power-coefficient = <520>;
311 qcom,freq-domain = <&cpufreq_hw 1>;
312 #cooling-cells = <2>;
313 l2_400: l2-cache {
315 cache-level = <2>;
316 cache-unified;
317 next-level-cache = <&l3_0>;
326 enable-method = "psci";
327 power-domains = <&cpu_pd5>;
328 power-domain-names = "psci";
329 next-level-cache = <&l2_500>;
330 operating-points-v2 = <&cpu4_opp_table>;
331 capacity-dmips-mhz = <1946>;
332 dynamic-power-coefficient = <520>;
335 qcom,freq-domain = <&cpufreq_hw 1>;
336 #cooling-cells = <2>;
337 l2_500: l2-cache {
339 cache-level = <2>;
340 cache-unified;
341 next-level-cache = <&l3_0>;
350 enable-method = "psci";
351 power-domains = <&cpu_pd6>;
352 power-domain-names = "psci";
353 next-level-cache = <&l2_600>;
354 operating-points-v2 = <&cpu4_opp_table>;
355 capacity-dmips-mhz = <1946>;
356 dynamic-power-coefficient = <520>;
359 qcom,freq-domain = <&cpufreq_hw 1>;
360 #cooling-cells = <2>;
361 l2_600: l2-cache {
363 cache-level = <2>;
364 cache-unified;
365 next-level-cache = <&l3_0>;
374 enable-method = "psci";
375 power-domains = <&cpu_pd7>;
376 power-domain-names = "psci";
377 next-level-cache = <&l2_700>;
378 operating-points-v2 = <&cpu7_opp_table>;
379 capacity-dmips-mhz = <1985>;
380 dynamic-power-coefficient = <552>;
383 qcom,freq-domain = <&cpufreq_hw 2>;
384 #cooling-cells = <2>;
385 l2_700: l2-cache {
387 cache-level = <2>;
388 cache-unified;
389 next-level-cache = <&l3_0>;
393 cpu-map {
429 idle-states {
430 entry-method = "psci";
432 little_cpu_sleep_0: cpu-sleep-0-0 {
433 compatible = "arm,idle-state";
434 idle-state-name = "little-power-down";
435 arm,psci-suspend-param = <0x40000003>;
436 entry-latency-us = <549>;
437 exit-latency-us = <901>;
438 min-residency-us = <1774>;
439 local-timer-stop;
442 little_cpu_sleep_1: cpu-sleep-0-1 {
443 compatible = "arm,idle-state";
444 idle-state-name = "little-rail-power-down";
445 arm,psci-suspend-param = <0x40000004>;
446 entry-latency-us = <702>;
447 exit-latency-us = <915>;
448 min-residency-us = <4001>;
449 local-timer-stop;
452 big_cpu_sleep_0: cpu-sleep-1-0 {
453 compatible = "arm,idle-state";
454 idle-state-name = "big-power-down";
455 arm,psci-suspend-param = <0x40000003>;
456 entry-latency-us = <523>;
457 exit-latency-us = <1244>;
458 min-residency-us = <2207>;
459 local-timer-stop;
462 big_cpu_sleep_1: cpu-sleep-1-1 {
463 compatible = "arm,idle-state";
464 idle-state-name = "big-rail-power-down";
465 arm,psci-suspend-param = <0x40000004>;
466 entry-latency-us = <526>;
467 exit-latency-us = <1854>;
468 min-residency-us = <5555>;
469 local-timer-stop;
473 domain_idle_states: domain-idle-states {
474 cluster_sleep_apss_off: cluster-sleep-0 {
475 compatible = "domain-idle-state";
476 arm,psci-suspend-param = <0x41000044>;
477 entry-latency-us = <2752>;
478 exit-latency-us = <3048>;
479 min-residency-us = <6118>;
482 cluster_sleep_cx_ret: cluster-sleep-1 {
483 compatible = "domain-idle-state";
484 arm,psci-suspend-param = <0x41001344>;
485 entry-latency-us = <3263>;
486 exit-latency-us = <4562>;
487 min-residency-us = <8467>;
490 cluster_sleep_llcc_off: cluster-sleep-2 {
491 compatible = "domain-idle-state";
492 arm,psci-suspend-param = <0x4100b344>;
493 entry-latency-us = <3638>;
494 exit-latency-us = <6562>;
495 min-residency-us = <9826>;
500 cpu0_opp_table: opp-table-cpu0 {
501 compatible = "operating-points-v2";
502 opp-shared;
504 cpu0_opp_300mhz: opp-300000000 {
505 opp-hz = /bits/ 64 <300000000>;
506 opp-peak-kBps = <800000 9600000>;
509 cpu0_opp_691mhz: opp-691200000 {
510 opp-hz = /bits/ 64 <691200000>;
511 opp-peak-kBps = <800000 17817600>;
514 cpu0_opp_806mhz: opp-806400000 {
515 opp-hz = /bits/ 64 <806400000>;
516 opp-peak-kBps = <800000 20889600>;
519 cpu0_opp_941mhz: opp-940800000 {
520 opp-hz = /bits/ 64 <940800000>;
521 opp-peak-kBps = <1804000 24576000>;
524 cpu0_opp_1152mhz: opp-1152000000 {
525 opp-hz = /bits/ 64 <1152000000>;
526 opp-peak-kBps = <2188000 27033600>;
529 cpu0_opp_1325mhz: opp-1324800000 {
530 opp-hz = /bits/ 64 <1324800000>;
531 opp-peak-kBps = <2188000 33792000>;
534 cpu0_opp_1517mhz: opp-1516800000 {
535 opp-hz = /bits/ 64 <1516800000>;
536 opp-peak-kBps = <3072000 38092800>;
539 cpu0_opp_1651mhz: opp-1651200000 {
540 opp-hz = /bits/ 64 <1651200000>;
541 opp-peak-kBps = <3072000 41779200>;
544 cpu0_opp_1805mhz: opp-1804800000 {
545 opp-hz = /bits/ 64 <1804800000>;
546 opp-peak-kBps = <4068000 48537600>;
549 cpu0_opp_1958mhz: opp-1958400000 {
550 opp-hz = /bits/ 64 <1958400000>;
551 opp-peak-kBps = <4068000 48537600>;
554 cpu0_opp_2016mhz: opp-2016000000 {
555 opp-hz = /bits/ 64 <2016000000>;
556 opp-peak-kBps = <6220000 48537600>;
560 cpu4_opp_table: opp-table-cpu4 {
561 compatible = "operating-points-v2";
562 opp-shared;
564 cpu4_opp_691mhz: opp-691200000 {
565 opp-hz = /bits/ 64 <691200000>;
566 opp-peak-kBps = <1804000 9600000>;
569 cpu4_opp_941mhz: opp-940800000 {
570 opp-hz = /bits/ 64 <940800000>;
571 opp-peak-kBps = <2188000 17817600>;
574 cpu4_opp_1229mhz: opp-1228800000 {
575 opp-hz = /bits/ 64 <1228800000>;
576 opp-peak-kBps = <4068000 24576000>;
579 cpu4_opp_1344mhz: opp-1344000000 {
580 opp-hz = /bits/ 64 <1344000000>;
581 opp-peak-kBps = <4068000 24576000>;
584 cpu4_opp_1517mhz: opp-1516800000 {
585 opp-hz = /bits/ 64 <1516800000>;
586 opp-peak-kBps = <4068000 24576000>;
589 cpu4_opp_1651mhz: opp-1651200000 {
590 opp-hz = /bits/ 64 <1651200000>;
591 opp-peak-kBps = <6220000 38092800>;
594 cpu4_opp_1901mhz: opp-1900800000 {
595 opp-hz = /bits/ 64 <1900800000>;
596 opp-peak-kBps = <6220000 44851200>;
599 cpu4_opp_2054mhz: opp-2054400000 {
600 opp-hz = /bits/ 64 <2054400000>;
601 opp-peak-kBps = <6220000 44851200>;
604 cpu4_opp_2112mhz: opp-2112000000 {
605 opp-hz = /bits/ 64 <2112000000>;
606 opp-peak-kBps = <6220000 44851200>;
609 cpu4_opp_2131mhz: opp-2131200000 {
610 opp-hz = /bits/ 64 <2131200000>;
611 opp-peak-kBps = <6220000 44851200>;
614 cpu4_opp_2208mhz: opp-2208000000 {
615 opp-hz = /bits/ 64 <2208000000>;
616 opp-peak-kBps = <6220000 44851200>;
619 cpu4_opp_2400mhz: opp-2400000000 {
620 opp-hz = /bits/ 64 <2400000000>;
621 opp-peak-kBps = <8532000 48537600>;
624 cpu4_opp_2611mhz: opp-2611200000 {
625 opp-hz = /bits/ 64 <2611200000>;
626 opp-peak-kBps = <8532000 48537600>;
630 cpu7_opp_table: opp-table-cpu7 {
631 compatible = "operating-points-v2";
632 opp-shared;
634 cpu7_opp_806mhz: opp-806400000 {
635 opp-hz = /bits/ 64 <806400000>;
636 opp-peak-kBps = <1804000 9600000>;
639 cpu7_opp_1056mhz: opp-1056000000 {
640 opp-hz = /bits/ 64 <1056000000>;
641 opp-peak-kBps = <2188000 17817600>;
644 cpu7_opp_1325mhz: opp-1324800000 {
645 opp-hz = /bits/ 64 <1324800000>;
646 opp-peak-kBps = <4068000 24576000>;
649 cpu7_opp_1517mhz: opp-1516800000 {
650 opp-hz = /bits/ 64 <1516800000>;
651 opp-peak-kBps = <4068000 24576000>;
654 cpu7_opp_1766mhz: opp-1766400000 {
655 opp-hz = /bits/ 64 <1766400000>;
656 opp-peak-kBps = <6220000 38092800>;
659 cpu7_opp_1862mhz: opp-1862400000 {
660 opp-hz = /bits/ 64 <1862400000>;
661 opp-peak-kBps = <6220000 38092800>;
664 cpu7_opp_2035mhz: opp-2035200000 {
665 opp-hz = /bits/ 64 <2035200000>;
666 opp-peak-kBps = <6220000 38092800>;
669 cpu7_opp_2112mhz: opp-2112000000 {
670 opp-hz = /bits/ 64 <2112000000>;
671 opp-peak-kBps = <6220000 44851200>;
674 cpu7_opp_2208mhz: opp-2208000000 {
675 opp-hz = /bits/ 64 <2208000000>;
676 opp-peak-kBps = <6220000 44851200>;
679 cpu7_opp_2381mhz: opp-2380800000 {
680 opp-hz = /bits/ 64 <2380800000>;
681 opp-peak-kBps = <6832000 44851200>;
684 cpu7_opp_2400mhz: opp-2400000000 {
685 opp-hz = /bits/ 64 <2400000000>;
686 opp-peak-kBps = <8532000 48537600>;
689 cpu7_opp_2515mhz: opp-2515200000 {
690 opp-hz = /bits/ 64 <2515200000>;
691 opp-peak-kBps = <8532000 48537600>;
694 cpu7_opp_2707mhz: opp-2707200000 {
695 opp-hz = /bits/ 64 <2707200000>;
696 opp-peak-kBps = <8532000 48537600>;
699 cpu7_opp_3014mhz: opp-3014400000 {
700 opp-hz = /bits/ 64 <3014400000>;
701 opp-peak-kBps = <8532000 48537600>;
713 compatible = "qcom,scm-sc7280", "qcom,scm";
714 qcom,dload-mode = <&tcsr_2 0x13000>;
719 compatible = "qcom,sc7280-clk-virt";
720 #interconnect-cells = <2>;
721 qcom,bcm-voters = <&apps_bcm_voter>;
726 memory-region = <&smem_mem>;
730 smp2p-adsp {
733 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
739 qcom,local-pid = <0>;
740 qcom,remote-pid = <2>;
742 adsp_smp2p_out: master-kernel {
743 qcom,entry-name = "master-kernel";
744 #qcom,smem-state-cells = <1>;
747 adsp_smp2p_in: slave-kernel {
748 qcom,entry-name = "slave-kernel";
749 interrupt-controller;
750 #interrupt-cells = <2>;
754 smp2p-cdsp {
757 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
763 qcom,local-pid = <0>;
764 qcom,remote-pid = <5>;
766 cdsp_smp2p_out: master-kernel {
767 qcom,entry-name = "master-kernel";
768 #qcom,smem-state-cells = <1>;
771 cdsp_smp2p_in: slave-kernel {
772 qcom,entry-name = "slave-kernel";
773 interrupt-controller;
774 #interrupt-cells = <2>;
778 smp2p-mpss {
781 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
787 qcom,local-pid = <0>;
788 qcom,remote-pid = <1>;
790 modem_smp2p_out: master-kernel {
791 qcom,entry-name = "master-kernel";
792 #qcom,smem-state-cells = <1>;
795 modem_smp2p_in: slave-kernel {
796 qcom,entry-name = "slave-kernel";
797 interrupt-controller;
798 #interrupt-cells = <2>;
801 ipa_smp2p_out: ipa-ap-to-modem {
802 qcom,entry-name = "ipa";
803 #qcom,smem-state-cells = <1>;
806 ipa_smp2p_in: ipa-modem-to-ap {
807 qcom,entry-name = "ipa";
808 interrupt-controller;
809 #interrupt-cells = <2>;
813 smp2p-wpss {
816 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
822 qcom,local-pid = <0>;
823 qcom,remote-pid = <13>;
825 wpss_smp2p_out: master-kernel {
826 qcom,entry-name = "master-kernel";
827 #qcom,smem-state-cells = <1>;
830 wpss_smp2p_in: slave-kernel {
831 qcom,entry-name = "slave-kernel";
832 interrupt-controller;
833 #interrupt-cells = <2>;
836 wlan_smp2p_out: wlan-ap-to-wpss {
837 qcom,entry-name = "wlan";
838 #qcom,smem-state-cells = <1>;
841 wlan_smp2p_in: wlan-wpss-to-ap {
842 qcom,entry-name = "wlan";
843 interrupt-controller;
844 #interrupt-cells = <2>;
848 pmu-a55 {
849 compatible = "arm,cortex-a55-pmu";
853 pmu-a78 {
854 compatible = "arm,cortex-a78-pmu";
859 compatible = "arm,psci-1.0";
862 cpu_pd0: power-domain-cpu0 {
863 #power-domain-cells = <0>;
864 power-domains = <&cluster_pd>;
865 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
868 cpu_pd1: power-domain-cpu1 {
869 #power-domain-cells = <0>;
870 power-domains = <&cluster_pd>;
871 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
874 cpu_pd2: power-domain-cpu2 {
875 #power-domain-cells = <0>;
876 power-domains = <&cluster_pd>;
877 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
880 cpu_pd3: power-domain-cpu3 {
881 #power-domain-cells = <0>;
882 power-domains = <&cluster_pd>;
883 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
886 cpu_pd4: power-domain-cpu4 {
887 #power-domain-cells = <0>;
888 power-domains = <&cluster_pd>;
889 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
892 cpu_pd5: power-domain-cpu5 {
893 #power-domain-cells = <0>;
894 power-domains = <&cluster_pd>;
895 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
898 cpu_pd6: power-domain-cpu6 {
899 #power-domain-cells = <0>;
900 power-domains = <&cluster_pd>;
901 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
904 cpu_pd7: power-domain-cpu7 {
905 #power-domain-cells = <0>;
906 power-domains = <&cluster_pd>;
907 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
910 cluster_pd: power-domain-cluster {
911 #power-domain-cells = <0>;
912 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>;
916 qspi_opp_table: opp-table-qspi {
917 compatible = "operating-points-v2";
919 opp-75000000 {
920 opp-hz = /bits/ 64 <75000000>;
921 required-opps = <&rpmhpd_opp_low_svs>;
924 opp-150000000 {
925 opp-hz = /bits/ 64 <150000000>;
926 required-opps = <&rpmhpd_opp_svs>;
929 opp-200000000 {
930 opp-hz = /bits/ 64 <200000000>;
931 required-opps = <&rpmhpd_opp_svs_l1>;
934 opp-300000000 {
935 opp-hz = /bits/ 64 <300000000>;
936 required-opps = <&rpmhpd_opp_nom>;
940 qup_opp_table: opp-table-qup {
941 compatible = "operating-points-v2";
943 opp-75000000 {
944 opp-hz = /bits/ 64 <75000000>;
945 required-opps = <&rpmhpd_opp_low_svs>;
948 opp-100000000 {
949 opp-hz = /bits/ 64 <100000000>;
950 required-opps = <&rpmhpd_opp_svs>;
953 opp-128000000 {
954 opp-hz = /bits/ 64 <128000000>;
955 required-opps = <&rpmhpd_opp_nom>;
960 #address-cells = <2>;
961 #size-cells = <2>;
963 dma-ranges = <0 0 0 0 0x10 0>;
964 compatible = "simple-bus";
966 gcc: clock-controller@100000 {
967 compatible = "qcom,gcc-sc7280";
974 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
979 #clock-cells = <1>;
980 #reset-cells = <1>;
981 #power-domain-cells = <1>;
982 power-domains = <&rpmhpd SC7280_CX>;
986 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
989 interrupt-controller;
990 #interrupt-cells = <3>;
991 #mbox-cells = <2>;
995 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
1001 clock-names = "core";
1002 power-domains = <&rpmhpd SC7280_MX>;
1003 #address-cells = <1>;
1004 #size-cells = <1>;
1006 gpu_speed_bin: gpu-speed-bin@1e9 {
1013 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
1014 pinctrl-names = "default", "sleep";
1015 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
1016 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
1021 reg-names = "hc", "cqhci";
1026 interrupt-names = "hc_irq", "pwr_irq";
1031 clock-names = "iface", "core", "xo";
1034 interconnect-names = "sdhc-ddr","cpu-sdhc";
1035 power-domains = <&rpmhpd SC7280_CX>;
1036 operating-points-v2 = <&sdhc1_opp_table>;
1038 bus-width = <8>;
1039 supports-cqe;
1040 dma-coherent;
1042 qcom,dll-config = <0x0007642c>;
1043 qcom,ddr-config = <0x80040868>;
1045 mmc-ddr-1_8v;
1046 mmc-hs200-1_8v;
1047 mmc-hs400-1_8v;
1048 mmc-hs400-enhanced-strobe;
1052 sdhc1_opp_table: opp-table {
1053 compatible = "operating-points-v2";
1055 opp-100000000 {
1056 opp-hz = /bits/ 64 <100000000>;
1057 required-opps = <&rpmhpd_opp_low_svs>;
1058 opp-peak-kBps = <1800000 400000>;
1059 opp-avg-kBps = <100000 0>;
1062 opp-384000000 {
1063 opp-hz = /bits/ 64 <384000000>;
1064 required-opps = <&rpmhpd_opp_nom>;
1065 opp-peak-kBps = <5400000 1600000>;
1066 opp-avg-kBps = <390000 0>;
1071 gpi_dma0: dma-controller@900000 {
1072 #dma-cells = <3>;
1073 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1087 dma-channels = <12>;
1088 dma-channel-mask = <0x7f>;
1094 compatible = "qcom,geni-se-qup";
1098 clock-names = "m-ahb", "s-ahb";
1099 #address-cells = <2>;
1100 #size-cells = <2>;
1105 i2c0: i2c@980000 {
1106 compatible = "qcom,geni-i2c";
1109 clock-names = "se";
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&qup_i2c0_data_clk>;
1113 #address-cells = <1>;
1114 #size-cells = <0>;
1118 interconnect-names = "qup-core", "qup-config",
1119 "qup-memory";
1120 power-domains = <&rpmhpd SC7280_CX>;
1121 required-opps = <&rpmhpd_opp_low_svs>;
1124 dma-names = "tx", "rx";
1129 compatible = "qcom,geni-spi";
1132 clock-names = "se";
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 power-domains = <&rpmhpd SC7280_CX>;
1139 operating-points-v2 = <&qup_opp_table>;
1142 interconnect-names = "qup-core", "qup-config";
1145 dma-names = "tx", "rx";
1150 compatible = "qcom,geni-uart";
1153 clock-names = "se";
1154 pinctrl-names = "default";
1155 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1157 power-domains = <&rpmhpd SC7280_CX>;
1158 operating-points-v2 = <&qup_opp_table>;
1161 interconnect-names = "qup-core", "qup-config";
1165 i2c1: i2c@984000 {
1166 compatible = "qcom,geni-i2c";
1169 clock-names = "se";
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&qup_i2c1_data_clk>;
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1178 interconnect-names = "qup-core", "qup-config",
1179 "qup-memory";
1180 power-domains = <&rpmhpd SC7280_CX>;
1181 required-opps = <&rpmhpd_opp_low_svs>;
1184 dma-names = "tx", "rx";
1189 compatible = "qcom,geni-spi";
1192 clock-names = "se";
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1198 power-domains = <&rpmhpd SC7280_CX>;
1199 operating-points-v2 = <&qup_opp_table>;
1202 interconnect-names = "qup-core", "qup-config";
1205 dma-names = "tx", "rx";
1210 compatible = "qcom,geni-uart";
1213 clock-names = "se";
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1217 power-domains = <&rpmhpd SC7280_CX>;
1218 operating-points-v2 = <&qup_opp_table>;
1221 interconnect-names = "qup-core", "qup-config";
1225 i2c2: i2c@988000 {
1226 compatible = "qcom,geni-i2c";
1229 clock-names = "se";
1230 pinctrl-names = "default";
1231 pinctrl-0 = <&qup_i2c2_data_clk>;
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1238 interconnect-names = "qup-core", "qup-config",
1239 "qup-memory";
1240 power-domains = <&rpmhpd SC7280_CX>;
1241 required-opps = <&rpmhpd_opp_low_svs>;
1244 dma-names = "tx", "rx";
1249 compatible = "qcom,geni-spi";
1252 clock-names = "se";
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1258 power-domains = <&rpmhpd SC7280_CX>;
1259 operating-points-v2 = <&qup_opp_table>;
1262 interconnect-names = "qup-core", "qup-config";
1265 dma-names = "tx", "rx";
1270 compatible = "qcom,geni-uart";
1273 clock-names = "se";
1274 pinctrl-names = "default";
1275 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1277 power-domains = <&rpmhpd SC7280_CX>;
1278 operating-points-v2 = <&qup_opp_table>;
1281 interconnect-names = "qup-core", "qup-config";
1285 i2c3: i2c@98c000 {
1286 compatible = "qcom,geni-i2c";
1289 clock-names = "se";
1290 pinctrl-names = "default";
1291 pinctrl-0 = <&qup_i2c3_data_clk>;
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1298 interconnect-names = "qup-core", "qup-config",
1299 "qup-memory";
1300 power-domains = <&rpmhpd SC7280_CX>;
1301 required-opps = <&rpmhpd_opp_low_svs>;
1304 dma-names = "tx", "rx";
1309 compatible = "qcom,geni-spi";
1312 clock-names = "se";
1313 pinctrl-names = "default";
1314 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1318 power-domains = <&rpmhpd SC7280_CX>;
1319 operating-points-v2 = <&qup_opp_table>;
1322 interconnect-names = "qup-core", "qup-config";
1325 dma-names = "tx", "rx";
1330 compatible = "qcom,geni-uart";
1333 clock-names = "se";
1334 pinctrl-names = "default";
1335 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1337 power-domains = <&rpmhpd SC7280_CX>;
1338 operating-points-v2 = <&qup_opp_table>;
1341 interconnect-names = "qup-core", "qup-config";
1345 i2c4: i2c@990000 {
1346 compatible = "qcom,geni-i2c";
1349 clock-names = "se";
1350 pinctrl-names = "default";
1351 pinctrl-0 = <&qup_i2c4_data_clk>;
1353 #address-cells = <1>;
1354 #size-cells = <0>;
1358 interconnect-names = "qup-core", "qup-config",
1359 "qup-memory";
1360 power-domains = <&rpmhpd SC7280_CX>;
1361 required-opps = <&rpmhpd_opp_low_svs>;
1364 dma-names = "tx", "rx";
1369 compatible = "qcom,geni-spi";
1372 clock-names = "se";
1373 pinctrl-names = "default";
1374 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1378 power-domains = <&rpmhpd SC7280_CX>;
1379 operating-points-v2 = <&qup_opp_table>;
1382 interconnect-names = "qup-core", "qup-config";
1385 dma-names = "tx", "rx";
1390 compatible = "qcom,geni-uart";
1393 clock-names = "se";
1394 pinctrl-names = "default";
1395 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1397 power-domains = <&rpmhpd SC7280_CX>;
1398 operating-points-v2 = <&qup_opp_table>;
1401 interconnect-names = "qup-core", "qup-config";
1405 i2c5: i2c@994000 {
1406 compatible = "qcom,geni-i2c";
1409 clock-names = "se";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_i2c5_data_clk>;
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1418 interconnect-names = "qup-core", "qup-config",
1419 "qup-memory";
1420 power-domains = <&rpmhpd SC7280_CX>;
1421 required-opps = <&rpmhpd_opp_low_svs>;
1424 dma-names = "tx", "rx";
1429 compatible = "qcom,geni-spi";
1432 clock-names = "se";
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1438 power-domains = <&rpmhpd SC7280_CX>;
1439 operating-points-v2 = <&qup_opp_table>;
1442 interconnect-names = "qup-core", "qup-config";
1445 dma-names = "tx", "rx";
1450 compatible = "qcom,geni-debug-uart";
1453 clock-names = "se";
1454 pinctrl-names = "default";
1455 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
1457 power-domains = <&rpmhpd SC7280_CX>;
1458 operating-points-v2 = <&qup_opp_table>;
1461 interconnect-names = "qup-core", "qup-config";
1465 i2c6: i2c@998000 {
1466 compatible = "qcom,geni-i2c";
1469 clock-names = "se";
1470 pinctrl-names = "default";
1471 pinctrl-0 = <&qup_i2c6_data_clk>;
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1478 interconnect-names = "qup-core", "qup-config",
1479 "qup-memory";
1480 power-domains = <&rpmhpd SC7280_CX>;
1481 required-opps = <&rpmhpd_opp_low_svs>;
1484 dma-names = "tx", "rx";
1489 compatible = "qcom,geni-spi";
1492 clock-names = "se";
1493 pinctrl-names = "default";
1494 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498 power-domains = <&rpmhpd SC7280_CX>;
1499 operating-points-v2 = <&qup_opp_table>;
1502 interconnect-names = "qup-core", "qup-config";
1505 dma-names = "tx", "rx";
1510 compatible = "qcom,geni-uart";
1513 clock-names = "se";
1514 pinctrl-names = "default";
1515 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1517 power-domains = <&rpmhpd SC7280_CX>;
1518 operating-points-v2 = <&qup_opp_table>;
1521 interconnect-names = "qup-core", "qup-config";
1525 i2c7: i2c@99c000 {
1526 compatible = "qcom,geni-i2c";
1529 clock-names = "se";
1530 pinctrl-names = "default";
1531 pinctrl-0 = <&qup_i2c7_data_clk>;
1533 #address-cells = <1>;
1534 #size-cells = <0>;
1538 interconnect-names = "qup-core", "qup-config",
1539 "qup-memory";
1540 power-domains = <&rpmhpd SC7280_CX>;
1541 required-opps = <&rpmhpd_opp_low_svs>;
1544 dma-names = "tx", "rx";
1549 compatible = "qcom,geni-spi";
1552 clock-names = "se";
1553 pinctrl-names = "default";
1554 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1558 power-domains = <&rpmhpd SC7280_CX>;
1559 operating-points-v2 = <&qup_opp_table>;
1562 interconnect-names = "qup-core", "qup-config";
1565 dma-names = "tx", "rx";
1570 compatible = "qcom,geni-uart";
1573 clock-names = "se";
1574 pinctrl-names = "default";
1575 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1577 power-domains = <&rpmhpd SC7280_CX>;
1578 operating-points-v2 = <&qup_opp_table>;
1581 interconnect-names = "qup-core", "qup-config";
1586 gpi_dma1: dma-controller@a00000 {
1587 #dma-cells = <3>;
1588 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1602 dma-channels = <12>;
1603 dma-channel-mask = <0x1e>;
1609 compatible = "qcom,geni-se-qup";
1613 clock-names = "m-ahb", "s-ahb";
1614 #address-cells = <2>;
1615 #size-cells = <2>;
1620 i2c8: i2c@a80000 {
1621 compatible = "qcom,geni-i2c";
1624 clock-names = "se";
1625 pinctrl-names = "default";
1626 pinctrl-0 = <&qup_i2c8_data_clk>;
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1633 interconnect-names = "qup-core", "qup-config",
1634 "qup-memory";
1635 power-domains = <&rpmhpd SC7280_CX>;
1636 required-opps = <&rpmhpd_opp_low_svs>;
1639 dma-names = "tx", "rx";
1644 compatible = "qcom,geni-spi";
1647 clock-names = "se";
1648 pinctrl-names = "default";
1649 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1651 #address-cells = <1>;
1652 #size-cells = <0>;
1653 power-domains = <&rpmhpd SC7280_CX>;
1654 operating-points-v2 = <&qup_opp_table>;
1657 interconnect-names = "qup-core", "qup-config";
1660 dma-names = "tx", "rx";
1665 compatible = "qcom,geni-uart";
1668 clock-names = "se";
1669 pinctrl-names = "default";
1670 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1672 power-domains = <&rpmhpd SC7280_CX>;
1673 operating-points-v2 = <&qup_opp_table>;
1676 interconnect-names = "qup-core", "qup-config";
1680 i2c9: i2c@a84000 {
1681 compatible = "qcom,geni-i2c";
1684 clock-names = "se";
1685 pinctrl-names = "default";
1686 pinctrl-0 = <&qup_i2c9_data_clk>;
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1693 interconnect-names = "qup-core", "qup-config",
1694 "qup-memory";
1695 power-domains = <&rpmhpd SC7280_CX>;
1696 required-opps = <&rpmhpd_opp_low_svs>;
1699 dma-names = "tx", "rx";
1704 compatible = "qcom,geni-spi";
1707 clock-names = "se";
1708 pinctrl-names = "default";
1709 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1713 power-domains = <&rpmhpd SC7280_CX>;
1714 operating-points-v2 = <&qup_opp_table>;
1717 interconnect-names = "qup-core", "qup-config";
1720 dma-names = "tx", "rx";
1725 compatible = "qcom,geni-uart";
1728 clock-names = "se";
1729 pinctrl-names = "default";
1730 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1732 power-domains = <&rpmhpd SC7280_CX>;
1733 operating-points-v2 = <&qup_opp_table>;
1736 interconnect-names = "qup-core", "qup-config";
1740 i2c10: i2c@a88000 {
1741 compatible = "qcom,geni-i2c";
1744 clock-names = "se";
1745 pinctrl-names = "default";
1746 pinctrl-0 = <&qup_i2c10_data_clk>;
1748 #address-cells = <1>;
1749 #size-cells = <0>;
1753 interconnect-names = "qup-core", "qup-config",
1754 "qup-memory";
1755 power-domains = <&rpmhpd SC7280_CX>;
1756 required-opps = <&rpmhpd_opp_low_svs>;
1759 dma-names = "tx", "rx";
1764 compatible = "qcom,geni-spi";
1767 clock-names = "se";
1768 pinctrl-names = "default";
1769 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1771 #address-cells = <1>;
1772 #size-cells = <0>;
1773 power-domains = <&rpmhpd SC7280_CX>;
1774 operating-points-v2 = <&qup_opp_table>;
1777 interconnect-names = "qup-core", "qup-config";
1780 dma-names = "tx", "rx";
1785 compatible = "qcom,geni-uart";
1788 clock-names = "se";
1789 pinctrl-names = "default";
1790 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1792 power-domains = <&rpmhpd SC7280_CX>;
1793 operating-points-v2 = <&qup_opp_table>;
1796 interconnect-names = "qup-core", "qup-config";
1800 i2c11: i2c@a8c000 {
1801 compatible = "qcom,geni-i2c";
1804 clock-names = "se";
1805 pinctrl-names = "default";
1806 pinctrl-0 = <&qup_i2c11_data_clk>;
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1813 interconnect-names = "qup-core", "qup-config",
1814 "qup-memory";
1815 power-domains = <&rpmhpd SC7280_CX>;
1816 required-opps = <&rpmhpd_opp_low_svs>;
1819 dma-names = "tx", "rx";
1824 compatible = "qcom,geni-spi";
1827 clock-names = "se";
1828 pinctrl-names = "default";
1829 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1831 #address-cells = <1>;
1832 #size-cells = <0>;
1833 power-domains = <&rpmhpd SC7280_CX>;
1834 operating-points-v2 = <&qup_opp_table>;
1837 interconnect-names = "qup-core", "qup-config";
1840 dma-names = "tx", "rx";
1845 compatible = "qcom,geni-uart";
1848 clock-names = "se";
1849 pinctrl-names = "default";
1850 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1852 power-domains = <&rpmhpd SC7280_CX>;
1853 operating-points-v2 = <&qup_opp_table>;
1856 interconnect-names = "qup-core", "qup-config";
1860 i2c12: i2c@a90000 {
1861 compatible = "qcom,geni-i2c";
1864 clock-names = "se";
1865 pinctrl-names = "default";
1866 pinctrl-0 = <&qup_i2c12_data_clk>;
1868 #address-cells = <1>;
1869 #size-cells = <0>;
1873 interconnect-names = "qup-core", "qup-config",
1874 "qup-memory";
1875 power-domains = <&rpmhpd SC7280_CX>;
1876 required-opps = <&rpmhpd_opp_low_svs>;
1879 dma-names = "tx", "rx";
1884 compatible = "qcom,geni-spi";
1887 clock-names = "se";
1888 pinctrl-names = "default";
1889 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1891 #address-cells = <1>;
1892 #size-cells = <0>;
1893 power-domains = <&rpmhpd SC7280_CX>;
1894 operating-points-v2 = <&qup_opp_table>;
1897 interconnect-names = "qup-core", "qup-config";
1900 dma-names = "tx", "rx";
1905 compatible = "qcom,geni-uart";
1908 clock-names = "se";
1909 pinctrl-names = "default";
1910 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1912 power-domains = <&rpmhpd SC7280_CX>;
1913 operating-points-v2 = <&qup_opp_table>;
1916 interconnect-names = "qup-core", "qup-config";
1920 i2c13: i2c@a94000 {
1921 compatible = "qcom,geni-i2c";
1924 clock-names = "se";
1925 pinctrl-names = "default";
1926 pinctrl-0 = <&qup_i2c13_data_clk>;
1928 #address-cells = <1>;
1929 #size-cells = <0>;
1933 interconnect-names = "qup-core", "qup-config",
1934 "qup-memory";
1935 power-domains = <&rpmhpd SC7280_CX>;
1936 required-opps = <&rpmhpd_opp_low_svs>;
1939 dma-names = "tx", "rx";
1944 compatible = "qcom,geni-spi";
1947 clock-names = "se";
1948 pinctrl-names = "default";
1949 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1951 #address-cells = <1>;
1952 #size-cells = <0>;
1953 power-domains = <&rpmhpd SC7280_CX>;
1954 operating-points-v2 = <&qup_opp_table>;
1957 interconnect-names = "qup-core", "qup-config";
1960 dma-names = "tx", "rx";
1965 compatible = "qcom,geni-uart";
1968 clock-names = "se";
1969 pinctrl-names = "default";
1970 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1972 power-domains = <&rpmhpd SC7280_CX>;
1973 operating-points-v2 = <&qup_opp_table>;
1976 interconnect-names = "qup-core", "qup-config";
1980 i2c14: i2c@a98000 {
1981 compatible = "qcom,geni-i2c";
1984 clock-names = "se";
1985 pinctrl-names = "default";
1986 pinctrl-0 = <&qup_i2c14_data_clk>;
1988 #address-cells = <1>;
1989 #size-cells = <0>;
1993 interconnect-names = "qup-core", "qup-config",
1994 "qup-memory";
1995 power-domains = <&rpmhpd SC7280_CX>;
1996 required-opps = <&rpmhpd_opp_low_svs>;
1999 dma-names = "tx", "rx";
2004 compatible = "qcom,geni-spi";
2007 clock-names = "se";
2008 pinctrl-names = "default";
2009 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2011 #address-cells = <1>;
2012 #size-cells = <0>;
2013 power-domains = <&rpmhpd SC7280_CX>;
2014 operating-points-v2 = <&qup_opp_table>;
2017 interconnect-names = "qup-core", "qup-config";
2020 dma-names = "tx", "rx";
2025 compatible = "qcom,geni-uart";
2028 clock-names = "se";
2029 pinctrl-names = "default";
2030 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
2032 power-domains = <&rpmhpd SC7280_CX>;
2033 operating-points-v2 = <&qup_opp_table>;
2036 interconnect-names = "qup-core", "qup-config";
2040 i2c15: i2c@a9c000 {
2041 compatible = "qcom,geni-i2c";
2044 clock-names = "se";
2045 pinctrl-names = "default";
2046 pinctrl-0 = <&qup_i2c15_data_clk>;
2048 #address-cells = <1>;
2049 #size-cells = <0>;
2053 interconnect-names = "qup-core", "qup-config",
2054 "qup-memory";
2055 power-domains = <&rpmhpd SC7280_CX>;
2056 required-opps = <&rpmhpd_opp_low_svs>;
2059 dma-names = "tx", "rx";
2064 compatible = "qcom,geni-spi";
2067 clock-names = "se";
2068 pinctrl-names = "default";
2069 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2071 #address-cells = <1>;
2072 #size-cells = <0>;
2073 power-domains = <&rpmhpd SC7280_CX>;
2074 operating-points-v2 = <&qup_opp_table>;
2077 interconnect-names = "qup-core", "qup-config";
2080 dma-names = "tx", "rx";
2085 compatible = "qcom,geni-uart";
2088 clock-names = "se";
2089 pinctrl-names = "default";
2090 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2092 power-domains = <&rpmhpd SC7280_CX>;
2093 operating-points-v2 = <&qup_opp_table>;
2096 interconnect-names = "qup-core", "qup-config";
2102 compatible = "qcom,sc7280-trng", "qcom,trng";
2108 compatible = "qcom,sc7280-cnoc2";
2109 #interconnect-cells = <2>;
2110 qcom,bcm-voters = <&apps_bcm_voter>;
2115 compatible = "qcom,sc7280-cnoc3";
2116 #interconnect-cells = <2>;
2117 qcom,bcm-voters = <&apps_bcm_voter>;
2122 compatible = "qcom,sc7280-mc-virt";
2123 #interconnect-cells = <2>;
2124 qcom,bcm-voters = <&apps_bcm_voter>;
2129 compatible = "qcom,sc7280-system-noc";
2130 #interconnect-cells = <2>;
2131 qcom,bcm-voters = <&apps_bcm_voter>;
2135 compatible = "qcom,sc7280-aggre1-noc";
2137 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&apps_bcm_voter>;
2145 compatible = "qcom,sc7280-aggre2-noc";
2146 #interconnect-cells = <2>;
2147 qcom,bcm-voters = <&apps_bcm_voter>;
2153 compatible = "qcom,sc7280-mmss-noc";
2154 #interconnect-cells = <2>;
2155 qcom,bcm-voters = <&apps_bcm_voter>;
2159 compatible = "qcom,wcn6750-wifi";
2195 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2197 qcom,smem-states = <&wlan_smp2p_out 0>;
2198 qcom,smem-state-names = "wlan-smp2p-out";
2202 compatible = "qcom,pcie-sc7280";
2209 reg-names = "parf", "dbi", "elbi", "atu", "config";
2211 linux,pci-domain = <1>;
2212 bus-range = <0x00 0xff>;
2213 num-lanes = <2>;
2215 #address-cells = <3>;
2216 #size-cells = <2>;
2229 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2231 #interrupt-cells = <1>;
2232 interrupt-map-mask = <0 0 0 0x7>;
2233 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2252 clock-names = "pipe",
2266 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2267 assigned-clock-rates = <19200000>;
2270 reset-names = "pci";
2272 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2275 phy-names = "pciephy";
2277 pinctrl-names = "default";
2278 pinctrl-0 = <&pcie1_clkreq_n>;
2280 dma-coherent;
2282 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2290 bus-range = <0x01 0xff>;
2292 #address-cells = <3>;
2293 #size-cells = <2>;
2299 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2306 clock-names = "aux",
2312 clock-output-names = "pcie_1_pipe_clk";
2313 #clock-cells = <0>;
2315 #phy-cells = <0>;
2318 reset-names = "phy";
2320 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2321 assigned-clock-rates = <100000000>;
2327 compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
2328 "jedec,ufs-2.0";
2332 phy-names = "ufsphy";
2333 lanes-per-direction = <2>;
2334 #reset-cells = <1>;
2336 reset-names = "rst";
2338 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2339 required-opps = <&rpmhpd_opp_nom>;
2342 dma-coherent;
2348 interconnect-names = "ufs-ddr", "cpu-ufs";
2358 clock-names = "core_clk",
2366 freq-table-hz =
2381 compatible = "qcom,sc7280-qmp-ufs-phy";
2386 clock-names = "ref", "ref_aux", "qref";
2388 power-domains = <&rpmhpd SC7280_MX>;
2391 reset-names = "ufsphy";
2393 #clock-cells = <1>;
2394 #phy-cells = <0>;
2400 compatible = "qcom,sc7280-inline-crypto-engine",
2401 "qcom,inline-crypto-engine";
2406 cryptobam: dma-controller@1dc4000 {
2407 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2410 #dma-cells = <1>;
2414 qcom,controlled-remotely;
2415 num-channels = <16>;
2416 qcom,num-ees = <4>;
2420 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
2423 dma-names = "rx", "tx";
2427 interconnect-names = "memory";
2431 compatible = "qcom,sc7280-ipa";
2438 reg-names = "ipa-reg",
2439 "ipa-shared",
2442 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2446 interrupt-names = "ipa",
2448 "ipa-clock-query",
2449 "ipa-setup-ready";
2452 clock-names = "core";
2456 interconnect-names = "memory",
2461 qcom,smem-states = <&ipa_smp2p_out 0>,
2463 qcom,smem-state-names = "ipa-clock-enabled-valid",
2464 "ipa-clock-enabled";
2470 compatible = "qcom,tcsr-mutex";
2472 #hwlock-cells = <1>;
2476 compatible = "qcom,sc7280-tcsr", "syscon";
2481 compatible = "qcom,sc7280-tcsr", "syscon";
2486 compatible = "qcom,sc7280-lpasscc";
2489 reg-names = "qdsp6ss", "top_cc";
2491 clock-names = "iface";
2492 #clock-cells = <1>;
2497 compatible = "qcom,sc7280-lpass-rx-macro";
2500 pinctrl-names = "default";
2501 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2506 clock-names = "mclk", "npl", "fsgen";
2508 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2510 power-domain-names = "macro", "dcodec";
2512 #clock-cells = <0>;
2513 #sound-dai-cells = <1>;
2519 compatible = "qcom,soundwire-v1.6.0";
2524 clock-names = "iface";
2526 qcom,din-ports = <0>;
2527 qcom,dout-ports = <5>;
2530 reset-names = "swr_audio_cgcr";
2532 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2533 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2534 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2535 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2536 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2537 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2538 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2539 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2540 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2542 #sound-dai-cells = <1>;
2543 #address-cells = <2>;
2544 #size-cells = <0>;
2550 compatible = "qcom,sc7280-lpass-tx-macro";
2553 pinctrl-names = "default";
2554 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2559 clock-names = "mclk", "npl", "fsgen";
2561 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2563 power-domain-names = "macro", "dcodec";
2565 #clock-cells = <0>;
2566 #sound-dai-cells = <1>;
2572 compatible = "qcom,soundwire-v1.6.0";
2575 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2578 clock-names = "iface";
2580 qcom,din-ports = <3>;
2581 qcom,dout-ports = <0>;
2584 reset-names = "swr_audio_cgcr";
2586 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2587 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2588 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2589 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2590 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2591 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2592 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2593 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2594 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2596 #sound-dai-cells = <1>;
2597 #address-cells = <2>;
2598 #size-cells = <0>;
2603 lpass_audiocc: clock-controller@3300000 {
2604 compatible = "qcom,sc7280-lpassaudiocc";
2609 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2610 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2611 #clock-cells = <1>;
2612 #power-domain-cells = <1>;
2613 #reset-cells = <1>;
2617 compatible = "qcom,sc7280-lpass-va-macro";
2620 pinctrl-names = "default";
2621 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2624 clock-names = "mclk";
2626 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2628 power-domain-names = "macro", "dcodec";
2630 #clock-cells = <0>;
2631 #sound-dai-cells = <1>;
2636 lpass_aon: clock-controller@3380000 {
2637 compatible = "qcom,sc7280-lpassaoncc";
2642 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2643 #clock-cells = <1>;
2644 #power-domain-cells = <1>;
2648 lpass_core: clock-controller@3900000 {
2649 compatible = "qcom,sc7280-lpasscorecc";
2652 clock-names = "bi_tcxo";
2653 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2654 #clock-cells = <1>;
2655 #power-domain-cells = <1>;
2660 compatible = "qcom,sc7280-lpass-cpu";
2668 reg-names = "lpass-hdmiif",
2669 "lpass-lpaif",
2670 "lpass-rxtx-cdc-dma-lpm",
2671 "lpass-rxtx-lpaif",
2672 "lpass-va-lpaif",
2673 "lpass-va-cdc-dma-lpm";
2679 power-domains = <&rpmhpd SC7280_LCX>;
2680 power-domain-names = "lcx";
2681 required-opps = <&rpmhpd_opp_nom>;
2693 clock-names = "aon_cc_audio_hm_h",
2704 #sound-dai-cells = <1>;
2705 #address-cells = <1>;
2706 #size-cells = <0>;
2712 interrupt-names = "lpass-irq-lpaif",
2713 "lpass-irq-hdmi",
2714 "lpass-irq-vaif",
2715 "lpass-irq-rxtxif";
2720 slimbam: dma-controller@3a84000 {
2721 compatible = "qcom,bam-v1.7.0";
2724 #dma-cells = <1>;
2725 qcom,controlled-remotely;
2726 num-channels = <31>;
2728 qcom,num-ees = <2>;
2733 slim: slim-ngd@3ac0000 {
2734 compatible = "qcom,slim-ngd-v1.5.0";
2738 dma-names = "rx", "tx";
2740 #address-cells = <1>;
2741 #size-cells = <0>;
2745 lpass_hm: clock-controller@3c00000 {
2746 compatible = "qcom,sc7280-lpasshm";
2749 clock-names = "bi_tcxo";
2750 #clock-cells = <1>;
2751 #power-domain-cells = <1>;
2757 compatible = "qcom,sc7280-lpass-ag-noc";
2758 #interconnect-cells = <2>;
2759 qcom,bcm-voters = <&apps_bcm_voter>;
2763 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2766 gpio-controller;
2767 #gpio-cells = <2>;
2768 gpio-ranges = <&lpass_tlmm 0 0 15>;
2770 lpass_dmic01_clk: dmic01-clk-state {
2775 lpass_dmic01_data: dmic01-data-state {
2780 lpass_dmic23_clk: dmic23-clk-state {
2785 lpass_dmic23_data: dmic23-data-state {
2790 lpass_rx_swr_clk: rx-swr-clk-state {
2795 lpass_rx_swr_data: rx-swr-data-state {
2800 lpass_tx_swr_clk: tx-swr-clk-state {
2805 lpass_tx_swr_data: tx-swr-data-state {
2812 compatible = "qcom,adreno-635.0", "qcom,adreno";
2816 reg-names = "kgsl_3d0_reg_memory",
2822 operating-points-v2 = <&gpu_opp_table>;
2825 interconnect-names = "gfx-mem";
2826 #cooling-cells = <2>;
2828 nvmem-cells = <&gpu_speed_bin>;
2829 nvmem-cell-names = "speed_bin";
2833 gpu_zap_shader: zap-shader {
2834 memory-region = <&gpu_zap_mem>;
2837 gpu_opp_table: opp-table {
2838 compatible = "operating-points-v2";
2840 opp-315000000 {
2841 opp-hz = /bits/ 64 <315000000>;
2842 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2843 opp-peak-kBps = <1804000>;
2844 opp-supported-hw = <0x17>;
2847 opp-450000000 {
2848 opp-hz = /bits/ 64 <450000000>;
2849 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2850 opp-peak-kBps = <4068000>;
2851 opp-supported-hw = <0x17>;
2855 opp-550000000-0 {
2856 opp-hz = /bits/ 64 <550000000>;
2857 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2858 opp-peak-kBps = <8368000>;
2859 opp-supported-hw = <0x01>;
2862 opp-550000000-1 {
2863 opp-hz = /bits/ 64 <550000000>;
2864 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2865 opp-peak-kBps = <6832000>;
2866 opp-supported-hw = <0x16>;
2869 opp-608000000 {
2870 opp-hz = /bits/ 64 <608000000>;
2871 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2872 opp-peak-kBps = <8368000>;
2873 opp-supported-hw = <0x16>;
2876 opp-700000000 {
2877 opp-hz = /bits/ 64 <700000000>;
2878 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2879 opp-peak-kBps = <8532000>;
2880 opp-supported-hw = <0x06>;
2883 opp-812000000 {
2884 opp-hz = /bits/ 64 <812000000>;
2885 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2886 opp-peak-kBps = <8532000>;
2887 opp-supported-hw = <0x06>;
2890 opp-840000000 {
2891 opp-hz = /bits/ 64 <840000000>;
2892 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2893 opp-peak-kBps = <8532000>;
2894 opp-supported-hw = <0x02>;
2897 opp-900000000 {
2898 opp-hz = /bits/ 64 <900000000>;
2899 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2900 opp-peak-kBps = <8532000>;
2901 opp-supported-hw = <0x02>;
2907 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2911 reg-names = "gmu", "rscc", "gmu_pdc";
2914 interrupt-names = "hfi", "gmu";
2922 clock-names = "gmu",
2929 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2931 power-domain-names = "cx",
2934 operating-points-v2 = <&gmu_opp_table>;
2936 gmu_opp_table: opp-table {
2937 compatible = "operating-points-v2";
2939 opp-200000000 {
2940 opp-hz = /bits/ 64 <200000000>;
2941 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2946 gpucc: clock-controller@3d90000 {
2947 compatible = "qcom,sc7280-gpucc";
2952 clock-names = "bi_tcxo",
2955 #clock-cells = <1>;
2956 #reset-cells = <1>;
2957 #power-domain-cells = <1>;
2961 compatible = "qcom,sc7280-dcc", "qcom,dcc";
2967 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
2968 "qcom,smmu-500", "arm,mmu-500";
2970 #iommu-cells = <2>;
2971 #global-interrupts = <2>;
2992 clock-names = "gcc_gpu_memnoc_gfx_clk",
3000 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3001 dma-coherent;
3005 compatible = "qcom,sc7280-tbu";
3007 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
3011 compatible = "qcom,sc7280-tbu";
3013 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
3017 compatible = "qcom,sc7280-mpss-pas";
3020 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
3026 interrupt-names = "wdog", "fatal", "ready", "handover",
3027 "stop-ack", "shutdown-ack";
3030 clock-names = "xo";
3032 power-domains = <&rpmhpd SC7280_CX>,
3034 power-domain-names = "cx", "mss";
3036 memory-region = <&mpss_mem>;
3040 qcom,smem-states = <&modem_smp2p_out 0>;
3041 qcom,smem-state-names = "stop";
3045 glink-edge {
3046 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
3052 qcom,remote-pid = <1>;
3057 compatible = "arm,coresight-stm", "arm,primecell";
3060 reg-names = "stm-base", "stm-stimulus-base";
3063 clock-names = "apb_pclk";
3065 out-ports {
3068 remote-endpoint = <&funnel0_in7>;
3075 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3079 clock-names = "apb_pclk";
3081 out-ports {
3084 remote-endpoint = <&merge_funnel_in0>;
3089 in-ports {
3090 #address-cells = <1>;
3091 #size-cells = <0>;
3096 remote-endpoint = <&stm_out>;
3103 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3107 clock-names = "apb_pclk";
3109 out-ports {
3112 remote-endpoint = <&merge_funnel_in1>;
3117 in-ports {
3118 #address-cells = <1>;
3119 #size-cells = <0>;
3124 remote-endpoint = <&apss_merge_funnel_out>;
3131 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3135 clock-names = "apb_pclk";
3137 out-ports {
3140 remote-endpoint = <&swao_funnel_in>;
3145 in-ports {
3146 #address-cells = <1>;
3147 #size-cells = <0>;
3152 remote-endpoint = <&funnel0_out>;
3159 remote-endpoint = <&funnel1_out>;
3166 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3170 clock-names = "apb_pclk";
3172 out-ports {
3175 remote-endpoint = <&etr_in>;
3180 in-ports {
3183 remote-endpoint = <&swao_replicator_out>;
3190 compatible = "arm,coresight-tmc", "arm,primecell";
3195 clock-names = "apb_pclk";
3196 arm,scatter-gather;
3198 in-ports {
3201 remote-endpoint = <&replicator_out>;
3208 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3212 clock-names = "apb_pclk";
3214 out-ports {
3217 remote-endpoint = <&etf_in>;
3222 in-ports {
3223 #address-cells = <1>;
3224 #size-cells = <0>;
3229 remote-endpoint = <&merge_funnel_out>;
3236 compatible = "arm,coresight-tmc", "arm,primecell";
3240 clock-names = "apb_pclk";
3242 out-ports {
3245 remote-endpoint = <&swao_replicator_in>;
3250 in-ports {
3253 remote-endpoint = <&swao_funnel_out>;
3260 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3264 clock-names = "apb_pclk";
3265 qcom,replicator-loses-context;
3267 out-ports {
3270 remote-endpoint = <&replicator_in>;
3275 in-ports {
3278 remote-endpoint = <&etf_out>;
3285 compatible = "arm,coresight-etm4x", "arm,primecell";
3291 clock-names = "apb_pclk";
3292 arm,coresight-loses-context-with-cpu;
3293 qcom,skip-power-up;
3295 out-ports {
3298 remote-endpoint = <&apss_funnel_in0>;
3305 compatible = "arm,coresight-etm4x", "arm,primecell";
3311 clock-names = "apb_pclk";
3312 arm,coresight-loses-context-with-cpu;
3313 qcom,skip-power-up;
3315 out-ports {
3318 remote-endpoint = <&apss_funnel_in1>;
3325 compatible = "arm,coresight-etm4x", "arm,primecell";
3331 clock-names = "apb_pclk";
3332 arm,coresight-loses-context-with-cpu;
3333 qcom,skip-power-up;
3335 out-ports {
3338 remote-endpoint = <&apss_funnel_in2>;
3345 compatible = "arm,coresight-etm4x", "arm,primecell";
3351 clock-names = "apb_pclk";
3352 arm,coresight-loses-context-with-cpu;
3353 qcom,skip-power-up;
3355 out-ports {
3358 remote-endpoint = <&apss_funnel_in3>;
3365 compatible = "arm,coresight-etm4x", "arm,primecell";
3371 clock-names = "apb_pclk";
3372 arm,coresight-loses-context-with-cpu;
3373 qcom,skip-power-up;
3375 out-ports {
3378 remote-endpoint = <&apss_funnel_in4>;
3385 compatible = "arm,coresight-etm4x", "arm,primecell";
3391 clock-names = "apb_pclk";
3392 arm,coresight-loses-context-with-cpu;
3393 qcom,skip-power-up;
3395 out-ports {
3398 remote-endpoint = <&apss_funnel_in5>;
3405 compatible = "arm,coresight-etm4x", "arm,primecell";
3411 clock-names = "apb_pclk";
3412 arm,coresight-loses-context-with-cpu;
3413 qcom,skip-power-up;
3415 out-ports {
3418 remote-endpoint = <&apss_funnel_in6>;
3425 compatible = "arm,coresight-etm4x", "arm,primecell";
3431 clock-names = "apb_pclk";
3432 arm,coresight-loses-context-with-cpu;
3433 qcom,skip-power-up;
3435 out-ports {
3438 remote-endpoint = <&apss_funnel_in7>;
3445 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3449 clock-names = "apb_pclk";
3451 out-ports {
3454 remote-endpoint = <&apss_merge_funnel_in>;
3459 in-ports {
3460 #address-cells = <1>;
3461 #size-cells = <0>;
3466 remote-endpoint = <&etm0_out>;
3473 remote-endpoint = <&etm1_out>;
3480 remote-endpoint = <&etm2_out>;
3487 remote-endpoint = <&etm3_out>;
3494 remote-endpoint = <&etm4_out>;
3501 remote-endpoint = <&etm5_out>;
3508 remote-endpoint = <&etm6_out>;
3515 remote-endpoint = <&etm7_out>;
3522 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3526 clock-names = "apb_pclk";
3528 out-ports {
3531 remote-endpoint = <&funnel1_in4>;
3536 in-ports {
3539 remote-endpoint = <&apss_funnel_out>;
3546 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3547 pinctrl-names = "default", "sleep";
3548 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3549 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3557 interrupt-names = "hc_irq", "pwr_irq";
3562 clock-names = "iface", "core", "xo";
3565 interconnect-names = "sdhc-ddr","cpu-sdhc";
3566 power-domains = <&rpmhpd SC7280_CX>;
3567 operating-points-v2 = <&sdhc2_opp_table>;
3569 bus-width = <4>;
3570 dma-coherent;
3572 qcom,dll-config = <0x0007642c>;
3576 sdhc2_opp_table: opp-table {
3577 compatible = "operating-points-v2";
3579 opp-100000000 {
3580 opp-hz = /bits/ 64 <100000000>;
3581 required-opps = <&rpmhpd_opp_low_svs>;
3582 opp-peak-kBps = <1800000 400000>;
3583 opp-avg-kBps = <100000 0>;
3586 opp-202000000 {
3587 opp-hz = /bits/ 64 <202000000>;
3588 required-opps = <&rpmhpd_opp_nom>;
3589 opp-peak-kBps = <5400000 1600000>;
3590 opp-avg-kBps = <200000 0>;
3596 compatible = "qcom,sc7280-usb-hs-phy",
3597 "qcom,usb-snps-hs-7nm-phy";
3600 #phy-cells = <0>;
3603 clock-names = "ref";
3609 compatible = "qcom,sc7280-usb-hs-phy",
3610 "qcom,usb-snps-hs-7nm-phy";
3613 #phy-cells = <0>;
3616 clock-names = "ref";
3622 compatible = "qcom,sc7280-qmp-usb3-dp-phy";
3630 clock-names = "aux",
3637 reset-names = "phy", "common";
3639 #clock-cells = <1>;
3640 #phy-cells = <1>;
3643 #address-cells = <1>;
3644 #size-cells = <0>;
3670 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3673 #address-cells = <2>;
3674 #size-cells = <2>;
3676 dma-ranges;
3683 clock-names = "cfg_noc",
3689 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3691 assigned-clock-rates = <19200000>, <200000000>;
3693 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3697 interrupt-names = "pwr_event",
3702 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3703 required-opps = <&rpmhpd_opp_nom>;
3709 interconnect-names = "usb-ddr", "apps-usb";
3718 snps,dis-u1-entry-quirk;
3719 snps,dis-u2-entry-quirk;
3721 phy-names = "usb2-phy";
3722 maximum-speed = "high-speed";
3723 usb-role-switch;
3727 remote-endpoint = <&eud_ep>;
3734 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3737 #address-cells = <1>;
3738 #size-cells = <0>;
3742 clock-names = "iface", "core";
3745 interconnect-names = "qspi-config";
3746 power-domains = <&rpmhpd SC7280_CX>;
3747 operating-points-v2 = <&qspi_opp_table>;
3752 compatible = "qcom,sc7280-adsp-pas";
3755 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3761 interrupt-names = "wdog", "fatal", "ready", "handover",
3762 "stop-ack", "shutdown-ack";
3765 clock-names = "xo";
3767 power-domains = <&rpmhpd SC7280_LCX>,
3769 power-domain-names = "lcx", "lmx";
3771 memory-region = <&adsp_mem>;
3775 qcom,smem-states = <&adsp_smp2p_out 0>;
3776 qcom,smem-state-names = "stop";
3780 glink-edge {
3781 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3789 qcom,remote-pid = <2>;
3792 compatible = "qcom,apr-v2";
3793 qcom,glink-channels = "apr_audio_svc";
3795 #address-cells = <1>;
3796 #size-cells = <0>;
3801 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3807 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3810 compatible = "qcom,q6afe-dais";
3811 #address-cells = <1>;
3812 #size-cells = <0>;
3813 #sound-dai-cells = <1>;
3816 q6afecc: clock-controller {
3817 compatible = "qcom,q6afe-clocks";
3818 #clock-cells = <2>;
3825 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3828 compatible = "qcom,q6asm-dais";
3829 #address-cells = <1>;
3830 #size-cells = <0>;
3831 #sound-dai-cells = <1>;
3851 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3854 compatible = "qcom,q6adm-routing";
3855 #sound-dai-cells = <0>;
3862 qcom,glink-channels = "fastrpcglink-apps-dsp";
3864 qcom,non-secure-domain;
3865 #address-cells = <1>;
3866 #size-cells = <0>;
3868 compute-cb@3 {
3869 compatible = "qcom,fastrpc-compute-cb";
3874 compute-cb@4 {
3875 compatible = "qcom,fastrpc-compute-cb";
3880 compute-cb@5 {
3881 compatible = "qcom,fastrpc-compute-cb";
3890 compatible = "qcom,sc7280-wpss-pas";
3893 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3899 interrupt-names = "wdog", "fatal", "ready", "handover",
3900 "stop-ack", "shutdown-ack";
3903 clock-names = "xo";
3905 power-domains = <&rpmhpd SC7280_CX>,
3907 power-domain-names = "cx", "mx";
3909 memory-region = <&wpss_mem>;
3913 qcom,smem-states = <&wpss_smp2p_out 0>;
3914 qcom,smem-state-names = "stop";
3919 glink-edge {
3920 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3927 qcom,remote-pid = <13>;
3932 compatible = "qcom,sc7280-llcc-bwmon";
3939 operating-points-v2 = <&llcc_bwmon_opp_table>;
3941 llcc_bwmon_opp_table: opp-table {
3942 compatible = "operating-points-v2";
3944 opp-0 {
3945 opp-peak-kBps = <800000>;
3947 opp-1 {
3948 opp-peak-kBps = <1804000>;
3950 opp-2 {
3951 opp-peak-kBps = <2188000>;
3953 opp-3 {
3954 opp-peak-kBps = <3072000>;
3956 opp-4 {
3957 opp-peak-kBps = <4068000>;
3959 opp-5 {
3960 opp-peak-kBps = <6220000>;
3962 opp-6 {
3963 opp-peak-kBps = <6832000>;
3965 opp-7 {
3966 opp-peak-kBps = <8532000>;
3972 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
3978 operating-points-v2 = <&cpu_bwmon_opp_table>;
3980 cpu_bwmon_opp_table: opp-table {
3981 compatible = "operating-points-v2";
3983 opp-0 {
3984 opp-peak-kBps = <2400000>;
3986 opp-1 {
3987 opp-peak-kBps = <4800000>;
3989 opp-2 {
3990 opp-peak-kBps = <7456000>;
3992 opp-3 {
3993 opp-peak-kBps = <9600000>;
3995 opp-4 {
3996 opp-peak-kBps = <12896000>;
3998 opp-5 {
3999 opp-peak-kBps = <14928000>;
4001 opp-6 {
4002 opp-peak-kBps = <17056000>;
4009 compatible = "qcom,sc7280-dc-noc";
4010 #interconnect-cells = <2>;
4011 qcom,bcm-voters = <&apps_bcm_voter>;
4016 compatible = "qcom,sc7280-gem-noc";
4017 #interconnect-cells = <2>;
4018 qcom,bcm-voters = <&apps_bcm_voter>;
4021 system-cache-controller@9200000 {
4022 compatible = "qcom,sc7280-llcc";
4025 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
4030 compatible = "qcom,sc7280-eud", "qcom,eud";
4033 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
4038 #address-cells = <1>;
4039 #size-cells = <0>;
4044 remote-endpoint = <&usb2_role_switch>;
4052 compatible = "qcom,sc7280-nsp-noc";
4053 #interconnect-cells = <2>;
4054 qcom,bcm-voters = <&apps_bcm_voter>;
4058 compatible = "qcom,sc7280-cdsp-pas";
4061 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4067 interrupt-names = "wdog", "fatal", "ready", "handover",
4068 "stop-ack", "shutdown-ack";
4071 clock-names = "xo";
4073 power-domains = <&rpmhpd SC7280_CX>,
4075 power-domain-names = "cx", "mx";
4079 memory-region = <&cdsp_mem>;
4083 qcom,smem-states = <&cdsp_smp2p_out 0>;
4084 qcom,smem-state-names = "stop";
4088 glink-edge {
4089 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4096 qcom,remote-pid = <5>;
4100 qcom,glink-channels = "fastrpcglink-apps-dsp";
4102 qcom,non-secure-domain;
4103 #address-cells = <1>;
4104 #size-cells = <0>;
4106 compute-cb@1 {
4107 compatible = "qcom,fastrpc-compute-cb";
4113 compute-cb@2 {
4114 compatible = "qcom,fastrpc-compute-cb";
4120 compute-cb@3 {
4121 compatible = "qcom,fastrpc-compute-cb";
4127 compute-cb@4 {
4128 compatible = "qcom,fastrpc-compute-cb";
4134 compute-cb@5 {
4135 compatible = "qcom,fastrpc-compute-cb";
4141 compute-cb@6 {
4142 compatible = "qcom,fastrpc-compute-cb";
4148 compute-cb@7 {
4149 compatible = "qcom,fastrpc-compute-cb";
4155 compute-cb@8 {
4156 compatible = "qcom,fastrpc-compute-cb";
4164 compute-cb@11 {
4165 compatible = "qcom,fastrpc-compute-cb";
4171 compute-cb@12 {
4172 compatible = "qcom,fastrpc-compute-cb";
4178 compute-cb@13 {
4179 compatible = "qcom,fastrpc-compute-cb";
4185 compute-cb@14 {
4186 compatible = "qcom,fastrpc-compute-cb";
4196 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
4199 #address-cells = <2>;
4200 #size-cells = <2>;
4202 dma-ranges;
4209 clock-names = "cfg_noc",
4215 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4217 assigned-clock-rates = <19200000>, <200000000>;
4219 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4224 interrupt-names = "pwr_event",
4230 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4231 required-opps = <&rpmhpd_opp_nom>;
4237 interconnect-names = "usb-ddr", "apps-usb";
4239 wakeup-source;
4248 snps,parkmode-disable-ss-quirk;
4249 snps,dis-u1-entry-quirk;
4250 snps,dis-u2-entry-quirk;
4252 phy-names = "usb2-phy", "usb3-phy";
4253 maximum-speed = "super-speed";
4256 #address-cells = <1>;
4257 #size-cells = <0>;
4276 venus: video-codec@aa00000 {
4277 compatible = "qcom,sc7280-venus";
4286 clock-names = "core", "bus", "iface",
4289 power-domains = <&videocc MVSC_GDSC>,
4292 power-domain-names = "venus", "vcodec0", "cx";
4293 operating-points-v2 = <&venus_opp_table>;
4297 interconnect-names = "cpu-cfg", "video-mem";
4300 memory-region = <&video_mem>;
4304 video-decoder {
4305 compatible = "venus-decoder";
4308 video-encoder {
4309 compatible = "venus-encoder";
4312 venus_opp_table: opp-table {
4313 compatible = "operating-points-v2";
4315 opp-133330000 {
4316 opp-hz = /bits/ 64 <133330000>;
4317 required-opps = <&rpmhpd_opp_low_svs>;
4320 opp-240000000 {
4321 opp-hz = /bits/ 64 <240000000>;
4322 required-opps = <&rpmhpd_opp_svs>;
4325 opp-335000000 {
4326 opp-hz = /bits/ 64 <335000000>;
4327 required-opps = <&rpmhpd_opp_svs_l1>;
4330 opp-424000000 {
4331 opp-hz = /bits/ 64 <424000000>;
4332 required-opps = <&rpmhpd_opp_nom>;
4335 opp-460000048 {
4336 opp-hz = /bits/ 64 <460000048>;
4337 required-opps = <&rpmhpd_opp_turbo>;
4342 videocc: clock-controller@aaf0000 {
4343 compatible = "qcom,sc7280-videocc";
4347 clock-names = "bi_tcxo", "bi_tcxo_ao";
4348 #clock-cells = <1>;
4349 #reset-cells = <1>;
4350 #power-domain-cells = <1>;
4354 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4357 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4364 clock-names = "camnoc_axi",
4369 pinctrl-0 = <&cci0_default &cci1_default>;
4370 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4371 pinctrl-names = "default", "sleep";
4373 #address-cells = <1>;
4374 #size-cells = <0>;
4378 cci0_i2c0: i2c-bus@0 {
4380 clock-frequency = <1000000>;
4381 #address-cells = <1>;
4382 #size-cells = <0>;
4385 cci0_i2c1: i2c-bus@1 {
4387 clock-frequency = <1000000>;
4388 #address-cells = <1>;
4389 #size-cells = <0>;
4394 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4397 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4404 clock-names = "camnoc_axi",
4409 pinctrl-0 = <&cci2_default &cci3_default>;
4410 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4411 pinctrl-names = "default", "sleep";
4413 #address-cells = <1>;
4414 #size-cells = <0>;
4418 cci1_i2c0: i2c-bus@0 {
4420 clock-frequency = <1000000>;
4421 #address-cells = <1>;
4422 #size-cells = <0>;
4425 cci1_i2c1: i2c-bus@1 {
4427 clock-frequency = <1000000>;
4428 #address-cells = <1>;
4429 #size-cells = <0>;
4433 camcc: clock-controller@ad00000 {
4434 compatible = "qcom,sc7280-camcc";
4439 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4440 #clock-cells = <1>;
4441 #reset-cells = <1>;
4442 #power-domain-cells = <1>;
4445 dispcc: clock-controller@af00000 {
4446 compatible = "qcom,sc7280-dispcc";
4456 clock-names = "bi_tcxo",
4464 #clock-cells = <1>;
4465 #reset-cells = <1>;
4466 #power-domain-cells = <1>;
4469 mdss: display-subsystem@ae00000 {
4470 compatible = "qcom,sc7280-mdss";
4472 reg-names = "mdss";
4474 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
4479 clock-names = "iface",
4484 interrupt-controller;
4485 #interrupt-cells = <1>;
4491 interconnect-names = "mdp0-mem",
4492 "cpu-cfg";
4496 #address-cells = <2>;
4497 #size-cells = <2>;
4502 mdss_mdp: display-controller@ae01000 {
4503 compatible = "qcom,sc7280-dpu";
4506 reg-names = "mdp", "vbif";
4514 clock-names = "bus",
4520 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
4522 assigned-clock-rates = <19200000>,
4524 operating-points-v2 = <&mdp_opp_table>;
4525 power-domains = <&rpmhpd SC7280_CX>;
4527 interrupt-parent = <&mdss>;
4531 #address-cells = <1>;
4532 #size-cells = <0>;
4537 remote-endpoint = <&mdss_dsi0_in>;
4544 remote-endpoint = <&edp_in>;
4551 remote-endpoint = <&dp_in>;
4556 mdp_opp_table: opp-table {
4557 compatible = "operating-points-v2";
4559 opp-200000000 {
4560 opp-hz = /bits/ 64 <200000000>;
4561 required-opps = <&rpmhpd_opp_low_svs>;
4564 opp-300000000 {
4565 opp-hz = /bits/ 64 <300000000>;
4566 required-opps = <&rpmhpd_opp_svs>;
4569 opp-380000000 {
4570 opp-hz = /bits/ 64 <380000000>;
4571 required-opps = <&rpmhpd_opp_svs_l1>;
4574 opp-506666667 {
4575 opp-hz = /bits/ 64 <506666667>;
4576 required-opps = <&rpmhpd_opp_nom>;
4579 opp-608000000 {
4580 opp-hz = /bits/ 64 <608000000>;
4581 required-opps = <&rpmhpd_opp_turbo>;
4587 compatible = "qcom,sc7280-dsi-ctrl",
4588 "qcom,mdss-dsi-ctrl";
4590 reg-names = "dsi_ctrl";
4592 interrupt-parent = <&mdss>;
4601 clock-names = "byte",
4608 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4609 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4611 operating-points-v2 = <&dsi_opp_table>;
4612 power-domains = <&rpmhpd SC7280_CX>;
4616 #address-cells = <1>;
4617 #size-cells = <0>;
4622 #address-cells = <1>;
4623 #size-cells = <0>;
4628 remote-endpoint = <&dpu_intf1_out>;
4639 dsi_opp_table: opp-table {
4640 compatible = "operating-points-v2";
4642 opp-187500000 {
4643 opp-hz = /bits/ 64 <187500000>;
4644 required-opps = <&rpmhpd_opp_low_svs>;
4647 opp-300000000 {
4648 opp-hz = /bits/ 64 <300000000>;
4649 required-opps = <&rpmhpd_opp_svs>;
4652 opp-358000000 {
4653 opp-hz = /bits/ 64 <358000000>;
4654 required-opps = <&rpmhpd_opp_svs_l1>;
4660 compatible = "qcom,sc7280-dsi-phy-7nm";
4664 reg-names = "dsi_phy",
4668 #clock-cells = <1>;
4669 #phy-cells = <0>;
4673 clock-names = "iface", "ref";
4679 compatible = "qcom,sc7280-edp";
4680 pinctrl-names = "default";
4681 pinctrl-0 = <&edp_hot_plug_det>;
4688 interrupt-parent = <&mdss>;
4696 clock-names = "core_iface",
4701 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4703 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4706 phy-names = "dp";
4708 operating-points-v2 = <&edp_opp_table>;
4709 power-domains = <&rpmhpd SC7280_CX>;
4714 #address-cells = <1>;
4715 #size-cells = <0>;
4720 remote-endpoint = <&dpu_intf5_out>;
4730 edp_opp_table: opp-table {
4731 compatible = "operating-points-v2";
4733 opp-160000000 {
4734 opp-hz = /bits/ 64 <160000000>;
4735 required-opps = <&rpmhpd_opp_low_svs>;
4738 opp-270000000 {
4739 opp-hz = /bits/ 64 <270000000>;
4740 required-opps = <&rpmhpd_opp_svs>;
4743 opp-540000000 {
4744 opp-hz = /bits/ 64 <540000000>;
4745 required-opps = <&rpmhpd_opp_nom>;
4748 opp-810000000 {
4749 opp-hz = /bits/ 64 <810000000>;
4750 required-opps = <&rpmhpd_opp_nom>;
4756 compatible = "qcom,sc7280-edp-phy";
4765 clock-names = "aux",
4768 #clock-cells = <1>;
4769 #phy-cells = <0>;
4774 mdss_dp: displayport-controller@ae90000 {
4775 compatible = "qcom,sc7280-dp";
4783 interrupt-parent = <&mdss>;
4791 clock-names = "core_iface",
4796 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4798 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4801 phy-names = "dp";
4803 operating-points-v2 = <&dp_opp_table>;
4804 power-domains = <&rpmhpd SC7280_CX>;
4806 #sound-dai-cells = <0>;
4811 #address-cells = <1>;
4812 #size-cells = <0>;
4817 remote-endpoint = <&dpu_intf0_out>;
4827 dp_opp_table: opp-table {
4828 compatible = "operating-points-v2";
4830 opp-160000000 {
4831 opp-hz = /bits/ 64 <160000000>;
4832 required-opps = <&rpmhpd_opp_low_svs>;
4835 opp-270000000 {
4836 opp-hz = /bits/ 64 <270000000>;
4837 required-opps = <&rpmhpd_opp_svs>;
4840 opp-540000000 {
4841 opp-hz = /bits/ 64 <540000000>;
4842 required-opps = <&rpmhpd_opp_svs_l1>;
4845 opp-810000000 {
4846 opp-hz = /bits/ 64 <810000000>;
4847 required-opps = <&rpmhpd_opp_nom>;
4853 pdc: interrupt-controller@b220000 {
4854 compatible = "qcom,sc7280-pdc", "qcom,pdc";
4856 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4861 #interrupt-cells = <2>;
4862 interrupt-parent = <&intc>;
4863 interrupt-controller;
4866 pdc_reset: reset-controller@b5e0000 {
4867 compatible = "qcom,sc7280-pdc-global";
4869 #reset-cells = <1>;
4873 tsens0: thermal-sensor@c263000 {
4874 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4880 interrupt-names = "uplow","critical";
4881 #thermal-sensor-cells = <1>;
4884 tsens1: thermal-sensor@c265000 {
4885 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4891 interrupt-names = "uplow","critical";
4892 #thermal-sensor-cells = <1>;
4895 aoss_reset: reset-controller@c2a0000 {
4896 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4898 #reset-cells = <1>;
4901 aoss_qmp: power-management@c300000 {
4902 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4904 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4910 #clock-cells = <0>;
4914 compatible = "qcom,rpmh-stats";
4919 compatible = "qcom,spmi-pmic-arb";
4925 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4926 interrupt-names = "periph_irq";
4927 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4930 #address-cells = <2>;
4931 #size-cells = <0>;
4932 interrupt-controller;
4933 #interrupt-cells = <4>;
4937 compatible = "qcom,sc7280-pinctrl";
4940 gpio-controller;
4941 #gpio-cells = <2>;
4942 interrupt-controller;
4943 #interrupt-cells = <2>;
4944 gpio-ranges = <&tlmm 0 0 175>;
4945 wakeup-parent = <&pdc>;
4947 cci0_default: cci0-default-state {
4950 drive-strength = <2>;
4951 bias-pull-up;
4954 cci0_sleep: cci0-sleep-state {
4957 drive-strength = <2>;
4958 bias-pull-down;
4961 cci1_default: cci1-default-state {
4964 drive-strength = <2>;
4965 bias-pull-up;
4968 cci1_sleep: cci1-sleep-state {
4971 drive-strength = <2>;
4972 bias-pull-down;
4975 cci2_default: cci2-default-state {
4978 drive-strength = <2>;
4979 bias-pull-up;
4982 cci2_sleep: cci2-sleep-state {
4985 drive-strength = <2>;
4986 bias-pull-down;
4989 cci3_default: cci3-default-state {
4992 drive-strength = <2>;
4993 bias-pull-up;
4996 cci3_sleep: cci3-sleep-state {
4999 drive-strength = <2>;
5000 bias-pull-down;
5003 dp_hot_plug_det: dp-hot-plug-det-state {
5008 edp_hot_plug_det: edp-hot-plug-det-state {
5013 mi2s0_data0: mi2s0-data0-state {
5018 mi2s0_data1: mi2s0-data1-state {
5023 mi2s0_mclk: mi2s0-mclk-state {
5028 mi2s0_sclk: mi2s0-sclk-state {
5033 mi2s0_ws: mi2s0-ws-state {
5038 mi2s1_data0: mi2s1-data0-state {
5043 mi2s1_sclk: mi2s1-sclk-state {
5048 mi2s1_ws: mi2s1-ws-state {
5053 pcie1_clkreq_n: pcie1-clkreq-n-state {
5058 qspi_clk: qspi-clk-state {
5063 qspi_cs0: qspi-cs0-state {
5068 qspi_cs1: qspi-cs1-state {
5073 qspi_data0: qspi-data0-state {
5078 qspi_data1: qspi-data1-state {
5083 qspi_data23: qspi-data23-state {
5088 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5093 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5098 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5103 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5108 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5113 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5118 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5123 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5128 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5133 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5138 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5143 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5148 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5153 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5158 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5163 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5168 qup_spi0_data_clk: qup-spi0-data-clk-state {
5173 qup_spi0_cs: qup-spi0-cs-state {
5178 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5183 qup_spi1_data_clk: qup-spi1-data-clk-state {
5188 qup_spi1_cs: qup-spi1-cs-state {
5193 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5198 qup_spi2_data_clk: qup-spi2-data-clk-state {
5203 qup_spi2_cs: qup-spi2-cs-state {
5208 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5213 qup_spi3_data_clk: qup-spi3-data-clk-state {
5218 qup_spi3_cs: qup-spi3-cs-state {
5223 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5228 qup_spi4_data_clk: qup-spi4-data-clk-state {
5233 qup_spi4_cs: qup-spi4-cs-state {
5238 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5243 qup_spi5_data_clk: qup-spi5-data-clk-state {
5248 qup_spi5_cs: qup-spi5-cs-state {
5253 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5258 qup_spi6_data_clk: qup-spi6-data-clk-state {
5263 qup_spi6_cs: qup-spi6-cs-state {
5268 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5273 qup_spi7_data_clk: qup-spi7-data-clk-state {
5278 qup_spi7_cs: qup-spi7-cs-state {
5283 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5288 qup_spi8_data_clk: qup-spi8-data-clk-state {
5293 qup_spi8_cs: qup-spi8-cs-state {
5298 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5303 qup_spi9_data_clk: qup-spi9-data-clk-state {
5308 qup_spi9_cs: qup-spi9-cs-state {
5313 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5318 qup_spi10_data_clk: qup-spi10-data-clk-state {
5323 qup_spi10_cs: qup-spi10-cs-state {
5328 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5333 qup_spi11_data_clk: qup-spi11-data-clk-state {
5338 qup_spi11_cs: qup-spi11-cs-state {
5343 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5348 qup_spi12_data_clk: qup-spi12-data-clk-state {
5353 qup_spi12_cs: qup-spi12-cs-state {
5358 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5363 qup_spi13_data_clk: qup-spi13-data-clk-state {
5368 qup_spi13_cs: qup-spi13-cs-state {
5373 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5378 qup_spi14_data_clk: qup-spi14-data-clk-state {
5383 qup_spi14_cs: qup-spi14-cs-state {
5388 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5393 qup_spi15_data_clk: qup-spi15-data-clk-state {
5398 qup_spi15_cs: qup-spi15-cs-state {
5403 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5408 qup_uart0_cts: qup-uart0-cts-state {
5413 qup_uart0_rts: qup-uart0-rts-state {
5418 qup_uart0_tx: qup-uart0-tx-state {
5423 qup_uart0_rx: qup-uart0-rx-state {
5428 qup_uart1_cts: qup-uart1-cts-state {
5433 qup_uart1_rts: qup-uart1-rts-state {
5438 qup_uart1_tx: qup-uart1-tx-state {
5443 qup_uart1_rx: qup-uart1-rx-state {
5448 qup_uart2_cts: qup-uart2-cts-state {
5453 qup_uart2_rts: qup-uart2-rts-state {
5458 qup_uart2_tx: qup-uart2-tx-state {
5463 qup_uart2_rx: qup-uart2-rx-state {
5468 qup_uart3_cts: qup-uart3-cts-state {
5473 qup_uart3_rts: qup-uart3-rts-state {
5478 qup_uart3_tx: qup-uart3-tx-state {
5483 qup_uart3_rx: qup-uart3-rx-state {
5488 qup_uart4_cts: qup-uart4-cts-state {
5493 qup_uart4_rts: qup-uart4-rts-state {
5498 qup_uart4_tx: qup-uart4-tx-state {
5503 qup_uart4_rx: qup-uart4-rx-state {
5508 qup_uart5_tx: qup-uart5-tx-state {
5513 qup_uart5_rx: qup-uart5-rx-state {
5518 qup_uart6_cts: qup-uart6-cts-state {
5523 qup_uart6_rts: qup-uart6-rts-state {
5528 qup_uart6_tx: qup-uart6-tx-state {
5533 qup_uart6_rx: qup-uart6-rx-state {
5538 qup_uart7_cts: qup-uart7-cts-state {
5543 qup_uart7_rts: qup-uart7-rts-state {
5548 qup_uart7_tx: qup-uart7-tx-state {
5553 qup_uart7_rx: qup-uart7-rx-state {
5558 qup_uart8_cts: qup-uart8-cts-state {
5563 qup_uart8_rts: qup-uart8-rts-state {
5568 qup_uart8_tx: qup-uart8-tx-state {
5573 qup_uart8_rx: qup-uart8-rx-state {
5578 qup_uart9_cts: qup-uart9-cts-state {
5583 qup_uart9_rts: qup-uart9-rts-state {
5588 qup_uart9_tx: qup-uart9-tx-state {
5593 qup_uart9_rx: qup-uart9-rx-state {
5598 qup_uart10_cts: qup-uart10-cts-state {
5603 qup_uart10_rts: qup-uart10-rts-state {
5608 qup_uart10_tx: qup-uart10-tx-state {
5613 qup_uart10_rx: qup-uart10-rx-state {
5618 qup_uart11_cts: qup-uart11-cts-state {
5623 qup_uart11_rts: qup-uart11-rts-state {
5628 qup_uart11_tx: qup-uart11-tx-state {
5633 qup_uart11_rx: qup-uart11-rx-state {
5638 qup_uart12_cts: qup-uart12-cts-state {
5643 qup_uart12_rts: qup-uart12-rts-state {
5648 qup_uart12_tx: qup-uart12-tx-state {
5653 qup_uart12_rx: qup-uart12-rx-state {
5658 qup_uart13_cts: qup-uart13-cts-state {
5663 qup_uart13_rts: qup-uart13-rts-state {
5668 qup_uart13_tx: qup-uart13-tx-state {
5673 qup_uart13_rx: qup-uart13-rx-state {
5678 qup_uart14_cts: qup-uart14-cts-state {
5683 qup_uart14_rts: qup-uart14-rts-state {
5688 qup_uart14_tx: qup-uart14-tx-state {
5693 qup_uart14_rx: qup-uart14-rx-state {
5698 qup_uart15_cts: qup-uart15-cts-state {
5703 qup_uart15_rts: qup-uart15-rts-state {
5708 qup_uart15_tx: qup-uart15-tx-state {
5713 qup_uart15_rx: qup-uart15-rx-state {
5718 sdc1_clk: sdc1-clk-state {
5722 sdc1_cmd: sdc1-cmd-state {
5726 sdc1_data: sdc1-data-state {
5730 sdc1_rclk: sdc1-rclk-state {
5734 sdc1_clk_sleep: sdc1-clk-sleep-state {
5736 drive-strength = <2>;
5737 bias-bus-hold;
5740 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5742 drive-strength = <2>;
5743 bias-bus-hold;
5746 sdc1_data_sleep: sdc1-data-sleep-state {
5748 drive-strength = <2>;
5749 bias-bus-hold;
5752 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5754 drive-strength = <2>;
5755 bias-bus-hold;
5758 sdc2_clk: sdc2-clk-state {
5762 sdc2_cmd: sdc2-cmd-state {
5766 sdc2_data: sdc2-data-state {
5770 sdc2_clk_sleep: sdc2-clk-sleep-state {
5772 drive-strength = <2>;
5773 bias-bus-hold;
5776 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
5778 drive-strength = <2>;
5779 bias-bus-hold;
5782 sdc2_data_sleep: sdc2-data-sleep-state {
5784 drive-strength = <2>;
5785 bias-bus-hold;
5790 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5793 #address-cells = <1>;
5794 #size-cells = <1>;
5798 pil-reloc@594c {
5799 compatible = "qcom,pil-reloc-info";
5805 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5807 #iommu-cells = <2>;
5808 #global-interrupts = <1>;
5809 dma-coherent;
5894 compatible = "qcom,sc7280-tbu";
5898 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
5902 compatible = "qcom,sc7280-tbu";
5906 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
5910 compatible = "qcom,sc7280-tbu";
5914 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
5915 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
5919 compatible = "qcom,sc7280-tbu";
5923 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
5924 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
5928 compatible = "qcom,sc7280-tbu";
5932 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>;
5933 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
5937 compatible = "qcom,sc7280-tbu";
5941 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
5942 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
5946 compatible = "qcom,sc7280-tbu";
5950 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
5954 compatible = "qcom,sc7280-tbu";
5958 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
5962 compatible = "qcom,sc7280-tbu";
5966 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>;
5967 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
5970 intc: interrupt-controller@17a00000 {
5971 compatible = "arm,gic-v3";
5975 #interrupt-cells = <3>;
5976 interrupt-controller;
5977 #address-cells = <2>;
5978 #size-cells = <2>;
5981 msi-controller@17a40000 {
5982 compatible = "arm,gic-v3-its";
5984 msi-controller;
5985 #msi-cells = <1>;
5991 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5999 #address-cells = <1>;
6000 #size-cells = <1>;
6002 compatible = "arm,armv7-timer-mem";
6006 frame-number = <0>;
6014 frame-number = <1>;
6021 frame-number = <2>;
6028 frame-number = <3>;
6035 frame-number = <4>;
6042 frame-number = <5>;
6049 frame-number = <6>;
6057 compatible = "qcom,rpmh-rsc";
6061 reg-names = "drv-0", "drv-1", "drv-2";
6065 qcom,tcs-offset = <0xd00>;
6066 qcom,drv-id = <2>;
6067 qcom,tcs-config = <ACTIVE_TCS 2>,
6071 power-domains = <&cluster_pd>;
6073 apps_bcm_voter: bcm-voter {
6074 compatible = "qcom,bcm-voter";
6077 rpmhpd: power-controller {
6078 compatible = "qcom,sc7280-rpmhpd";
6079 #power-domain-cells = <1>;
6080 operating-points-v2 = <&rpmhpd_opp_table>;
6082 rpmhpd_opp_table: opp-table {
6083 compatible = "operating-points-v2";
6086 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6090 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6094 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6098 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6102 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
6106 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6110 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6114 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6118 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6123 rpmhcc: clock-controller {
6124 compatible = "qcom,sc7280-rpmh-clk";
6126 clock-names = "xo";
6127 #clock-cells = <1>;
6132 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
6135 clock-names = "xo", "alternate";
6136 #interconnect-cells = <1>;
6140 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
6148 interrupt-names = "dcvsh-irq-0",
6149 "dcvsh-irq-1",
6150 "dcvsh-irq-2";
6153 clock-names = "xo", "alternate";
6154 #freq-domain-cells = <1>;
6155 #clock-cells = <1>;
6162 thermal_zones: thermal-zones {
6163 cpu0-thermal {
6164 polling-delay-passive = <250>;
6166 thermal-sensors = <&tsens0 1>;
6169 cpu0_alert0: trip-point0 {
6175 cpu0_alert1: trip-point1 {
6181 cpu0_crit: cpu-crit {
6188 cooling-maps {
6191 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6206 cpu1-thermal {
6207 polling-delay-passive = <250>;
6209 thermal-sensors = <&tsens0 2>;
6212 cpu1_alert0: trip-point0 {
6218 cpu1_alert1: trip-point1 {
6224 cpu1_crit: cpu-crit {
6231 cooling-maps {
6234 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6241 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6249 cpu2-thermal {
6250 polling-delay-passive = <250>;
6252 thermal-sensors = <&tsens0 3>;
6255 cpu2_alert0: trip-point0 {
6261 cpu2_alert1: trip-point1 {
6267 cpu2_crit: cpu-crit {
6274 cooling-maps {
6277 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6284 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6292 cpu3-thermal {
6293 polling-delay-passive = <250>;
6295 thermal-sensors = <&tsens0 4>;
6298 cpu3_alert0: trip-point0 {
6304 cpu3_alert1: trip-point1 {
6310 cpu3_crit: cpu-crit {
6317 cooling-maps {
6320 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6327 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6335 cpu4-thermal {
6336 polling-delay-passive = <250>;
6338 thermal-sensors = <&tsens0 7>;
6341 cpu4_alert0: trip-point0 {
6347 cpu4_alert1: trip-point1 {
6353 cpu4_crit: cpu-crit {
6360 cooling-maps {
6363 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6370 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6378 cpu5-thermal {
6379 polling-delay-passive = <250>;
6381 thermal-sensors = <&tsens0 8>;
6384 cpu5_alert0: trip-point0 {
6390 cpu5_alert1: trip-point1 {
6396 cpu5_crit: cpu-crit {
6403 cooling-maps {
6406 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6413 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6421 cpu6-thermal {
6422 polling-delay-passive = <250>;
6424 thermal-sensors = <&tsens0 9>;
6427 cpu6_alert0: trip-point0 {
6433 cpu6_alert1: trip-point1 {
6439 cpu6_crit: cpu-crit {
6446 cooling-maps {
6449 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6456 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6464 cpu7-thermal {
6465 polling-delay-passive = <250>;
6467 thermal-sensors = <&tsens0 10>;
6470 cpu7_alert0: trip-point0 {
6476 cpu7_alert1: trip-point1 {
6482 cpu7_crit: cpu-crit {
6489 cooling-maps {
6492 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6499 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6507 cpu8-thermal {
6508 polling-delay-passive = <250>;
6510 thermal-sensors = <&tsens0 11>;
6513 cpu8_alert0: trip-point0 {
6519 cpu8_alert1: trip-point1 {
6525 cpu8_crit: cpu-crit {
6532 cooling-maps {
6535 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6542 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6550 cpu9-thermal {
6551 polling-delay-passive = <250>;
6553 thermal-sensors = <&tsens0 12>;
6556 cpu9_alert0: trip-point0 {
6562 cpu9_alert1: trip-point1 {
6568 cpu9_crit: cpu-crit {
6575 cooling-maps {
6578 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6585 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6593 cpu10-thermal {
6594 polling-delay-passive = <250>;
6596 thermal-sensors = <&tsens0 13>;
6599 cpu10_alert0: trip-point0 {
6605 cpu10_alert1: trip-point1 {
6611 cpu10_crit: cpu-crit {
6618 cooling-maps {
6621 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6628 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6636 cpu11-thermal {
6637 polling-delay-passive = <250>;
6639 thermal-sensors = <&tsens0 14>;
6642 cpu11_alert0: trip-point0 {
6648 cpu11_alert1: trip-point1 {
6654 cpu11_crit: cpu-crit {
6661 cooling-maps {
6664 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6671 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6679 aoss0-thermal {
6680 polling-delay-passive = <0>;
6682 thermal-sensors = <&tsens0 0>;
6685 aoss0_alert0: trip-point0 {
6691 aoss0_crit: aoss0-crit {
6699 aoss1-thermal {
6700 polling-delay-passive = <0>;
6702 thermal-sensors = <&tsens1 0>;
6705 aoss1_alert0: trip-point0 {
6711 aoss1_crit: aoss1-crit {
6719 cpuss0-thermal {
6720 polling-delay-passive = <0>;
6722 thermal-sensors = <&tsens0 5>;
6725 cpuss0_alert0: trip-point0 {
6730 cpuss0_crit: cluster0-crit {
6738 cpuss1-thermal {
6739 polling-delay-passive = <0>;
6741 thermal-sensors = <&tsens0 6>;
6744 cpuss1_alert0: trip-point0 {
6749 cpuss1_crit: cluster0-crit {
6757 gpuss0-thermal {
6758 polling-delay-passive = <100>;
6760 thermal-sensors = <&tsens1 1>;
6763 gpuss0_alert0: trip-point0 {
6769 gpuss0_crit: gpuss0-crit {
6776 cooling-maps {
6779 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6784 gpuss1-thermal {
6785 polling-delay-passive = <100>;
6787 thermal-sensors = <&tsens1 2>;
6790 gpuss1_alert0: trip-point0 {
6796 gpuss1_crit: gpuss1-crit {
6803 cooling-maps {
6806 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6811 nspss0-thermal {
6812 thermal-sensors = <&tsens1 3>;
6815 nspss0_alert0: trip-point0 {
6821 nspss0_crit: nspss0-crit {
6829 nspss1-thermal {
6830 thermal-sensors = <&tsens1 4>;
6833 nspss1_alert0: trip-point0 {
6839 nspss1_crit: nspss1-crit {
6847 video-thermal {
6848 thermal-sensors = <&tsens1 5>;
6851 video_alert0: trip-point0 {
6857 video_crit: video-crit {
6865 ddr-thermal {
6866 thermal-sensors = <&tsens1 6>;
6869 ddr_alert0: trip-point0 {
6875 ddr_crit: ddr-crit {
6883 mdmss0-thermal {
6884 thermal-sensors = <&tsens1 7>;
6887 mdmss0_alert0: trip-point0 {
6893 mdmss0_crit: mdmss0-crit {
6901 mdmss1-thermal {
6902 thermal-sensors = <&tsens1 8>;
6905 mdmss1_alert0: trip-point0 {
6911 mdmss1_crit: mdmss1-crit {
6919 mdmss2-thermal {
6920 thermal-sensors = <&tsens1 9>;
6923 mdmss2_alert0: trip-point0 {
6929 mdmss2_crit: mdmss2-crit {
6937 mdmss3-thermal {
6938 thermal-sensors = <&tsens1 10>;
6941 mdmss3_alert0: trip-point0 {
6947 mdmss3_crit: mdmss3-crit {
6955 camera0-thermal {
6956 thermal-sensors = <&tsens1 11>;
6959 camera0_alert0: trip-point0 {
6965 camera0_crit: camera0-crit {
6975 compatible = "arm,armv8-timer";