Lines Matching +full:1 +full:c08000
187 qcom,client-id = <1>;
301 clocks = <&cpufreq_hw 1>;
311 qcom,freq-domain = <&cpufreq_hw 1>;
325 clocks = <&cpufreq_hw 1>;
335 qcom,freq-domain = <&cpufreq_hw 1>;
349 clocks = <&cpufreq_hw 1>;
359 qcom,freq-domain = <&cpufreq_hw 1>;
442 little_cpu_sleep_1: cpu-sleep-0-1 {
452 big_cpu_sleep_0: cpu-sleep-1-0 {
462 big_cpu_sleep_1: cpu-sleep-1-1 {
482 cluster_sleep_cx_ret: cluster-sleep-1 {
744 #qcom,smem-state-cells = <1>;
768 #qcom,smem-state-cells = <1>;
788 qcom,remote-pid = <1>;
792 #qcom,smem-state-cells = <1>;
803 #qcom,smem-state-cells = <1>;
827 #qcom,smem-state-cells = <1>;
838 #qcom,smem-state-cells = <1>;
972 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
979 #clock-cells = <1>;
980 #reset-cells = <1>;
981 #power-domain-cells = <1>;
1003 #address-cells = <1>;
1004 #size-cells = <1>;
1006 gpu_speed_bin: gpu-speed-bin@1e9 {
1016 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
1045 mmc-ddr-1_8v;
1046 mmc-hs200-1_8v;
1047 mmc-hs400-1_8v;
1113 #address-cells = <1>;
1123 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1136 #address-cells = <1>;
1144 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1173 #address-cells = <1>;
1182 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1183 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1196 #address-cells = <1>;
1203 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1204 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1233 #address-cells = <1>;
1243 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1256 #address-cells = <1>;
1264 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1293 #address-cells = <1>;
1303 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1316 #address-cells = <1>;
1324 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1353 #address-cells = <1>;
1363 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1376 #address-cells = <1>;
1384 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1413 #address-cells = <1>;
1423 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1436 #address-cells = <1>;
1444 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1473 #address-cells = <1>;
1483 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1496 #address-cells = <1>;
1504 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1533 #address-cells = <1>;
1543 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1556 #address-cells = <1>;
1564 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1628 #address-cells = <1>;
1638 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1651 #address-cells = <1>;
1659 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1688 #address-cells = <1>;
1697 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1698 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1711 #address-cells = <1>;
1718 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1719 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1748 #address-cells = <1>;
1758 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1771 #address-cells = <1>;
1779 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1808 #address-cells = <1>;
1818 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1831 #address-cells = <1>;
1839 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1868 #address-cells = <1>;
1878 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1891 #address-cells = <1>;
1899 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1928 #address-cells = <1>;
1938 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1951 #address-cells = <1>;
1959 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1988 #address-cells = <1>;
1998 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2011 #address-cells = <1>;
2019 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2048 #address-cells = <1>;
2058 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2071 #address-cells = <1>;
2079 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2201 pcie1: pcie@1c08000 {
2211 linux,pci-domain = <1>;
2231 #interrupt-cells = <1>;
2233 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2298 pcie1_phy: phy@1c0e000 {
2326 ufs_mem_hc: ufshc@1d84000 {
2334 #reset-cells = <1>;
2380 ufs_mem_phy: phy@1d87000 {
2393 #clock-cells = <1>;
2399 ice: crypto@1d88000 {
2406 cryptobam: dma-controller@1dc4000 {
2410 #dma-cells = <1>;
2419 crypto: crypto@1dfa000 {
2430 ipa: ipa@1e40000 {
2445 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2462 <&ipa_smp2p_out 1>;
2469 tcsr_mutex: hwlock@1f40000 {
2472 #hwlock-cells = <1>;
2475 tcsr_1: syscon@1f60000 {
2480 tcsr_2: syscon@1fc0000 {
2492 #clock-cells = <1>;
2513 #sound-dai-cells = <1>;
2542 #sound-dai-cells = <1>;
2566 #sound-dai-cells = <1>;
2596 #sound-dai-cells = <1>;
2611 #clock-cells = <1>;
2612 #power-domain-cells = <1>;
2613 #reset-cells = <1>;
2631 #sound-dai-cells = <1>;
2643 #clock-cells = <1>;
2644 #power-domain-cells = <1>;
2654 #clock-cells = <1>;
2655 #power-domain-cells = <1>;
2704 #sound-dai-cells = <1>;
2705 #address-cells = <1>;
2724 #dma-cells = <1>;
2727 qcom,ee = <1>;
2740 #address-cells = <1>;
2750 #clock-cells = <1>;
2751 #power-domain-cells = <1>;
2821 <&adreno_smmu 1 0x400>;
2862 opp-550000000-1 {
2955 #clock-cells = <1>;
2956 #reset-cells = <1>;
2957 #power-domain-cells = <1>;
3022 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3052 qcom,remote-pid = <1>;
3090 #address-cells = <1>;
3118 #address-cells = <1>;
3146 #address-cells = <1>;
3156 port@1 {
3157 reg = <1>;
3223 #address-cells = <1>;
3460 #address-cells = <1>;
3470 port@1 {
3471 reg = <1>;
3549 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3639 #clock-cells = <1>;
3640 #phy-cells = <1>;
3643 #address-cells = <1>;
3653 port@1 {
3654 reg = <1>;
3737 #address-cells = <1>;
3757 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3795 #address-cells = <1>;
3811 #address-cells = <1>;
3813 #sound-dai-cells = <1>;
3829 #address-cells = <1>;
3831 #sound-dai-cells = <1>;
3838 dai@1 {
3839 reg = <1>;
3865 #address-cells = <1>;
3895 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3947 opp-1 {
3986 opp-1 {
4038 #address-cells = <1>;
4063 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4103 #address-cells = <1>;
4106 compute-cb@1 {
4108 reg = <1>;
4256 #address-cells = <1>;
4266 port@1 {
4267 reg = <1>;
4348 #clock-cells = <1>;
4349 #reset-cells = <1>;
4350 #power-domain-cells = <1>;
4370 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4373 #address-cells = <1>;
4381 #address-cells = <1>;
4385 cci0_i2c1: i2c-bus@1 {
4386 reg = <1>;
4388 #address-cells = <1>;
4410 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4413 #address-cells = <1>;
4421 #address-cells = <1>;
4425 cci1_i2c1: i2c-bus@1 {
4426 reg = <1>;
4428 #address-cells = <1>;
4440 #clock-cells = <1>;
4441 #reset-cells = <1>;
4442 #power-domain-cells = <1>;
4451 <&mdss_dsi_phy 1>,
4455 <&mdss_edp_phy 1>;
4464 #clock-cells = <1>;
4465 #reset-cells = <1>;
4466 #power-domain-cells = <1>;
4485 #interrupt-cells = <1>;
4531 #address-cells = <1>;
4541 port@1 {
4542 reg = <1>;
4609 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4616 #address-cells = <1>;
4622 #address-cells = <1>;
4632 port@1 {
4633 reg = <1>;
4668 #clock-cells = <1>;
4703 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4714 #address-cells = <1>;
4724 port@1 {
4725 reg = <1>;
4768 #clock-cells = <1>;
4811 #address-cells = <1>;
4821 port@1 {
4822 reg = <1>;
4856 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4858 <64 434 2>, <66 438 3>, <69 86 1>,
4859 <70 520 54>, <124 609 31>, <155 63 1>,
4869 #reset-cells = <1>;
4881 #thermal-sensor-cells = <1>;
4892 #thermal-sensor-cells = <1>;
4898 #reset-cells = <1>;
4927 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5793 #address-cells = <1>;
5794 #size-cells = <1>;
5808 #global-interrupts = <1>;
5985 #msi-cells = <1>;
5999 #address-cells = <1>;
6000 #size-cells = <1>;
6014 frame-number = <1>;
6061 reg-names = "drv-0", "drv-1", "drv-2";
6070 <CONTROL_TCS 1>;
6079 #power-domain-cells = <1>;
6127 #clock-cells = <1>;
6136 #interconnect-cells = <1>;
6149 "dcvsh-irq-1",
6154 #freq-domain-cells = <1>;
6155 #clock-cells = <1>;
6166 thermal-sensors = <&tsens0 1>;
6760 thermal-sensors = <&tsens1 1>;