Lines Matching +full:0 +full:x17a10040
81 #clock-cells = <0>;
87 #clock-cells = <0>;
98 reg = <0x0 0x004cd000 0x0 0x1000>;
102 reg = <0x0 0x80000000 0x0 0x600000>;
107 reg = <0x0 0x80600000 0x0 0x200000>;
112 reg = <0x0 0x80800000 0x0 0x60000>;
117 reg = <0x0 0x80860000 0x0 0x20000>;
123 reg = <0x0 0x80884000 0x0 0x10000>;
128 reg = <0x0 0x808ff000 0x0 0x1000>;
133 reg = <0x0 0x80900000 0x0 0x200000>;
139 reg = <0x0 0x80b00000 0x0 0x100000>;
143 reg = <0x0 0x80c00000 0x0 0xc00000>;
148 reg = <0x0 0x86700000 0x0 0x2800000>;
153 reg = <0x0 0x8b200000 0x0 0x500000>;
158 reg = <0x0 0x88f00000 0x0 0x1e00000>;
163 reg = <0 0x8b700000 0 0x10000>;
168 reg = <0 0x8b71a000 0 0x2000>;
173 reg = <0x0 0x8b800000 0x0 0xf600000>;
178 reg = <0x0 0x9ae00000 0x0 0x1900000>;
184 reg = <0x0 0x9c900000 0x0 0x280000>;
194 #size-cells = <0>;
196 cpu0: cpu@0 {
199 reg = <0x0 0x0>;
200 clocks = <&cpufreq_hw 0>;
210 qcom,freq-domain = <&cpufreq_hw 0>;
228 reg = <0x0 0x100>;
229 clocks = <&cpufreq_hw 0>;
239 qcom,freq-domain = <&cpufreq_hw 0>;
252 reg = <0x0 0x200>;
253 clocks = <&cpufreq_hw 0>;
263 qcom,freq-domain = <&cpufreq_hw 0>;
276 reg = <0x0 0x300>;
277 clocks = <&cpufreq_hw 0>;
287 qcom,freq-domain = <&cpufreq_hw 0>;
300 reg = <0x0 0x400>;
324 reg = <0x0 0x500>;
348 reg = <0x0 0x600>;
372 reg = <0x0 0x700>;
432 little_cpu_sleep_0: cpu-sleep-0-0 {
435 arm,psci-suspend-param = <0x40000003>;
442 little_cpu_sleep_1: cpu-sleep-0-1 {
445 arm,psci-suspend-param = <0x40000004>;
452 big_cpu_sleep_0: cpu-sleep-1-0 {
455 arm,psci-suspend-param = <0x40000003>;
465 arm,psci-suspend-param = <0x40000004>;
474 cluster_sleep_apss_off: cluster-sleep-0 {
476 arm,psci-suspend-param = <0x41000044>;
484 arm,psci-suspend-param = <0x41001344>;
492 arm,psci-suspend-param = <0x4100b344>;
708 reg = <0 0x80000000 0 0>;
714 qcom,dload-mode = <&tcsr_2 0x13000>;
739 qcom,local-pid = <0>;
763 qcom,local-pid = <0>;
787 qcom,local-pid = <0>;
822 qcom,local-pid = <0>;
863 #power-domain-cells = <0>;
869 #power-domain-cells = <0>;
875 #power-domain-cells = <0>;
881 #power-domain-cells = <0>;
887 #power-domain-cells = <0>;
893 #power-domain-cells = <0>;
899 #power-domain-cells = <0>;
905 #power-domain-cells = <0>;
911 #power-domain-cells = <0>;
959 soc: soc@0 {
962 ranges = <0 0 0 0 0x10 0>;
963 dma-ranges = <0 0 0 0 0x10 0>;
968 reg = <0 0x00100000 0 0x1f0000>;
971 <0>, <&pcie1_phy>,
972 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
987 reg = <0 0x00408000 0 0x1000>;
996 reg = <0 0x00784000 0 0xa20>,
997 <0 0x00780000 0 0xa20>,
998 <0 0x00782000 0 0x120>,
999 <0 0x00786000 0 0x1fff>;
1007 reg = <0x1e9 0x2>;
1015 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
1019 reg = <0 0x007c4000 0 0x1000>,
1020 <0 0x007c5000 0 0x1000>;
1023 iommus = <&apps_smmu 0xc0 0x0>;
1032 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
1033 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
1042 qcom,dll-config = <0x0007642c>;
1043 qcom,ddr-config = <0x80040868>;
1059 opp-avg-kBps = <100000 0>;
1066 opp-avg-kBps = <390000 0>;
1074 reg = <0 0x00900000 0 0x60000>;
1088 dma-channel-mask = <0x7f>;
1089 iommus = <&apps_smmu 0x0136 0x0>;
1095 reg = <0 0x009c0000 0 0x2000>;
1102 iommus = <&apps_smmu 0x123 0x0>;
1107 reg = <0 0x00980000 0 0x4000>;
1111 pinctrl-0 = <&qup_i2c0_data_clk>;
1114 #size-cells = <0>;
1115 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1116 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1117 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1122 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1123 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1130 reg = <0 0x00980000 0 0x4000>;
1134 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1137 #size-cells = <0>;
1140 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1141 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1143 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1144 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1151 reg = <0 0x00980000 0 0x4000>;
1155 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1160 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1167 reg = <0 0x00984000 0 0x4000>;
1171 pinctrl-0 = <&qup_i2c1_data_clk>;
1174 #size-cells = <0>;
1175 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1176 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1177 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1182 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1190 reg = <0 0x00984000 0 0x4000>;
1194 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1197 #size-cells = <0>;
1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1201 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1203 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1211 reg = <0 0x00984000 0 0x4000>;
1215 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1220 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1227 reg = <0 0x00988000 0 0x4000>;
1231 pinctrl-0 = <&qup_i2c2_data_clk>;
1234 #size-cells = <0>;
1235 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1236 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1237 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1242 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1250 reg = <0 0x00988000 0 0x4000>;
1254 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1257 #size-cells = <0>;
1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1263 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1271 reg = <0 0x00988000 0 0x4000>;
1275 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1279 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1280 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1287 reg = <0 0x0098c000 0 0x4000>;
1291 pinctrl-0 = <&qup_i2c3_data_clk>;
1294 #size-cells = <0>;
1295 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1296 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1297 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1302 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1310 reg = <0 0x0098c000 0 0x4000>;
1314 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1317 #size-cells = <0>;
1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1321 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1323 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1331 reg = <0 0x0098c000 0 0x4000>;
1335 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1339 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1340 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1347 reg = <0 0x00990000 0 0x4000>;
1351 pinctrl-0 = <&qup_i2c4_data_clk>;
1354 #size-cells = <0>;
1355 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1356 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1357 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1362 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1370 reg = <0 0x00990000 0 0x4000>;
1374 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1377 #size-cells = <0>;
1380 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1381 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1383 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1391 reg = <0 0x00990000 0 0x4000>;
1395 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1399 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1400 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1407 reg = <0 0x00994000 0 0x4000>;
1411 pinctrl-0 = <&qup_i2c5_data_clk>;
1414 #size-cells = <0>;
1415 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1416 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1417 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1422 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1430 reg = <0 0x00994000 0 0x4000>;
1434 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1437 #size-cells = <0>;
1440 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1443 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1451 reg = <0 0x00994000 0 0x4000>;
1455 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
1459 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1460 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1467 reg = <0 0x00998000 0 0x4000>;
1471 pinctrl-0 = <&qup_i2c6_data_clk>;
1474 #size-cells = <0>;
1475 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1476 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1477 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1482 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1490 reg = <0 0x00998000 0 0x4000>;
1494 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1497 #size-cells = <0>;
1500 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1501 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1503 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1511 reg = <0 0x00998000 0 0x4000>;
1515 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1519 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1520 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1527 reg = <0 0x0099c000 0 0x4000>;
1531 pinctrl-0 = <&qup_i2c7_data_clk>;
1534 #size-cells = <0>;
1535 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1536 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1537 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1542 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1550 reg = <0 0x0099c000 0 0x4000>;
1554 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1557 #size-cells = <0>;
1560 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1561 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1563 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1571 reg = <0 0x0099c000 0 0x4000>;
1575 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1579 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1580 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1589 reg = <0 0x00a00000 0 0x60000>;
1603 dma-channel-mask = <0x1e>;
1604 iommus = <&apps_smmu 0x56 0x0>;
1610 reg = <0 0x00ac0000 0 0x2000>;
1617 iommus = <&apps_smmu 0x43 0x0>;
1622 reg = <0 0x00a80000 0 0x4000>;
1626 pinctrl-0 = <&qup_i2c8_data_clk>;
1629 #size-cells = <0>;
1630 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1631 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1632 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1637 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1638 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1645 reg = <0 0x00a80000 0 0x4000>;
1649 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1652 #size-cells = <0>;
1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1656 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1658 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1659 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1666 reg = <0 0x00a80000 0 0x4000>;
1670 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1674 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1675 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1682 reg = <0 0x00a84000 0 0x4000>;
1686 pinctrl-0 = <&qup_i2c9_data_clk>;
1689 #size-cells = <0>;
1690 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1691 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1692 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1697 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1705 reg = <0 0x00a84000 0 0x4000>;
1709 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1712 #size-cells = <0>;
1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1716 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1718 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1726 reg = <0 0x00a84000 0 0x4000>;
1730 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1734 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1735 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1742 reg = <0 0x00a88000 0 0x4000>;
1746 pinctrl-0 = <&qup_i2c10_data_clk>;
1749 #size-cells = <0>;
1750 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1751 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1752 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1757 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1765 reg = <0 0x00a88000 0 0x4000>;
1769 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1772 #size-cells = <0>;
1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1776 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1778 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1786 reg = <0 0x00a88000 0 0x4000>;
1790 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1794 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1795 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1802 reg = <0 0x00a8c000 0 0x4000>;
1806 pinctrl-0 = <&qup_i2c11_data_clk>;
1809 #size-cells = <0>;
1810 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1811 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1812 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1817 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1825 reg = <0 0x00a8c000 0 0x4000>;
1829 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1832 #size-cells = <0>;
1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1836 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1838 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1846 reg = <0 0x00a8c000 0 0x4000>;
1850 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1854 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1855 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1862 reg = <0 0x00a90000 0 0x4000>;
1866 pinctrl-0 = <&qup_i2c12_data_clk>;
1869 #size-cells = <0>;
1870 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1871 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1872 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1877 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1885 reg = <0 0x00a90000 0 0x4000>;
1889 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1892 #size-cells = <0>;
1895 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1896 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1898 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1906 reg = <0 0x00a90000 0 0x4000>;
1910 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1914 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1915 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1922 reg = <0 0x00a94000 0 0x4000>;
1926 pinctrl-0 = <&qup_i2c13_data_clk>;
1929 #size-cells = <0>;
1930 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1931 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1932 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1937 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1945 reg = <0 0x00a94000 0 0x4000>;
1949 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1952 #size-cells = <0>;
1955 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1956 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1958 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1966 reg = <0 0x00a94000 0 0x4000>;
1970 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1974 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1975 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1982 reg = <0 0x00a98000 0 0x4000>;
1986 pinctrl-0 = <&qup_i2c14_data_clk>;
1989 #size-cells = <0>;
1990 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1991 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1992 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1997 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2005 reg = <0 0x00a98000 0 0x4000>;
2009 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2012 #size-cells = <0>;
2015 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2016 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2018 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2026 reg = <0 0x00a98000 0 0x4000>;
2030 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
2034 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2035 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2042 reg = <0 0x00a9c000 0 0x4000>;
2046 pinctrl-0 = <&qup_i2c15_data_clk>;
2049 #size-cells = <0>;
2050 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2051 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
2052 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
2057 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2065 reg = <0 0x00a9c000 0 0x4000>;
2069 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2072 #size-cells = <0>;
2075 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2076 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2078 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2086 reg = <0 0x00a9c000 0 0x4000>;
2090 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2094 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2095 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2103 reg = <0 0x010d3000 0 0x1000>;
2107 reg = <0 0x01500000 0 0x1000>;
2114 reg = <0 0x01502000 0 0x1000>;
2121 reg = <0 0x01580000 0 0x4>;
2128 reg = <0 0x01680000 0 0x15480>;
2136 reg = <0 0x016e0000 0 0x1c080>;
2144 reg = <0 0x01700000 0 0x2b080>;
2152 reg = <0 0x01740000 0 0x1e080>;
2160 reg = <0 0x17a10040 0 0x0>;
2161 iommus = <&apps_smmu 0x1c00 0x1>;
2197 qcom,smem-states = <&wlan_smp2p_out 0>;
2203 reg = <0 0x01c08000 0 0x3000>,
2204 <0 0x40000000 0 0xf1d>,
2205 <0 0x40000f20 0 0xa8>,
2206 <0 0x40001000 0 0x1000>,
2207 <0 0x40100000 0 0x100000>;
2212 bus-range = <0x00 0xff>;
2218 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2219 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2232 interrupt-map-mask = <0 0 0 0x7>;
2233 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2234 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2235 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2236 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2278 pinctrl-0 = <&pcie1_clkreq_n>;
2282 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2283 <0x100 &apps_smmu 0x1c81 0x1>;
2287 pcie@0 {
2289 reg = <0x0 0x0 0x0 0x0 0x0>;
2290 bus-range = <0x01 0xff>;
2300 reg = <0 0x01c0e000 0 0x1000>;
2313 #clock-cells = <0>;
2315 #phy-cells = <0>;
2329 reg = <0x0 0x01d84000 0x0 0x3000>;
2341 iommus = <&apps_smmu 0x80 0x0>;
2368 <0 0>,
2369 <0 0>,
2371 <0 0>,
2372 <0 0>,
2373 <0 0>,
2374 <0 0>;
2382 reg = <0x0 0x01d87000 0x0 0xe00>;
2390 resets = <&ufs_mem_hc 0>;
2394 #phy-cells = <0>;
2402 reg = <0 0x01d88000 0 0x8000>;
2408 reg = <0x0 0x01dc4000 0x0 0x28000>;
2411 iommus = <&apps_smmu 0x4e4 0x0011>,
2412 <&apps_smmu 0x4e6 0x0011>;
2413 qcom,ee = <0>;
2421 reg = <0x0 0x01dfa000 0x0 0x6000>;
2424 iommus = <&apps_smmu 0x4e4 0x0011>,
2425 <&apps_smmu 0x4e4 0x0011>;
2426 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
2433 iommus = <&apps_smmu 0x480 0x0>,
2434 <&apps_smmu 0x482 0x0>;
2435 reg = <0 0x01e40000 0 0x8000>,
2436 <0 0x01e50000 0 0x4ad0>,
2437 <0 0x01e04000 0 0x23000>;
2444 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2454 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2455 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2461 qcom,smem-states = <&ipa_smp2p_out 0>,
2471 reg = <0 0x01f40000 0 0x20000>;
2477 reg = <0 0x01f60000 0 0x20000>;
2482 reg = <0 0x01fc0000 0 0x30000>;
2487 reg = <0 0x03000000 0 0x40>,
2488 <0 0x03c04000 0 0x4>;
2498 reg = <0 0x03200000 0 0x1000>;
2501 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2512 #clock-cells = <0>;
2520 reg = <0 0x03210000 0 0x2000>;
2526 qcom,din-ports = <0>;
2532 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2533 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2534 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2535 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2536 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2537 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2538 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2539 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2540 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2544 #size-cells = <0>;
2551 reg = <0 0x03220000 0 0x1000>;
2554 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2565 #clock-cells = <0>;
2573 reg = <0 0x03230000 0 0x2000>;
2581 qcom,dout-ports = <0>;
2586 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2587 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2588 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2589 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2590 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2591 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2592 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2593 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2594 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2598 #size-cells = <0>;
2605 reg = <0 0x03300000 0 0x30000>,
2606 <0 0x032a9000 0 0x1000>;
2618 reg = <0 0x03370000 0 0x1000>;
2621 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2630 #clock-cells = <0>;
2638 reg = <0 0x03380000 0 0x30000>;
2650 reg = <0 0x03900000 0 0x50000>;
2662 reg = <0 0x03987000 0 0x68000>,
2663 <0 0x03b00000 0 0x29000>,
2664 <0 0x03260000 0 0xc000>,
2665 <0 0x03280000 0 0x29000>,
2666 <0 0x03340000 0 0x29000>,
2667 <0 0x0336c000 0 0x3000>;
2675 iommus = <&apps_smmu 0x1820 0>,
2676 <&apps_smmu 0x1821 0>,
2677 <&apps_smmu 0x1832 0>;
2706 #size-cells = <0>;
2722 reg = <0 0x03a84000 0 0x20000>;
2729 iommus = <&apps_smmu 0x1826 0x0>;
2735 reg = <0 0x03ac0000 0 0x2c000>;
2739 iommus = <&apps_smmu 0x1826 0x0>;
2741 #size-cells = <0>;
2747 reg = <0 0x03c00000 0 0x28>;
2756 reg = <0 0x03c40000 0 0xf080>;
2764 reg = <0 0x033c0000 0x0 0x20000>,
2765 <0 0x03550000 0x0 0x10000>;
2768 gpio-ranges = <&lpass_tlmm 0 0 15>;
2813 reg = <0 0x03d00000 0 0x40000>,
2814 <0 0x03d9e000 0 0x1000>,
2815 <0 0x03d61000 0 0x800>;
2820 iommus = <&adreno_smmu 0 0x400>,
2821 <&adreno_smmu 1 0x400>;
2824 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2844 opp-supported-hw = <0x17>;
2851 opp-supported-hw = <0x17>;
2855 opp-550000000-0 {
2859 opp-supported-hw = <0x01>;
2866 opp-supported-hw = <0x16>;
2873 opp-supported-hw = <0x16>;
2880 opp-supported-hw = <0x06>;
2887 opp-supported-hw = <0x06>;
2894 opp-supported-hw = <0x02>;
2901 opp-supported-hw = <0x02>;
2908 reg = <0 0x03d6a000 0 0x34000>,
2909 <0 0x3de0000 0 0x10000>,
2910 <0 0x0b290000 0 0x10000>;
2933 iommus = <&adreno_smmu 5 0x400>;
2948 reg = <0 0x03d90000 0 0x9000>;
2962 reg = <0x0 0x0117f000 0x0 0x1000>,
2963 <0x0 0x01112000 0x0 0x6000>;
2969 reg = <0 0x03da0000 0 0x20000>;
3006 reg = <0x0 0x3dd9000 0x0 0x1000>;
3007 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
3012 reg = <0x0 0x3ddd000 0x0 0x1000>;
3013 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
3018 reg = <0 0x04080000 0 0x10000>;
3021 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3040 qcom,smem-states = <&modem_smp2p_out 0>;
3058 reg = <0 0x06002000 0 0x1000>,
3059 <0 0x16280000 0 0x180000>;
3076 reg = <0 0x06041000 0 0x1000>;
3091 #size-cells = <0>;
3104 reg = <0 0x06042000 0 0x1000>;
3119 #size-cells = <0>;
3132 reg = <0 0x06045000 0 0x1000>;
3147 #size-cells = <0>;
3149 port@0 {
3150 reg = <0>;
3167 reg = <0 0x06046000 0 0x1000>;
3191 reg = <0 0x06048000 0 0x1000>;
3192 iommus = <&apps_smmu 0x04c0 0>;
3209 reg = <0 0x06b04000 0 0x1000>;
3224 #size-cells = <0>;
3237 reg = <0 0x06b05000 0 0x1000>;
3261 reg = <0 0x06b06000 0 0x1000>;
3286 reg = <0 0x07040000 0 0x1000>;
3306 reg = <0 0x07140000 0 0x1000>;
3326 reg = <0 0x07240000 0 0x1000>;
3346 reg = <0 0x07340000 0 0x1000>;
3366 reg = <0 0x07440000 0 0x1000>;
3386 reg = <0 0x07540000 0 0x1000>;
3406 reg = <0 0x07640000 0 0x1000>;
3426 reg = <0 0x07740000 0 0x1000>;
3446 reg = <0 0x07800000 0 0x1000>;
3461 #size-cells = <0>;
3463 port@0 {
3464 reg = <0>;
3523 reg = <0 0x07810000 0 0x1000>;
3548 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3552 reg = <0 0x08804000 0 0x1000>;
3554 iommus = <&apps_smmu 0x100 0x0>;
3563 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3572 qcom,dll-config = <0x0007642c>;
3583 opp-avg-kBps = <100000 0>;
3590 opp-avg-kBps = <200000 0>;
3598 reg = <0 0x088e3000 0 0x400>;
3600 #phy-cells = <0>;
3611 reg = <0 0x088e4000 0 0x400>;
3613 #phy-cells = <0>;
3623 reg = <0 0x088e8000 0 0x3000>;
3644 #size-cells = <0>;
3646 port@0 {
3647 reg = <0>;
3671 reg = <0 0x08cf8800 0 0x400>;
3707 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3708 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3713 reg = <0 0x08c00000 0 0xe000>;
3715 iommus = <&apps_smmu 0xa0 0x0>;
3735 reg = <0 0x088dc000 0 0x1000>;
3736 iommus = <&apps_smmu 0x20 0x0>;
3738 #size-cells = <0>;
3743 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3744 &cnoc2 SLAVE_QSPI_0 0>;
3753 reg = <0 0x03700000 0 0x100>;
3756 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3775 qcom,smem-states = <&adsp_smp2p_out 0>;
3796 #size-cells = <0>;
3812 #size-cells = <0>;
3830 #size-cells = <0>;
3832 iommus = <&apps_smmu 0x1801 0x0>;
3834 dai@0 {
3835 reg = <0>;
3855 #sound-dai-cells = <0>;
3866 #size-cells = <0>;
3871 iommus = <&apps_smmu 0x1803 0x0>;
3877 iommus = <&apps_smmu 0x1804 0x0>;
3883 iommus = <&apps_smmu 0x1805 0x0>;
3891 reg = <0 0x08a00000 0 0x10000>;
3894 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3913 qcom,smem-states = <&wpss_smp2p_out 0>;
3933 reg = <0 0x09091000 0 0x1000>;
3944 opp-0 {
3973 reg = <0 0x090b6400 0 0x600>;
3983 opp-0 {
4008 reg = <0 0x090e0000 0 0x5080>;
4015 reg = <0 0x09100000 0 0xe2200>;
4023 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
4024 <0 0x09600000 0 0x58000>;
4031 reg = <0 0x88e0000 0 0x2000>,
4032 <0 0x88e2000 0 0x1000>;
4039 #size-cells = <0>;
4041 port@0 {
4042 reg = <0>;
4051 reg = <0 0x0a0c0000 0 0x10000>;
4059 reg = <0 0x0a300000 0 0x10000>;
4062 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4077 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4083 qcom,smem-states = <&cdsp_smp2p_out 0>;
4104 #size-cells = <0>;
4109 iommus = <&apps_smmu 0x11a1 0x0420>,
4110 <&apps_smmu 0x1181 0x0420>;
4116 iommus = <&apps_smmu 0x11a2 0x0420>,
4117 <&apps_smmu 0x1182 0x0420>;
4123 iommus = <&apps_smmu 0x11a3 0x0420>,
4124 <&apps_smmu 0x1183 0x0420>;
4130 iommus = <&apps_smmu 0x11a4 0x0420>,
4131 <&apps_smmu 0x1184 0x0420>;
4137 iommus = <&apps_smmu 0x11a5 0x0420>,
4138 <&apps_smmu 0x1185 0x0420>;
4144 iommus = <&apps_smmu 0x11a6 0x0420>,
4145 <&apps_smmu 0x1186 0x0420>;
4151 iommus = <&apps_smmu 0x11a7 0x0420>,
4152 <&apps_smmu 0x1187 0x0420>;
4158 iommus = <&apps_smmu 0x11a8 0x0420>,
4159 <&apps_smmu 0x1188 0x0420>;
4167 iommus = <&apps_smmu 0x11ab 0x0420>,
4168 <&apps_smmu 0x118b 0x0420>;
4174 iommus = <&apps_smmu 0x11ac 0x0420>,
4175 <&apps_smmu 0x118c 0x0420>;
4181 iommus = <&apps_smmu 0x11ad 0x0420>,
4182 <&apps_smmu 0x118d 0x0420>;
4188 iommus = <&apps_smmu 0x11ae 0x0420>,
4189 <&apps_smmu 0x118e 0x0420>;
4197 reg = <0 0x0a6f8800 0 0x400>;
4235 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4236 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
4243 reg = <0 0x0a600000 0 0xe000>;
4245 iommus = <&apps_smmu 0xe0 0x0>;
4257 #size-cells = <0>;
4259 port@0 {
4260 reg = <0>;
4278 reg = <0 0x0aa00000 0 0xd0600>;
4295 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
4296 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
4299 iommus = <&apps_smmu 0x2180 0x20>;
4344 reg = <0 0x0aaf0000 0 0x10000>;
4355 reg = <0 0x0ac4a000 0 0x1000>;
4369 pinctrl-0 = <&cci0_default &cci1_default>;
4374 #size-cells = <0>;
4378 cci0_i2c0: i2c-bus@0 {
4379 reg = <0>;
4382 #size-cells = <0>;
4389 #size-cells = <0>;
4395 reg = <0 0x0ac4b000 0 0x1000>;
4409 pinctrl-0 = <&cci2_default &cci3_default>;
4414 #size-cells = <0>;
4418 cci1_i2c0: i2c-bus@0 {
4419 reg = <0>;
4422 #size-cells = <0>;
4429 #size-cells = <0>;
4435 reg = <0 0x0ad00000 0 0x10000>;
4447 reg = <0 0x0af00000 0 0x20000>;
4450 <&mdss_dsi_phy 0>,
4454 <&mdss_edp_phy 0>,
4471 reg = <0 0x0ae00000 0 0x1000>;
4494 iommus = <&apps_smmu 0x900 0x402>;
4504 reg = <0 0x0ae01000 0 0x8f030>,
4505 <0 0x0aeb0000 0 0x2008>;
4528 interrupts = <0>;
4532 #size-cells = <0>;
4534 port@0 {
4535 reg = <0>;
4589 reg = <0 0x0ae94000 0 0x400>;
4609 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4617 #size-cells = <0>;
4623 #size-cells = <0>;
4625 port@0 {
4626 reg = <0>;
4661 reg = <0 0x0ae94400 0 0x200>,
4662 <0 0x0ae94600 0 0x280>,
4663 <0 0x0ae94900 0 0x280>;
4669 #phy-cells = <0>;
4681 pinctrl-0 = <&edp_hot_plug_det>;
4683 reg = <0 0x0aea0000 0 0x200>,
4684 <0 0x0aea0200 0 0x200>,
4685 <0 0x0aea0400 0 0xc00>,
4686 <0 0x0aea1000 0 0x400>;
4703 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4715 #size-cells = <0>;
4717 port@0 {
4718 reg = <0>;
4758 reg = <0 0x0aec2a00 0 0x19c>,
4759 <0 0x0aec2200 0 0xa0>,
4760 <0 0x0aec2600 0 0xa0>,
4761 <0 0x0aec2000 0 0x1c0>;
4769 #phy-cells = <0>;
4777 reg = <0 0x0ae90000 0 0x200>,
4778 <0 0x0ae90200 0 0x200>,
4779 <0 0x0ae90400 0 0xc00>,
4780 <0 0x0ae91000 0 0x400>,
4781 <0 0x0ae91400 0 0x400>;
4806 #sound-dai-cells = <0>;
4812 #size-cells = <0>;
4814 port@0 {
4815 reg = <0>;
4855 reg = <0 0x0b220000 0 0x30000>;
4856 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4868 reg = <0 0x0b5e0000 0 0x20000>;
4875 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4876 <0 0x0c222000 0 0x1ff>; /* SROT */
4886 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4887 <0 0x0c223000 0 0x1ff>; /* SROT */
4897 reg = <0 0x0c2a0000 0 0x31000>;
4903 reg = <0 0x0c300000 0 0x400>;
4910 #clock-cells = <0>;
4915 reg = <0 0x0c3f0000 0 0x400>;
4920 reg = <0 0x0c440000 0 0x1100>,
4921 <0 0x0c600000 0 0x2000000>,
4922 <0 0x0e600000 0 0x100000>,
4923 <0 0x0e700000 0 0xa0000>,
4924 <0 0x0c40a000 0 0x26000>;
4928 qcom,ee = <0>;
4929 qcom,channel = <0>;
4931 #size-cells = <0>;
4938 reg = <0 0x0f100000 0 0x300000>;
4944 gpio-ranges = <&tlmm 0 0 175>;
5791 reg = <0 0x146a5000 0 0x6000>;
5796 ranges = <0 0 0x146a5000 0x6000>;
5800 reg = <0x594c 0xc8>;
5806 reg = <0 0x15000000 0 0x100000>;
5895 reg = <0x0 0x151dd000 0x0 0x1000>;
5898 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
5903 reg = <0x0 0x151e1000 0x0 0x1000>;
5906 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
5911 reg = <0x0 0x151e5000 0x0 0x1000>;
5915 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
5920 reg = <0x0 0x151e9000 0x0 0x1000>;
5924 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
5929 reg = <0x0 0x151ed000 0x0 0x1000>;
5933 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
5938 reg = <0x0 0x151f1000 0x0 0x1000>;
5942 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
5947 reg = <0x0 0x151f5000 0x0 0x1000>;
5950 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
5955 reg = <0x0 0x151f9000 0x0 0x1000>;
5958 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
5963 reg = <0x0 0x151fd000 0x0 0x1000>;
5967 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
5972 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5973 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5983 reg = <0 0x17a40000 0 0x20000>;
5992 reg = <0 0x17c10000 0 0x1000>;
5994 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6001 ranges = <0 0 0 0x20000000>;
6003 reg = <0 0x17c20000 0 0x1000>;
6006 frame-number = <0>;
6009 reg = <0x17c21000 0x1000>,
6010 <0x17c22000 0x1000>;
6016 reg = <0x17c23000 0x1000>;
6023 reg = <0x17c25000 0x1000>;
6030 reg = <0x17c27000 0x1000>;
6037 reg = <0x17c29000 0x1000>;
6044 reg = <0x17c2b000 0x1000>;
6051 reg = <0x17c2d000 0x1000>;
6058 reg = <0 0x18200000 0 0x10000>,
6059 <0 0x18210000 0 0x10000>,
6060 <0 0x18220000 0 0x10000>;
6061 reg-names = "drv-0", "drv-1", "drv-2";
6065 qcom,tcs-offset = <0xd00>;
6133 reg = <0 0x18590000 0 0x1000>;
6141 reg = <0 0x18591000 0 0x1000>,
6142 <0 0x18592000 0 0x1000>,
6143 <0 0x18593000 0 0x1000>;
6148 interrupt-names = "dcvsh-irq-0",
6183 hysteresis = <0>;
6226 hysteresis = <0>;
6269 hysteresis = <0>;
6312 hysteresis = <0>;
6355 hysteresis = <0>;
6398 hysteresis = <0>;
6441 hysteresis = <0>;
6484 hysteresis = <0>;
6527 hysteresis = <0>;
6570 hysteresis = <0>;
6613 hysteresis = <0>;
6656 hysteresis = <0>;
6680 polling-delay-passive = <0>;
6682 thermal-sensors = <&tsens0 0>;
6693 hysteresis = <0>;
6700 polling-delay-passive = <0>;
6702 thermal-sensors = <&tsens1 0>;
6713 hysteresis = <0>;
6720 polling-delay-passive = <0>;
6732 hysteresis = <0>;
6739 polling-delay-passive = <0>;
6751 hysteresis = <0>;
6771 hysteresis = <0>;
6798 hysteresis = <0>;
6823 hysteresis = <0>;
6841 hysteresis = <0>;
6859 hysteresis = <0>;
6877 hysteresis = <0>;
6895 hysteresis = <0>;
6913 hysteresis = <0>;
6931 hysteresis = <0>;
6949 hysteresis = <0>;
6967 hysteresis = <0>;