Lines Matching +full:gcc +full:- +full:sc7280

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * sc7280 fragment for devices with Chrome bootloader
20 /delete-node/ &cdsp_mem;
21 /delete-node/ &domain_idle_states;
22 /delete-node/ &gpu_zap_mem;
23 /delete-node/ &gpu_zap_shader;
24 /delete-node/ &hyp_mem;
25 /delete-node/ &xbl_mem;
26 /delete-node/ &reserved_xbl_uefi_log;
27 /delete-node/ &sec_apps_mem;
31 		domain_idle_states: domain-idle-states {
32 			cluster_sleep_0: cluster-sleep-0 {
33 				compatible = "domain-idle-state";
34 				arm,psci-suspend-param = <0x40003444>;
35 				entry-latency-us = <2752>;
36 				exit-latency-us = <6562>;
37 				min-residency-us = <9926>;
42 	reserved-memory {
45 			no-map;
50 			no-map;
56 	domain-idle-states = <&cluster_sleep_0>;
97 	pinctrl-names = "default", "sleep";
98 	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
99 	pinctrl-1 = <&qspi_sleep>;
102 		compatible = "jedec,spi-nor";
105 		spi-max-frequency = <37500000>;
106 		spi-tx-bus-width = <2>;
107 		spi-rx-bus-width = <2>;
113 	/delete-property/ memory-region;
117 	compatible = "qcom,sc7280-wpss-pil";
118 	clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
119 		 <&gcc GCC_WPSS_AHB_CLK>,
120 		 <&gcc GCC_WPSS_RSCP_CLK>,
122 	clock-names = "ahb_bdg",
129 	reset-names = "restart", "pdc_sync";
131 	qcom,halt-regs = <&tcsr_1 0x17000>;
133 	firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
139 	/* TF-A firmware maps memory cached so mark dma-coherent to match. */
140 	dma-coherent;
149 	video-firmware {
161 	wifi-firmware {
166 /* PINCTRL - chrome-common pinctrl */
169 	qspi_sleep: qspi-sleep-state {
177 		 * that we don't need the reverse (output-enable) in the
178 		 * normal mode since the "output-enable" only matters for
182 		output-disable;