Lines Matching +full:i2c +full:- +full:qup +full:- +full:v2
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h>
26 #include <dt-bindings/sound/qcom,q6afe.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
63 xo_board: xo-board {
64 compatible = "fixed-clock";
65 clock-frequency = <38400000>;
66 #clock-cells = <0>;
69 sleep_clk: sleep-clk {
70 compatible = "fixed-clock";
71 clock-frequency = <32764>;
72 #clock-cells = <0>;
77 #address-cells = <2>;
78 #size-cells = <0>;
85 enable-method = "psci";
86 power-domains = <&cpu_pd0>;
87 power-domain-names = "psci";
88 capacity-dmips-mhz = <415>;
89 dynamic-power-coefficient = <137>;
90 operating-points-v2 = <&cpu0_opp_table>;
93 next-level-cache = <&l2_0>;
94 #cooling-cells = <2>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
96 l2_0: l2-cache {
98 cache-level = <2>;
99 cache-unified;
100 next-level-cache = <&l3_0>;
101 l3_0: l3-cache {
103 cache-level = <3>;
104 cache-unified;
114 enable-method = "psci";
115 power-domains = <&cpu_pd1>;
116 power-domain-names = "psci";
117 capacity-dmips-mhz = <415>;
118 dynamic-power-coefficient = <137>;
119 next-level-cache = <&l2_100>;
120 operating-points-v2 = <&cpu0_opp_table>;
123 #cooling-cells = <2>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 l2_100: l2-cache {
127 cache-level = <2>;
128 cache-unified;
129 next-level-cache = <&l3_0>;
138 enable-method = "psci";
139 power-domains = <&cpu_pd2>;
140 power-domain-names = "psci";
141 capacity-dmips-mhz = <415>;
142 dynamic-power-coefficient = <137>;
143 next-level-cache = <&l2_200>;
144 operating-points-v2 = <&cpu0_opp_table>;
147 #cooling-cells = <2>;
148 qcom,freq-domain = <&cpufreq_hw 0>;
149 l2_200: l2-cache {
151 cache-level = <2>;
152 cache-unified;
153 next-level-cache = <&l3_0>;
162 enable-method = "psci";
163 power-domains = <&cpu_pd3>;
164 power-domain-names = "psci";
165 capacity-dmips-mhz = <415>;
166 dynamic-power-coefficient = <137>;
167 next-level-cache = <&l2_300>;
168 operating-points-v2 = <&cpu0_opp_table>;
171 #cooling-cells = <2>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
173 l2_300: l2-cache {
175 cache-level = <2>;
176 cache-unified;
177 next-level-cache = <&l3_0>;
186 enable-method = "psci";
187 power-domains = <&cpu_pd4>;
188 power-domain-names = "psci";
189 capacity-dmips-mhz = <415>;
190 dynamic-power-coefficient = <137>;
191 next-level-cache = <&l2_400>;
192 operating-points-v2 = <&cpu0_opp_table>;
195 #cooling-cells = <2>;
196 qcom,freq-domain = <&cpufreq_hw 0>;
197 l2_400: l2-cache {
199 cache-level = <2>;
200 cache-unified;
201 next-level-cache = <&l3_0>;
210 enable-method = "psci";
211 power-domains = <&cpu_pd5>;
212 power-domain-names = "psci";
213 capacity-dmips-mhz = <415>;
214 dynamic-power-coefficient = <137>;
215 next-level-cache = <&l2_500>;
216 operating-points-v2 = <&cpu0_opp_table>;
219 #cooling-cells = <2>;
220 qcom,freq-domain = <&cpufreq_hw 0>;
221 l2_500: l2-cache {
223 cache-level = <2>;
224 cache-unified;
225 next-level-cache = <&l3_0>;
234 enable-method = "psci";
235 power-domains = <&cpu_pd6>;
236 power-domain-names = "psci";
237 capacity-dmips-mhz = <1024>;
238 dynamic-power-coefficient = <480>;
239 next-level-cache = <&l2_600>;
240 operating-points-v2 = <&cpu6_opp_table>;
243 #cooling-cells = <2>;
244 qcom,freq-domain = <&cpufreq_hw 1>;
245 l2_600: l2-cache {
247 cache-level = <2>;
248 cache-unified;
249 next-level-cache = <&l3_0>;
258 enable-method = "psci";
259 power-domains = <&cpu_pd7>;
260 power-domain-names = "psci";
261 capacity-dmips-mhz = <1024>;
262 dynamic-power-coefficient = <480>;
263 next-level-cache = <&l2_700>;
264 operating-points-v2 = <&cpu6_opp_table>;
267 #cooling-cells = <2>;
268 qcom,freq-domain = <&cpufreq_hw 1>;
269 l2_700: l2-cache {
271 cache-level = <2>;
272 cache-unified;
273 next-level-cache = <&l3_0>;
277 cpu-map {
313 idle_states: idle-states {
314 entry-method = "psci";
316 little_cpu_sleep_0: cpu-sleep-0-0 {
317 compatible = "arm,idle-state";
318 idle-state-name = "little-power-down";
319 arm,psci-suspend-param = <0x40000003>;
320 entry-latency-us = <549>;
321 exit-latency-us = <901>;
322 min-residency-us = <1774>;
323 local-timer-stop;
326 little_cpu_sleep_1: cpu-sleep-0-1 {
327 compatible = "arm,idle-state";
328 idle-state-name = "little-rail-power-down";
329 arm,psci-suspend-param = <0x40000004>;
330 entry-latency-us = <702>;
331 exit-latency-us = <915>;
332 min-residency-us = <4001>;
333 local-timer-stop;
336 big_cpu_sleep_0: cpu-sleep-1-0 {
337 compatible = "arm,idle-state";
338 idle-state-name = "big-power-down";
339 arm,psci-suspend-param = <0x40000003>;
340 entry-latency-us = <523>;
341 exit-latency-us = <1244>;
342 min-residency-us = <2207>;
343 local-timer-stop;
346 big_cpu_sleep_1: cpu-sleep-1-1 {
347 compatible = "arm,idle-state";
348 idle-state-name = "big-rail-power-down";
349 arm,psci-suspend-param = <0x40000004>;
350 entry-latency-us = <526>;
351 exit-latency-us = <1854>;
352 min-residency-us = <5555>;
353 local-timer-stop;
357 domain_idle_states: domain-idle-states {
358 cluster_sleep_pc: cluster-sleep-0 {
359 compatible = "domain-idle-state";
360 arm,psci-suspend-param = <0x41000044>;
361 entry-latency-us = <2752>;
362 exit-latency-us = <3048>;
363 min-residency-us = <6118>;
366 cluster_sleep_cx_ret: cluster-sleep-1 {
367 compatible = "domain-idle-state";
368 arm,psci-suspend-param = <0x41001244>;
369 entry-latency-us = <3638>;
370 exit-latency-us = <4562>;
371 min-residency-us = <8467>;
374 cluster_aoss_sleep: cluster-sleep-2 {
375 compatible = "domain-idle-state";
376 arm,psci-suspend-param = <0x4100b244>;
377 entry-latency-us = <3263>;
378 exit-latency-us = <6562>;
379 min-residency-us = <9826>;
386 compatible = "qcom,scm-sc7180", "qcom,scm";
396 cpu0_opp_table: opp-table-cpu0 {
397 compatible = "operating-points-v2";
398 opp-shared;
400 cpu0_opp1: opp-300000000 {
401 opp-hz = /bits/ 64 <300000000>;
402 opp-peak-kBps = <1200000 4800000>;
405 cpu0_opp2: opp-576000000 {
406 opp-hz = /bits/ 64 <576000000>;
407 opp-peak-kBps = <1200000 4800000>;
410 cpu0_opp3: opp-768000000 {
411 opp-hz = /bits/ 64 <768000000>;
412 opp-peak-kBps = <1200000 4800000>;
415 cpu0_opp4: opp-1017600000 {
416 opp-hz = /bits/ 64 <1017600000>;
417 opp-peak-kBps = <1804000 8908800>;
420 cpu0_opp5: opp-1248000000 {
421 opp-hz = /bits/ 64 <1248000000>;
422 opp-peak-kBps = <2188000 12902400>;
425 cpu0_opp6: opp-1324800000 {
426 opp-hz = /bits/ 64 <1324800000>;
427 opp-peak-kBps = <2188000 12902400>;
430 cpu0_opp7: opp-1516800000 {
431 opp-hz = /bits/ 64 <1516800000>;
432 opp-peak-kBps = <3072000 15052800>;
435 cpu0_opp8: opp-1612800000 {
436 opp-hz = /bits/ 64 <1612800000>;
437 opp-peak-kBps = <3072000 15052800>;
440 cpu0_opp9: opp-1708800000 {
441 opp-hz = /bits/ 64 <1708800000>;
442 opp-peak-kBps = <3072000 15052800>;
445 cpu0_opp10: opp-1804800000 {
446 opp-hz = /bits/ 64 <1804800000>;
447 opp-peak-kBps = <4068000 22425600>;
451 cpu6_opp_table: opp-table-cpu6 {
452 compatible = "operating-points-v2";
453 opp-shared;
455 cpu6_opp1: opp-300000000 {
456 opp-hz = /bits/ 64 <300000000>;
457 opp-peak-kBps = <2188000 8908800>;
460 cpu6_opp2: opp-652800000 {
461 opp-hz = /bits/ 64 <652800000>;
462 opp-peak-kBps = <2188000 8908800>;
465 cpu6_opp3: opp-825600000 {
466 opp-hz = /bits/ 64 <825600000>;
467 opp-peak-kBps = <2188000 8908800>;
470 cpu6_opp4: opp-979200000 {
471 opp-hz = /bits/ 64 <979200000>;
472 opp-peak-kBps = <2188000 8908800>;
475 cpu6_opp5: opp-1113600000 {
476 opp-hz = /bits/ 64 <1113600000>;
477 opp-peak-kBps = <2188000 8908800>;
480 cpu6_opp6: opp-1267200000 {
481 opp-hz = /bits/ 64 <1267200000>;
482 opp-peak-kBps = <4068000 12902400>;
485 cpu6_opp7: opp-1555200000 {
486 opp-hz = /bits/ 64 <1555200000>;
487 opp-peak-kBps = <4068000 15052800>;
490 cpu6_opp8: opp-1708800000 {
491 opp-hz = /bits/ 64 <1708800000>;
492 opp-peak-kBps = <6220000 19353600>;
495 cpu6_opp9: opp-1843200000 {
496 opp-hz = /bits/ 64 <1843200000>;
497 opp-peak-kBps = <6220000 19353600>;
500 cpu6_opp10: opp-1900800000 {
501 opp-hz = /bits/ 64 <1900800000>;
502 opp-peak-kBps = <6220000 22425600>;
505 cpu6_opp11: opp-1996800000 {
506 opp-hz = /bits/ 64 <1996800000>;
507 opp-peak-kBps = <6220000 22425600>;
510 cpu6_opp12: opp-2112000000 {
511 opp-hz = /bits/ 64 <2112000000>;
512 opp-peak-kBps = <6220000 22425600>;
515 cpu6_opp13: opp-2208000000 {
516 opp-hz = /bits/ 64 <2208000000>;
517 opp-peak-kBps = <7216000 22425600>;
520 cpu6_opp14: opp-2323200000 {
521 opp-hz = /bits/ 64 <2323200000>;
522 opp-peak-kBps = <7216000 22425600>;
525 cpu6_opp15: opp-2400000000 {
526 opp-hz = /bits/ 64 <2400000000>;
527 opp-peak-kBps = <8532000 23347200>;
530 cpu6_opp16: opp-2553600000 {
531 opp-hz = /bits/ 64 <2553600000>;
532 opp-peak-kBps = <8532000 23347200>;
536 qspi_opp_table: opp-table-qspi {
537 compatible = "operating-points-v2";
539 opp-75000000 {
540 opp-hz = /bits/ 64 <75000000>;
541 required-opps = <&rpmhpd_opp_low_svs>;
544 opp-150000000 {
545 opp-hz = /bits/ 64 <150000000>;
546 required-opps = <&rpmhpd_opp_svs>;
549 opp-300000000 {
550 opp-hz = /bits/ 64 <300000000>;
551 required-opps = <&rpmhpd_opp_nom>;
555 qup_opp_table: opp-table-qup {
556 compatible = "operating-points-v2";
558 opp-75000000 {
559 opp-hz = /bits/ 64 <75000000>;
560 required-opps = <&rpmhpd_opp_low_svs>;
563 opp-100000000 {
564 opp-hz = /bits/ 64 <100000000>;
565 required-opps = <&rpmhpd_opp_svs>;
568 opp-128000000 {
569 opp-hz = /bits/ 64 <128000000>;
570 required-opps = <&rpmhpd_opp_nom>;
575 compatible = "arm,armv8-pmuv3";
580 compatible = "arm,psci-1.0";
583 cpu_pd0: power-domain-cpu0 {
584 #power-domain-cells = <0>;
585 power-domains = <&cluster_pd>;
586 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
589 cpu_pd1: power-domain-cpu1 {
590 #power-domain-cells = <0>;
591 power-domains = <&cluster_pd>;
592 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
595 cpu_pd2: power-domain-cpu2 {
596 #power-domain-cells = <0>;
597 power-domains = <&cluster_pd>;
598 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
601 cpu_pd3: power-domain-cpu3 {
602 #power-domain-cells = <0>;
603 power-domains = <&cluster_pd>;
604 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
607 cpu_pd4: power-domain-cpu4 {
608 #power-domain-cells = <0>;
609 power-domains = <&cluster_pd>;
610 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
613 cpu_pd5: power-domain-cpu5 {
614 #power-domain-cells = <0>;
615 power-domains = <&cluster_pd>;
616 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
619 cpu_pd6: power-domain-cpu6 {
620 #power-domain-cells = <0>;
621 power-domains = <&cluster_pd>;
622 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
625 cpu_pd7: power-domain-cpu7 {
626 #power-domain-cells = <0>;
627 power-domains = <&cluster_pd>;
628 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
631 cluster_pd: power-domain-cluster {
632 #power-domain-cells = <0>;
633 domain-idle-states = <&cluster_sleep_pc
639 reserved_memory: reserved-memory {
640 #address-cells = <2>;
641 #size-cells = <2>;
646 no-map;
651 no-map;
656 no-map;
661 compatible = "qcom,cmd-db";
662 no-map;
667 no-map;
672 no-map;
677 no-map;
682 no-map;
686 compatible = "qcom,rmtfs-mem";
688 no-map;
690 qcom,client-id = <1>;
697 memory-region = <&smem_mem>;
701 smp2p-cdsp {
709 qcom,local-pid = <0>;
710 qcom,remote-pid = <5>;
712 cdsp_smp2p_out: master-kernel {
713 qcom,entry-name = "master-kernel";
714 #qcom,smem-state-cells = <1>;
717 cdsp_smp2p_in: slave-kernel {
718 qcom,entry-name = "slave-kernel";
720 interrupt-controller;
721 #interrupt-cells = <2>;
725 smp2p-lpass {
733 qcom,local-pid = <0>;
734 qcom,remote-pid = <2>;
736 adsp_smp2p_out: master-kernel {
737 qcom,entry-name = "master-kernel";
738 #qcom,smem-state-cells = <1>;
741 adsp_smp2p_in: slave-kernel {
742 qcom,entry-name = "slave-kernel";
744 interrupt-controller;
745 #interrupt-cells = <2>;
749 smp2p-mpss {
754 qcom,local-pid = <0>;
755 qcom,remote-pid = <1>;
757 modem_smp2p_out: master-kernel {
758 qcom,entry-name = "master-kernel";
759 #qcom,smem-state-cells = <1>;
762 modem_smp2p_in: slave-kernel {
763 qcom,entry-name = "slave-kernel";
764 interrupt-controller;
765 #interrupt-cells = <2>;
768 ipa_smp2p_out: ipa-ap-to-modem {
769 qcom,entry-name = "ipa";
770 #qcom,smem-state-cells = <1>;
773 ipa_smp2p_in: ipa-modem-to-ap {
774 qcom,entry-name = "ipa";
775 interrupt-controller;
776 #interrupt-cells = <2>;
781 #address-cells = <2>;
782 #size-cells = <2>;
784 dma-ranges = <0 0 0 0 0x10 0>;
785 compatible = "simple-bus";
787 gcc: clock-controller@100000 {
788 compatible = "qcom,gcc-sc7180";
793 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
794 #clock-cells = <1>;
795 #reset-cells = <1>;
796 #power-domain-cells = <1>;
797 power-domains = <&rpmhpd SC7180_CX>;
801 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
808 clock-names = "core";
809 #address-cells = <1>;
810 #size-cells = <1>;
812 qusb2p_hstx_trim: hstx-trim-primary@25b {
817 gpu_speed_bin: gpu-speed-bin@1d2 {
824 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
827 reg-names = "hc", "cqhci";
832 interrupt-names = "hc_irq", "pwr_irq";
837 clock-names = "iface", "core", "xo";
840 interconnect-names = "sdhc-ddr","cpu-sdhc";
841 power-domains = <&rpmhpd SC7180_CX>;
842 operating-points-v2 = <&sdhc1_opp_table>;
844 bus-width = <8>;
845 non-removable;
846 supports-cqe;
848 mmc-ddr-1_8v;
849 mmc-hs200-1_8v;
850 mmc-hs400-1_8v;
851 mmc-hs400-enhanced-strobe;
855 sdhc1_opp_table: opp-table {
856 compatible = "operating-points-v2";
858 opp-100000000 {
859 opp-hz = /bits/ 64 <100000000>;
860 required-opps = <&rpmhpd_opp_low_svs>;
861 opp-peak-kBps = <1800000 600000>;
862 opp-avg-kBps = <100000 0>;
865 opp-384000000 {
866 opp-hz = /bits/ 64 <384000000>;
867 required-opps = <&rpmhpd_opp_nom>;
868 opp-peak-kBps = <5400000 1600000>;
869 opp-avg-kBps = <390000 0>;
875 compatible = "qcom,geni-se-qup";
877 clock-names = "m-ahb", "s-ahb";
880 #address-cells = <2>;
881 #size-cells = <2>;
886 i2c0: i2c@880000 {
887 compatible = "qcom,geni-i2c";
889 clock-names = "se";
891 pinctrl-names = "default";
892 pinctrl-0 = <&qup_i2c0_default>;
894 #address-cells = <1>;
895 #size-cells = <0>;
899 interconnect-names = "qup-core", "qup-config",
900 "qup-memory";
901 power-domains = <&rpmhpd SC7180_CX>;
902 required-opps = <&rpmhpd_opp_low_svs>;
907 compatible = "qcom,geni-spi";
909 clock-names = "se";
911 pinctrl-names = "default";
912 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
914 #address-cells = <1>;
915 #size-cells = <0>;
916 power-domains = <&rpmhpd SC7180_CX>;
917 operating-points-v2 = <&qup_opp_table>;
920 interconnect-names = "qup-core", "qup-config";
925 compatible = "qcom,geni-uart";
927 clock-names = "se";
929 pinctrl-names = "default";
930 pinctrl-0 = <&qup_uart0_default>;
932 power-domains = <&rpmhpd SC7180_CX>;
933 operating-points-v2 = <&qup_opp_table>;
936 interconnect-names = "qup-core", "qup-config";
940 i2c1: i2c@884000 {
941 compatible = "qcom,geni-i2c";
943 clock-names = "se";
945 pinctrl-names = "default";
946 pinctrl-0 = <&qup_i2c1_default>;
948 #address-cells = <1>;
949 #size-cells = <0>;
953 interconnect-names = "qup-core", "qup-config",
954 "qup-memory";
955 power-domains = <&rpmhpd SC7180_CX>;
956 required-opps = <&rpmhpd_opp_low_svs>;
961 compatible = "qcom,geni-spi";
963 clock-names = "se";
965 pinctrl-names = "default";
966 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
968 #address-cells = <1>;
969 #size-cells = <0>;
970 power-domains = <&rpmhpd SC7180_CX>;
971 operating-points-v2 = <&qup_opp_table>;
974 interconnect-names = "qup-core", "qup-config";
979 compatible = "qcom,geni-uart";
981 clock-names = "se";
983 pinctrl-names = "default";
984 pinctrl-0 = <&qup_uart1_default>;
986 power-domains = <&rpmhpd SC7180_CX>;
987 operating-points-v2 = <&qup_opp_table>;
990 interconnect-names = "qup-core", "qup-config";
994 i2c2: i2c@888000 {
995 compatible = "qcom,geni-i2c";
997 clock-names = "se";
999 pinctrl-names = "default";
1000 pinctrl-0 = <&qup_i2c2_default>;
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1007 interconnect-names = "qup-core", "qup-config",
1008 "qup-memory";
1009 power-domains = <&rpmhpd SC7180_CX>;
1010 required-opps = <&rpmhpd_opp_low_svs>;
1015 compatible = "qcom,geni-uart";
1017 clock-names = "se";
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&qup_uart2_default>;
1022 power-domains = <&rpmhpd SC7180_CX>;
1023 operating-points-v2 = <&qup_opp_table>;
1026 interconnect-names = "qup-core", "qup-config";
1030 i2c3: i2c@88c000 {
1031 compatible = "qcom,geni-i2c";
1033 clock-names = "se";
1035 pinctrl-names = "default";
1036 pinctrl-0 = <&qup_i2c3_default>;
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1043 interconnect-names = "qup-core", "qup-config",
1044 "qup-memory";
1045 power-domains = <&rpmhpd SC7180_CX>;
1046 required-opps = <&rpmhpd_opp_low_svs>;
1051 compatible = "qcom,geni-spi";
1053 clock-names = "se";
1055 pinctrl-names = "default";
1056 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 power-domains = <&rpmhpd SC7180_CX>;
1061 operating-points-v2 = <&qup_opp_table>;
1064 interconnect-names = "qup-core", "qup-config";
1069 compatible = "qcom,geni-uart";
1071 clock-names = "se";
1073 pinctrl-names = "default";
1074 pinctrl-0 = <&qup_uart3_default>;
1076 power-domains = <&rpmhpd SC7180_CX>;
1077 operating-points-v2 = <&qup_opp_table>;
1080 interconnect-names = "qup-core", "qup-config";
1084 i2c4: i2c@890000 {
1085 compatible = "qcom,geni-i2c";
1087 clock-names = "se";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&qup_i2c4_default>;
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1097 interconnect-names = "qup-core", "qup-config",
1098 "qup-memory";
1099 power-domains = <&rpmhpd SC7180_CX>;
1100 required-opps = <&rpmhpd_opp_low_svs>;
1105 compatible = "qcom,geni-uart";
1107 clock-names = "se";
1109 pinctrl-names = "default";
1110 pinctrl-0 = <&qup_uart4_default>;
1112 power-domains = <&rpmhpd SC7180_CX>;
1113 operating-points-v2 = <&qup_opp_table>;
1116 interconnect-names = "qup-core", "qup-config";
1120 i2c5: i2c@894000 {
1121 compatible = "qcom,geni-i2c";
1123 clock-names = "se";
1125 pinctrl-names = "default";
1126 pinctrl-0 = <&qup_i2c5_default>;
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1133 interconnect-names = "qup-core", "qup-config",
1134 "qup-memory";
1135 power-domains = <&rpmhpd SC7180_CX>;
1136 required-opps = <&rpmhpd_opp_low_svs>;
1141 compatible = "qcom,geni-spi";
1143 clock-names = "se";
1145 pinctrl-names = "default";
1146 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1150 power-domains = <&rpmhpd SC7180_CX>;
1151 operating-points-v2 = <&qup_opp_table>;
1154 interconnect-names = "qup-core", "qup-config";
1159 compatible = "qcom,geni-uart";
1161 clock-names = "se";
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_uart5_default>;
1166 power-domains = <&rpmhpd SC7180_CX>;
1167 operating-points-v2 = <&qup_opp_table>;
1170 interconnect-names = "qup-core", "qup-config";
1176 compatible = "qcom,geni-se-qup";
1178 clock-names = "m-ahb", "s-ahb";
1181 #address-cells = <2>;
1182 #size-cells = <2>;
1187 i2c6: i2c@a80000 {
1188 compatible = "qcom,geni-i2c";
1190 clock-names = "se";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_i2c6_default>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1200 interconnect-names = "qup-core", "qup-config",
1201 "qup-memory";
1202 power-domains = <&rpmhpd SC7180_CX>;
1203 required-opps = <&rpmhpd_opp_low_svs>;
1208 compatible = "qcom,geni-spi";
1210 clock-names = "se";
1212 pinctrl-names = "default";
1213 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217 power-domains = <&rpmhpd SC7180_CX>;
1218 operating-points-v2 = <&qup_opp_table>;
1221 interconnect-names = "qup-core", "qup-config";
1226 compatible = "qcom,geni-uart";
1228 clock-names = "se";
1230 pinctrl-names = "default";
1231 pinctrl-0 = <&qup_uart6_default>;
1233 power-domains = <&rpmhpd SC7180_CX>;
1234 operating-points-v2 = <&qup_opp_table>;
1237 interconnect-names = "qup-core", "qup-config";
1241 i2c7: i2c@a84000 {
1242 compatible = "qcom,geni-i2c";
1244 clock-names = "se";
1246 pinctrl-names = "default";
1247 pinctrl-0 = <&qup_i2c7_default>;
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1254 interconnect-names = "qup-core", "qup-config",
1255 "qup-memory";
1256 power-domains = <&rpmhpd SC7180_CX>;
1257 required-opps = <&rpmhpd_opp_low_svs>;
1262 compatible = "qcom,geni-uart";
1264 clock-names = "se";
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&qup_uart7_default>;
1269 power-domains = <&rpmhpd SC7180_CX>;
1270 operating-points-v2 = <&qup_opp_table>;
1273 interconnect-names = "qup-core", "qup-config";
1277 i2c8: i2c@a88000 {
1278 compatible = "qcom,geni-i2c";
1280 clock-names = "se";
1282 pinctrl-names = "default";
1283 pinctrl-0 = <&qup_i2c8_default>;
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1290 interconnect-names = "qup-core", "qup-config",
1291 "qup-memory";
1292 power-domains = <&rpmhpd SC7180_CX>;
1293 required-opps = <&rpmhpd_opp_low_svs>;
1298 compatible = "qcom,geni-spi";
1300 clock-names = "se";
1302 pinctrl-names = "default";
1303 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1307 power-domains = <&rpmhpd SC7180_CX>;
1308 operating-points-v2 = <&qup_opp_table>;
1311 interconnect-names = "qup-core", "qup-config";
1316 compatible = "qcom,geni-debug-uart";
1318 clock-names = "se";
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&qup_uart8_default>;
1323 power-domains = <&rpmhpd SC7180_CX>;
1324 operating-points-v2 = <&qup_opp_table>;
1327 interconnect-names = "qup-core", "qup-config";
1331 i2c9: i2c@a8c000 {
1332 compatible = "qcom,geni-i2c";
1334 clock-names = "se";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_i2c9_default>;
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1344 interconnect-names = "qup-core", "qup-config",
1345 "qup-memory";
1346 power-domains = <&rpmhpd SC7180_CX>;
1347 required-opps = <&rpmhpd_opp_low_svs>;
1352 compatible = "qcom,geni-uart";
1354 clock-names = "se";
1356 pinctrl-names = "default";
1357 pinctrl-0 = <&qup_uart9_default>;
1359 power-domains = <&rpmhpd SC7180_CX>;
1360 operating-points-v2 = <&qup_opp_table>;
1363 interconnect-names = "qup-core", "qup-config";
1367 i2c10: i2c@a90000 {
1368 compatible = "qcom,geni-i2c";
1370 clock-names = "se";
1372 pinctrl-names = "default";
1373 pinctrl-0 = <&qup_i2c10_default>;
1375 #address-cells = <1>;
1376 #size-cells = <0>;
1380 interconnect-names = "qup-core", "qup-config",
1381 "qup-memory";
1382 power-domains = <&rpmhpd SC7180_CX>;
1383 required-opps = <&rpmhpd_opp_low_svs>;
1388 compatible = "qcom,geni-spi";
1390 clock-names = "se";
1392 pinctrl-names = "default";
1393 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1395 #address-cells = <1>;
1396 #size-cells = <0>;
1397 power-domains = <&rpmhpd SC7180_CX>;
1398 operating-points-v2 = <&qup_opp_table>;
1401 interconnect-names = "qup-core", "qup-config";
1406 compatible = "qcom,geni-uart";
1408 clock-names = "se";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_uart10_default>;
1413 power-domains = <&rpmhpd SC7180_CX>;
1414 operating-points-v2 = <&qup_opp_table>;
1417 interconnect-names = "qup-core", "qup-config";
1421 i2c11: i2c@a94000 {
1422 compatible = "qcom,geni-i2c";
1424 clock-names = "se";
1426 pinctrl-names = "default";
1427 pinctrl-0 = <&qup_i2c11_default>;
1429 #address-cells = <1>;
1430 #size-cells = <0>;
1434 interconnect-names = "qup-core", "qup-config",
1435 "qup-memory";
1436 power-domains = <&rpmhpd SC7180_CX>;
1437 required-opps = <&rpmhpd_opp_low_svs>;
1442 compatible = "qcom,geni-spi";
1444 clock-names = "se";
1446 pinctrl-names = "default";
1447 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451 power-domains = <&rpmhpd SC7180_CX>;
1452 operating-points-v2 = <&qup_opp_table>;
1455 interconnect-names = "qup-core", "qup-config";
1460 compatible = "qcom,geni-uart";
1462 clock-names = "se";
1464 pinctrl-names = "default";
1465 pinctrl-0 = <&qup_uart11_default>;
1467 power-domains = <&rpmhpd SC7180_CX>;
1468 operating-points-v2 = <&qup_opp_table>;
1471 interconnect-names = "qup-core", "qup-config";
1477 compatible = "qcom,sc7180-config-noc";
1479 #interconnect-cells = <2>;
1480 qcom,bcm-voters = <&apps_bcm_voter>;
1484 compatible = "qcom,sc7180-system-noc";
1486 #interconnect-cells = <2>;
1487 qcom,bcm-voters = <&apps_bcm_voter>;
1491 compatible = "qcom,sc7180-mc-virt";
1493 #interconnect-cells = <2>;
1494 qcom,bcm-voters = <&apps_bcm_voter>;
1498 compatible = "qcom,sc7180-qup-virt";
1500 #interconnect-cells = <2>;
1501 qcom,bcm-voters = <&apps_bcm_voter>;
1505 compatible = "qcom,sc7180-aggre1-noc";
1507 #interconnect-cells = <2>;
1508 qcom,bcm-voters = <&apps_bcm_voter>;
1512 compatible = "qcom,sc7180-aggre2-noc";
1514 #interconnect-cells = <2>;
1515 qcom,bcm-voters = <&apps_bcm_voter>;
1519 compatible = "qcom,sc7180-compute-noc";
1521 #interconnect-cells = <2>;
1522 qcom,bcm-voters = <&apps_bcm_voter>;
1526 compatible = "qcom,sc7180-mmss-noc";
1528 #interconnect-cells = <2>;
1529 qcom,bcm-voters = <&apps_bcm_voter>;
1533 compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
1534 "jedec,ufs-2.0";
1538 phy-names = "ufsphy";
1539 lanes-per-direction = <1>;
1540 #reset-cells = <1>;
1542 reset-names = "rst";
1544 power-domains = <&gcc UFS_PHY_GDSC>;
1548 clock-names = "core_clk",
1562 freq-table-hz = <50000000 200000000>,
1574 interconnect-names = "ufs-ddr", "cpu-ufs";
1582 compatible = "qcom,sc7180-qmp-ufs-phy";
1587 clock-names = "ref",
1590 power-domains = <&gcc UFS_PHY_GDSC>;
1592 reset-names = "ufsphy";
1593 #phy-cells = <0>;
1598 compatible = "qcom,sc7180-inline-crypto-engine",
1599 "qcom,inline-crypto-engine";
1605 compatible = "qcom,sc7180-ipa";
1612 reg-names = "ipa-reg",
1613 "ipa-shared",
1616 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 interrupt-names = "ipa",
1622 "ipa-clock-query",
1623 "ipa-setup-ready";
1626 clock-names = "core";
1631 interconnect-names = "memory",
1637 qcom,smem-states = <&ipa_smp2p_out 0>,
1639 qcom,smem-state-names = "ipa-clock-enabled-valid",
1640 "ipa-clock-enabled";
1646 compatible = "qcom,tcsr-mutex";
1648 #hwlock-cells = <1>;
1652 compatible = "qcom,sc7180-tcsr", "syscon";
1657 compatible = "qcom,sc7180-tcsr", "syscon";
1662 compatible = "qcom,sc7180-pinctrl";
1666 reg-names = "west", "north", "south";
1668 gpio-controller;
1669 #gpio-cells = <2>;
1670 interrupt-controller;
1671 #interrupt-cells = <2>;
1672 gpio-ranges = <&tlmm 0 0 120>;
1673 wakeup-parent = <&pdc>;
1675 dp_hot_plug_det: dp-hot-plug-det-state {
1680 qspi_clk: qspi-clk-state {
1685 qspi_cs0: qspi-cs0-state {
1690 qspi_cs1: qspi-cs1-state {
1695 qspi_data0: qspi-data0-state {
1700 qspi_data1: qspi-data1-state {
1705 qspi_data23: qspi-data23-state {
1710 qup_i2c0_default: qup-i2c0-default-state {
1715 qup_i2c1_default: qup-i2c1-default-state {
1720 qup_i2c2_default: qup-i2c2-default-state {
1725 qup_i2c3_default: qup-i2c3-default-state {
1730 qup_i2c4_default: qup-i2c4-default-state {
1735 qup_i2c5_default: qup-i2c5-default-state {
1740 qup_i2c6_default: qup-i2c6-default-state {
1745 qup_i2c7_default: qup-i2c7-default-state {
1750 qup_i2c8_default: qup-i2c8-default-state {
1755 qup_i2c9_default: qup-i2c9-default-state {
1760 qup_i2c10_default: qup-i2c10-default-state {
1765 qup_i2c11_default: qup-i2c11-default-state {
1770 qup_spi0_spi: qup-spi0-spi-state {
1775 qup_spi0_cs: qup-spi0-cs-state {
1780 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1785 qup_spi1_spi: qup-spi1-spi-state {
1790 qup_spi1_cs: qup-spi1-cs-state {
1795 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1800 qup_spi3_spi: qup-spi3-spi-state {
1805 qup_spi3_cs: qup-spi3-cs-state {
1810 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1815 qup_spi5_spi: qup-spi5-spi-state {
1820 qup_spi5_cs: qup-spi5-cs-state {
1825 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1830 qup_spi6_spi: qup-spi6-spi-state {
1835 qup_spi6_cs: qup-spi6-cs-state {
1840 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1845 qup_spi8_spi: qup-spi8-spi-state {
1850 qup_spi8_cs: qup-spi8-cs-state {
1855 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1860 qup_spi10_spi: qup-spi10-spi-state {
1865 qup_spi10_cs: qup-spi10-cs-state {
1870 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1875 qup_spi11_spi: qup-spi11-spi-state {
1880 qup_spi11_cs: qup-spi11-cs-state {
1885 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1890 qup_uart0_default: qup-uart0-default-state {
1891 qup_uart0_cts: cts-pins {
1896 qup_uart0_rts: rts-pins {
1901 qup_uart0_tx: tx-pins {
1906 qup_uart0_rx: rx-pins {
1912 qup_uart1_default: qup-uart1-default-state {
1913 qup_uart1_cts: cts-pins {
1918 qup_uart1_rts: rts-pins {
1923 qup_uart1_tx: tx-pins {
1928 qup_uart1_rx: rx-pins {
1934 qup_uart2_default: qup-uart2-default-state {
1935 qup_uart2_tx: tx-pins {
1940 qup_uart2_rx: rx-pins {
1946 qup_uart3_default: qup-uart3-default-state {
1947 qup_uart3_cts: cts-pins {
1952 qup_uart3_rts: rts-pins {
1957 qup_uart3_tx: tx-pins {
1962 qup_uart3_rx: rx-pins {
1968 qup_uart4_default: qup-uart4-default-state {
1969 qup_uart4_tx: tx-pins {
1974 qup_uart4_rx: rx-pins {
1980 qup_uart5_default: qup-uart5-default-state {
1981 qup_uart5_cts: cts-pins {
1986 qup_uart5_rts: rts-pins {
1991 qup_uart5_tx: tx-pins {
1996 qup_uart5_rx: rx-pins {
2002 qup_uart6_default: qup-uart6-default-state {
2003 qup_uart6_cts: cts-pins {
2008 qup_uart6_rts: rts-pins {
2013 qup_uart6_tx: tx-pins {
2018 qup_uart6_rx: rx-pins {
2024 qup_uart7_default: qup-uart7-default-state {
2025 qup_uart7_tx: tx-pins {
2030 qup_uart7_rx: rx-pins {
2036 qup_uart8_default: qup-uart8-default-state {
2037 qup_uart8_tx: tx-pins {
2042 qup_uart8_rx: rx-pins {
2048 qup_uart9_default: qup-uart9-default-state {
2049 qup_uart9_tx: tx-pins {
2054 qup_uart9_rx: rx-pins {
2060 qup_uart10_default: qup-uart10-default-state {
2061 qup_uart10_cts: cts-pins {
2066 qup_uart10_rts: rts-pins {
2071 qup_uart10_tx: tx-pins {
2076 qup_uart10_rx: rx-pins {
2082 qup_uart11_default: qup-uart11-default-state {
2083 qup_uart11_cts: cts-pins {
2088 qup_uart11_rts: rts-pins {
2093 qup_uart11_tx: tx-pins {
2098 qup_uart11_rx: rx-pins {
2104 sec_mi2s_active: sec-mi2s-active-state {
2109 pri_mi2s_active: pri-mi2s-active-state {
2114 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2119 ter_mi2s_active: ter-mi2s-active-state {
2126 compatible = "qcom,sc7180-mpss-pas";
2129 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2135 interrupt-names = "wdog", "fatal", "ready", "handover",
2136 "stop-ack", "shutdown-ack";
2139 clock-names = "xo";
2141 power-domains = <&rpmhpd SC7180_CX>,
2144 power-domain-names = "cx", "mx", "mss";
2146 memory-region = <&mpss_mem>;
2150 qcom,smem-states = <&modem_smp2p_out 0>;
2151 qcom,smem-state-names = "stop";
2155 glink-edge {
2158 qcom,remote-pid = <1>;
2164 compatible = "qcom,adreno-618.0", "qcom,adreno";
2167 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2170 operating-points-v2 = <&gpu_opp_table>;
2173 #cooling-cells = <2>;
2175 nvmem-cells = <&gpu_speed_bin>;
2176 nvmem-cell-names = "speed_bin";
2179 interconnect-names = "gfx-mem";
2181 gpu_opp_table: opp-table {
2182 compatible = "operating-points-v2";
2184 opp-825000000 {
2185 opp-hz = /bits/ 64 <825000000>;
2186 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2187 opp-peak-kBps = <8532000>;
2188 opp-supported-hw = <0x04>;
2191 opp-800000000 {
2192 opp-hz = /bits/ 64 <800000000>;
2193 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2194 opp-peak-kBps = <8532000>;
2195 opp-supported-hw = <0x07>;
2198 opp-650000000 {
2199 opp-hz = /bits/ 64 <650000000>;
2200 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2201 opp-peak-kBps = <7216000>;
2202 opp-supported-hw = <0x07>;
2205 opp-565000000 {
2206 opp-hz = /bits/ 64 <565000000>;
2207 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2208 opp-peak-kBps = <5412000>;
2209 opp-supported-hw = <0x07>;
2212 opp-430000000 {
2213 opp-hz = /bits/ 64 <430000000>;
2214 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2215 opp-peak-kBps = <5412000>;
2216 opp-supported-hw = <0x07>;
2219 opp-355000000 {
2220 opp-hz = /bits/ 64 <355000000>;
2221 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2222 opp-peak-kBps = <3072000>;
2223 opp-supported-hw = <0x07>;
2226 opp-267000000 {
2227 opp-hz = /bits/ 64 <267000000>;
2228 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2229 opp-peak-kBps = <3072000>;
2230 opp-supported-hw = <0x07>;
2233 opp-180000000 {
2234 opp-hz = /bits/ 64 <180000000>;
2235 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2236 opp-peak-kBps = <1804000>;
2237 opp-supported-hw = <0x07>;
2243 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2245 #iommu-cells = <1>;
2246 #global-interrupts = <2>;
2260 clock-names = "bus", "iface";
2262 power-domains = <&gpucc CX_GDSC>;
2266 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2269 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2272 interrupt-names = "hfi", "gmu";
2277 clock-names = "gmu", "cxo", "axi", "memnoc";
2278 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2279 power-domain-names = "cx", "gx";
2281 operating-points-v2 = <&gmu_opp_table>;
2283 gmu_opp_table: opp-table {
2284 compatible = "operating-points-v2";
2286 opp-200000000 {
2287 opp-hz = /bits/ 64 <200000000>;
2288 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2293 gpucc: clock-controller@5090000 {
2294 compatible = "qcom,sc7180-gpucc";
2299 clock-names = "bi_tcxo",
2302 #clock-cells = <1>;
2303 #reset-cells = <1>;
2304 #power-domain-cells = <1>;
2308 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2315 compatible = "arm,coresight-stm", "arm,primecell";
2318 reg-names = "stm-base", "stm-stimulus-base";
2321 clock-names = "apb_pclk";
2323 out-ports {
2326 remote-endpoint = <&funnel0_in7>;
2333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 clock-names = "apb_pclk";
2339 out-ports {
2342 remote-endpoint = <&merge_funnel_in0>;
2347 in-ports {
2348 #address-cells = <1>;
2349 #size-cells = <0>;
2354 remote-endpoint = <&stm_out>;
2361 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 clock-names = "apb_pclk";
2367 out-ports {
2370 remote-endpoint = <&merge_funnel_in1>;
2375 in-ports {
2376 #address-cells = <1>;
2377 #size-cells = <0>;
2382 remote-endpoint = <&apss_merge_funnel_out>;
2389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 clock-names = "apb_pclk";
2395 out-ports {
2398 remote-endpoint = <&swao_funnel_in>;
2403 in-ports {
2404 #address-cells = <1>;
2405 #size-cells = <0>;
2410 remote-endpoint = <&funnel0_out>;
2417 remote-endpoint = <&funnel1_out>;
2424 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 clock-names = "apb_pclk";
2430 out-ports {
2433 remote-endpoint = <&etr_in>;
2438 in-ports {
2441 remote-endpoint = <&swao_replicator_out>;
2448 compatible = "arm,coresight-tmc", "arm,primecell";
2453 clock-names = "apb_pclk";
2454 arm,scatter-gather;
2456 in-ports {
2459 remote-endpoint = <&replicator_out>;
2466 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 clock-names = "apb_pclk";
2472 out-ports {
2475 remote-endpoint = <&etf_in>;
2480 in-ports {
2481 #address-cells = <1>;
2482 #size-cells = <0>;
2487 remote-endpoint = <&merge_funnel_out>;
2494 compatible = "arm,coresight-tmc", "arm,primecell";
2498 clock-names = "apb_pclk";
2500 out-ports {
2503 remote-endpoint = <&swao_replicator_in>;
2508 in-ports {
2511 remote-endpoint = <&swao_funnel_out>;
2518 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 clock-names = "apb_pclk";
2523 qcom,replicator-loses-context;
2525 out-ports {
2528 remote-endpoint = <&replicator_in>;
2533 in-ports {
2536 remote-endpoint = <&etf_out>;
2543 compatible = "arm,coresight-etm4x", "arm,primecell";
2549 clock-names = "apb_pclk";
2550 arm,coresight-loses-context-with-cpu;
2551 qcom,skip-power-up;
2553 out-ports {
2556 remote-endpoint = <&apss_funnel_in0>;
2563 compatible = "arm,coresight-etm4x", "arm,primecell";
2569 clock-names = "apb_pclk";
2570 arm,coresight-loses-context-with-cpu;
2571 qcom,skip-power-up;
2573 out-ports {
2576 remote-endpoint = <&apss_funnel_in1>;
2583 compatible = "arm,coresight-etm4x", "arm,primecell";
2589 clock-names = "apb_pclk";
2590 arm,coresight-loses-context-with-cpu;
2591 qcom,skip-power-up;
2593 out-ports {
2596 remote-endpoint = <&apss_funnel_in2>;
2603 compatible = "arm,coresight-etm4x", "arm,primecell";
2609 clock-names = "apb_pclk";
2610 arm,coresight-loses-context-with-cpu;
2611 qcom,skip-power-up;
2613 out-ports {
2616 remote-endpoint = <&apss_funnel_in3>;
2623 compatible = "arm,coresight-etm4x", "arm,primecell";
2629 clock-names = "apb_pclk";
2630 arm,coresight-loses-context-with-cpu;
2631 qcom,skip-power-up;
2633 out-ports {
2636 remote-endpoint = <&apss_funnel_in4>;
2643 compatible = "arm,coresight-etm4x", "arm,primecell";
2649 clock-names = "apb_pclk";
2650 arm,coresight-loses-context-with-cpu;
2651 qcom,skip-power-up;
2653 out-ports {
2656 remote-endpoint = <&apss_funnel_in5>;
2663 compatible = "arm,coresight-etm4x", "arm,primecell";
2669 clock-names = "apb_pclk";
2670 arm,coresight-loses-context-with-cpu;
2671 qcom,skip-power-up;
2673 out-ports {
2676 remote-endpoint = <&apss_funnel_in6>;
2683 compatible = "arm,coresight-etm4x", "arm,primecell";
2689 clock-names = "apb_pclk";
2690 arm,coresight-loses-context-with-cpu;
2691 qcom,skip-power-up;
2693 out-ports {
2696 remote-endpoint = <&apss_funnel_in7>;
2703 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 clock-names = "apb_pclk";
2709 out-ports {
2712 remote-endpoint = <&apss_merge_funnel_in>;
2717 in-ports {
2718 #address-cells = <1>;
2719 #size-cells = <0>;
2724 remote-endpoint = <&etm0_out>;
2731 remote-endpoint = <&etm1_out>;
2738 remote-endpoint = <&etm2_out>;
2745 remote-endpoint = <&etm3_out>;
2752 remote-endpoint = <&etm4_out>;
2759 remote-endpoint = <&etm5_out>;
2766 remote-endpoint = <&etm6_out>;
2773 remote-endpoint = <&etm7_out>;
2780 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 clock-names = "apb_pclk";
2786 out-ports {
2789 remote-endpoint = <&funnel1_in4>;
2794 in-ports {
2797 remote-endpoint = <&apss_funnel_out>;
2804 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2810 interrupt-names = "hc_irq", "pwr_irq";
2815 clock-names = "iface", "core", "xo";
2819 interconnect-names = "sdhc-ddr","cpu-sdhc";
2820 power-domains = <&rpmhpd SC7180_CX>;
2821 operating-points-v2 = <&sdhc2_opp_table>;
2823 bus-width = <4>;
2827 sdhc2_opp_table: opp-table {
2828 compatible = "operating-points-v2";
2830 opp-100000000 {
2831 opp-hz = /bits/ 64 <100000000>;
2832 required-opps = <&rpmhpd_opp_low_svs>;
2833 opp-peak-kBps = <1800000 600000>;
2834 opp-avg-kBps = <100000 0>;
2837 opp-202000000 {
2838 opp-hz = /bits/ 64 <202000000>;
2839 required-opps = <&rpmhpd_opp_nom>;
2840 opp-peak-kBps = <5400000 1600000>;
2841 opp-avg-kBps = <200000 0>;
2847 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2850 #address-cells = <1>;
2851 #size-cells = <0>;
2855 clock-names = "iface", "core";
2858 interconnect-names = "qspi-config";
2859 power-domains = <&rpmhpd SC7180_CX>;
2860 operating-points-v2 = <&qspi_opp_table>;
2865 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2868 #phy-cells = <0>;
2871 clock-names = "cfg_ahb", "ref";
2874 nvmem-cells = <&qusb2p_hstx_trim>;
2878 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2887 clock-names = "aux",
2895 reset-names = "phy", "common";
2897 #clock-cells = <1>;
2898 #phy-cells = <1>;
2902 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2908 operating-points-v2 = <&cpu_bwmon_opp_table>;
2910 cpu_bwmon_opp_table: opp-table {
2911 compatible = "operating-points-v2";
2913 opp-0 {
2914 opp-peak-kBps = <2288000>;
2917 opp-1 {
2918 opp-peak-kBps = <4577000>;
2921 opp-2 {
2922 opp-peak-kBps = <7110000>;
2925 opp-3 {
2926 opp-peak-kBps = <9155000>;
2929 opp-4 {
2930 opp-peak-kBps = <12298000>;
2933 opp-5 {
2934 opp-peak-kBps = <14236000>;
2940 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2946 operating-points-v2 = <&llcc_bwmon_opp_table>;
2948 llcc_bwmon_opp_table: opp-table {
2949 compatible = "operating-points-v2";
2951 opp-0 {
2952 opp-peak-kBps = <1144000>;
2955 opp-1 {
2956 opp-peak-kBps = <1720000>;
2959 opp-2 {
2960 opp-peak-kBps = <2086000>;
2963 opp-3 {
2964 opp-peak-kBps = <2929000>;
2967 opp-4 {
2968 opp-peak-kBps = <3879000>;
2971 opp-5 {
2972 opp-peak-kBps = <5931000>;
2975 opp-6 {
2976 opp-peak-kBps = <6881000>;
2979 opp-7 {
2980 opp-peak-kBps = <8137000>;
2986 compatible = "qcom,sc7180-dc-noc";
2988 #interconnect-cells = <2>;
2989 qcom,bcm-voters = <&apps_bcm_voter>;
2992 system-cache-controller@9200000 {
2993 compatible = "qcom,sc7180-llcc";
2995 reg-names = "llcc0_base", "llcc_broadcast_base";
3000 compatible = "qcom,sc7180-gem-noc";
3002 #interconnect-cells = <2>;
3003 qcom,bcm-voters = <&apps_bcm_voter>;
3007 compatible = "qcom,sc7180-npu-noc";
3009 #interconnect-cells = <2>;
3010 qcom,bcm-voters = <&apps_bcm_voter>;
3014 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3017 #address-cells = <2>;
3018 #size-cells = <2>;
3020 dma-ranges;
3027 clock-names = "cfg_noc",
3033 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3035 assigned-clock-rates = <19200000>, <150000000>;
3037 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3042 interrupt-names = "pwr_event",
3048 power-domains = <&gcc USB30_PRIM_GDSC>;
3049 required-opps = <&rpmhpd_opp_nom>;
3055 interconnect-names = "usb-ddr", "apps-usb";
3057 wakeup-source;
3066 snps,parkmode-disable-ss-quirk;
3067 snps,dis-u1-entry-quirk;
3068 snps,dis-u2-entry-quirk;
3070 phy-names = "usb2-phy", "usb3-phy";
3071 maximum-speed = "super-speed";
3075 venus: video-codec@aa00000 {
3076 compatible = "qcom,sc7180-venus";
3079 power-domains = <&videocc VENUS_GDSC>,
3082 power-domain-names = "venus", "vcodec0", "cx";
3083 operating-points-v2 = <&venus_opp_table>;
3089 clock-names = "core", "iface", "bus",
3092 memory-region = <&venus_mem>;
3095 interconnect-names = "video-mem", "cpu-cfg";
3097 video-decoder {
3098 compatible = "venus-decoder";
3101 video-encoder {
3102 compatible = "venus-encoder";
3105 venus_opp_table: opp-table {
3106 compatible = "operating-points-v2";
3108 opp-150000000 {
3109 opp-hz = /bits/ 64 <150000000>;
3110 required-opps = <&rpmhpd_opp_low_svs>;
3113 opp-270000000 {
3114 opp-hz = /bits/ 64 <270000000>;
3115 required-opps = <&rpmhpd_opp_svs>;
3118 opp-340000000 {
3119 opp-hz = /bits/ 64 <340000000>;
3120 required-opps = <&rpmhpd_opp_svs_l1>;
3123 opp-434000000 {
3124 opp-hz = /bits/ 64 <434000000>;
3125 required-opps = <&rpmhpd_opp_nom>;
3128 opp-500000097 {
3129 opp-hz = /bits/ 64 <500000097>;
3130 required-opps = <&rpmhpd_opp_turbo>;
3135 videocc: clock-controller@ab00000 {
3136 compatible = "qcom,sc7180-videocc";
3139 clock-names = "bi_tcxo";
3140 #clock-cells = <1>;
3141 #reset-cells = <1>;
3142 #power-domain-cells = <1>;
3146 compatible = "qcom,sc7180-camnoc-virt";
3148 #interconnect-cells = <2>;
3149 qcom,bcm-voters = <&apps_bcm_voter>;
3152 camcc: clock-controller@ad00000 {
3153 compatible = "qcom,sc7180-camcc";
3158 clock-names = "bi_tcxo", "iface", "xo";
3159 #clock-cells = <1>;
3160 #reset-cells = <1>;
3161 #power-domain-cells = <1>;
3164 mdss: display-subsystem@ae00000 {
3165 compatible = "qcom,sc7180-mdss";
3167 reg-names = "mdss";
3169 power-domains = <&dispcc MDSS_GDSC>;
3174 clock-names = "iface", "ahb", "core";
3177 interrupt-controller;
3178 #interrupt-cells = <1>;
3184 interconnect-names = "mdp0-mem",
3185 "cpu-cfg";
3189 #address-cells = <2>;
3190 #size-cells = <2>;
3195 mdp: display-controller@ae01000 {
3196 compatible = "qcom,sc7180-dpu";
3199 reg-names = "mdp", "vbif";
3207 clock-names = "bus", "iface", "rot", "lut", "core",
3209 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3212 assigned-clock-rates = <19200000>,
3215 operating-points-v2 = <&mdp_opp_table>;
3216 power-domains = <&rpmhpd SC7180_CX>;
3218 interrupt-parent = <&mdss>;
3222 #address-cells = <1>;
3223 #size-cells = <0>;
3228 remote-endpoint = <&mdss_dsi0_in>;
3235 remote-endpoint = <&dp_in>;
3240 mdp_opp_table: opp-table {
3241 compatible = "operating-points-v2";
3243 opp-200000000 {
3244 opp-hz = /bits/ 64 <200000000>;
3245 required-opps = <&rpmhpd_opp_low_svs>;
3248 opp-300000000 {
3249 opp-hz = /bits/ 64 <300000000>;
3250 required-opps = <&rpmhpd_opp_svs>;
3253 opp-345000000 {
3254 opp-hz = /bits/ 64 <345000000>;
3255 required-opps = <&rpmhpd_opp_svs_l1>;
3258 opp-460000000 {
3259 opp-hz = /bits/ 64 <460000000>;
3260 required-opps = <&rpmhpd_opp_nom>;
3266 compatible = "qcom,sc7180-dsi-ctrl",
3267 "qcom,mdss-dsi-ctrl";
3269 reg-names = "dsi_ctrl";
3271 interrupt-parent = <&mdss>;
3280 clock-names = "byte",
3287 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3288 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3290 operating-points-v2 = <&dsi_opp_table>;
3291 power-domains = <&rpmhpd SC7180_CX>;
3295 #address-cells = <1>;
3296 #size-cells = <0>;
3301 #address-cells = <1>;
3302 #size-cells = <0>;
3307 remote-endpoint = <&dpu_intf1_out>;
3318 dsi_opp_table: opp-table {
3319 compatible = "operating-points-v2";
3321 opp-187500000 {
3322 opp-hz = /bits/ 64 <187500000>;
3323 required-opps = <&rpmhpd_opp_low_svs>;
3326 opp-300000000 {
3327 opp-hz = /bits/ 64 <300000000>;
3328 required-opps = <&rpmhpd_opp_svs>;
3331 opp-358000000 {
3332 opp-hz = /bits/ 64 <358000000>;
3333 required-opps = <&rpmhpd_opp_svs_l1>;
3339 compatible = "qcom,dsi-phy-10nm";
3343 reg-names = "dsi_phy",
3347 #clock-cells = <1>;
3348 #phy-cells = <0>;
3352 clock-names = "iface", "ref";
3357 mdss_dp: displayport-controller@ae90000 {
3358 compatible = "qcom,sc7180-dp";
3367 interrupt-parent = <&mdss>;
3375 clock-names = "core_iface", "core_aux", "ctrl_link",
3377 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3379 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3382 phy-names = "dp";
3384 operating-points-v2 = <&dp_opp_table>;
3385 power-domains = <&rpmhpd SC7180_CX>;
3387 #sound-dai-cells = <0>;
3390 #address-cells = <1>;
3391 #size-cells = <0>;
3395 remote-endpoint = <&dpu_intf0_out>;
3405 dp_opp_table: opp-table {
3406 compatible = "operating-points-v2";
3408 opp-160000000 {
3409 opp-hz = /bits/ 64 <160000000>;
3410 required-opps = <&rpmhpd_opp_low_svs>;
3413 opp-270000000 {
3414 opp-hz = /bits/ 64 <270000000>;
3415 required-opps = <&rpmhpd_opp_svs>;
3418 opp-540000000 {
3419 opp-hz = /bits/ 64 <540000000>;
3420 required-opps = <&rpmhpd_opp_svs_l1>;
3423 opp-810000000 {
3424 opp-hz = /bits/ 64 <810000000>;
3425 required-opps = <&rpmhpd_opp_nom>;
3431 dispcc: clock-controller@af00000 {
3432 compatible = "qcom,sc7180-dispcc";
3440 clock-names = "bi_tcxo",
3446 #clock-cells = <1>;
3447 #reset-cells = <1>;
3448 #power-domain-cells = <1>;
3451 pdc: interrupt-controller@b220000 {
3452 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3455 #interrupt-cells = <2>;
3456 interrupt-parent = <&intc>;
3457 interrupt-controller;
3460 pdc_reset: reset-controller@b2e0000 {
3461 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 #reset-cells = <1>;
3466 tsens0: thermal-sensor@c263000 {
3467 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3473 interrupt-names = "uplow","critical";
3474 #thermal-sensor-cells = <1>;
3477 tsens1: thermal-sensor@c265000 {
3478 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3484 interrupt-names = "uplow","critical";
3485 #thermal-sensor-cells = <1>;
3488 aoss_reset: reset-controller@c2a0000 {
3489 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 #reset-cells = <1>;
3494 aoss_qmp: power-management@c300000 {
3495 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3500 #clock-cells = <0>;
3504 compatible = "qcom,rpmh-stats";
3509 compatible = "qcom,spmi-pmic-arb";
3515 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3516 interrupt-names = "periph_irq";
3517 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3520 #address-cells = <2>;
3521 #size-cells = <0>;
3522 interrupt-controller;
3523 #interrupt-cells = <4>;
3527 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3530 #address-cells = <1>;
3531 #size-cells = <1>;
3535 pil-reloc@94c {
3536 compatible = "qcom,pil-reloc-info";
3542 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 #iommu-cells = <2>;
3545 #global-interrupts = <1>;
3627 dma-coherent;
3630 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic-v3";
3632 #address-cells = <2>;
3633 #size-cells = <2>;
3635 #interrupt-cells = <3>;
3636 interrupt-controller;
3641 msi-controller@17a40000 {
3642 compatible = "arm,gic-v3-its";
3643 msi-controller;
3644 #msi-cells = <1>;
3651 compatible = "qcom,sc7180-apss-shared",
3652 "qcom,sdm845-apss-shared";
3654 #mbox-cells = <1>;
3658 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3665 #address-cells = <1>;
3666 #size-cells = <1>;
3668 compatible = "arm,armv7-timer-mem";
3672 frame-number = <0>;
3680 frame-number = <1>;
3687 frame-number = <2>;
3694 frame-number = <3>;
3701 frame-number = <4>;
3708 frame-number = <5>;
3715 frame-number = <6>;
3723 compatible = "qcom,rpmh-rsc";
3727 reg-names = "drv-0", "drv-1", "drv-2";
3731 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>;
3733 qcom,tcs-config = <ACTIVE_TCS 2>,
3737 power-domains = <&cluster_pd>;
3739 rpmhcc: clock-controller {
3740 compatible = "qcom,sc7180-rpmh-clk";
3742 clock-names = "xo";
3743 #clock-cells = <1>;
3746 rpmhpd: power-controller {
3747 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain-cells = <1>;
3749 operating-points-v2 = <&rpmhpd_opp_table>;
3751 rpmhpd_opp_table: opp-table {
3752 compatible = "operating-points-v2";
3755 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3759 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3763 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3767 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3771 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3775 opp-level = <224>;
3779 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3783 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3787 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3795 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3800 apps_bcm_voter: bcm-voter {
3801 compatible = "qcom,bcm-voter";
3806 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3810 clock-names = "xo", "alternate";
3812 #interconnect-cells = <1>;
3816 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3818 reg-names = "freq-domain0", "freq-domain1";
3821 clock-names = "xo", "alternate";
3823 #freq-domain-cells = <1>;
3824 #clock-cells = <1>;
3828 compatible = "qcom,wcn3990-wifi";
3830 reg-names = "membase";
3845 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm;
3851 compatible = "qcom,sc7180-adsp-pas";
3854 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3859 interrupt-names = "wdog",
3863 "stop-ack";
3866 clock-names = "xo";
3868 power-domains = <&rpmhpd SC7180_LCX>,
3870 power-domain-names = "lcx", "lmx";
3873 qcom,smem-states = <&adsp_smp2p_out 0>;
3874 qcom,smem-state-names = "stop";
3878 glink-edge {
3881 qcom,remote-pid = <2>;
3885 compatible = "qcom,apr-v2";
3886 qcom,glink-channels = "apr_audio_svc";
3888 #address-cells = <1>;
3889 #size-cells = <0>;
3894 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3900 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3903 compatible = "qcom,q6afe-dais";
3904 #address-cells = <1>;
3905 #size-cells = <0>;
3906 #sound-dai-cells = <1>;
3909 q6afecc: clock-controller {
3910 compatible = "qcom,q6afe-clocks";
3911 #clock-cells = <2>;
3918 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3921 compatible = "qcom,q6asm-dais";
3922 #address-cells = <1>;
3923 #size-cells = <0>;
3924 #sound-dai-cells = <1>;
3932 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3935 compatible = "qcom,q6adm-routing";
3936 #sound-dai-cells = <0>;
3943 qcom,glink-channels = "fastrpcglink-apps-dsp";
3945 #address-cells = <1>;
3946 #size-cells = <0>;
3948 compute-cb@3 {
3949 compatible = "qcom,fastrpc-compute-cb";
3954 compute-cb@4 {
3955 compatible = "qcom,fastrpc-compute-cb";
3960 compute-cb@5 {
3961 compatible = "qcom,fastrpc-compute-cb";
3970 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc7180-lpasscorecc";
3974 reg-names = "lpass_core_cc", "lpass_audio_cc";
3977 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>;
3980 #power-domain-cells = <1>;
3986 compatible = "qcom,sc7180-lpass-cpu";
3989 reg-names = "lpass-hdmiif", "lpass-lpaif";
3995 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpmhpd_opp_nom>;
4007 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk0", "pcnoc-mport-clk",
4009 "mi2s-bit-clk0", "mi2s-bit-clk1";
4012 #sound-dai-cells = <1>;
4013 #address-cells = <1>;
4014 #size-cells = <0>;
4018 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4021 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc7180-lpasshm";
4026 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpmhpd SC7180_CX>;
4029 #clock-cells = <1>;
4030 #power-domain-cells = <1>;
4036 thermal-zones {
4037 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive = <250>;
4040 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = <1052>;
4044 cpu0_alert0: trip-point0 {
4050 cpu0_alert1: trip-point1 {
4056 cpu0_crit: cpu-crit {
4063 cooling-maps {
4066 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4075 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4085 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive = <250>;
4088 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = <1052>;
4092 cpu1_alert0: trip-point0 {
4098 cpu1_alert1: trip-point1 {
4104 cpu1_crit: cpu-crit {
4111 cooling-maps {
4114 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4123 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4133 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive = <250>;
4136 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = <1052>;
4140 cpu2_alert0: trip-point0 {
4146 cpu2_alert1: trip-point1 {
4152 cpu2_crit: cpu-crit {
4159 cooling-maps {
4162 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4171 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4181 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive = <250>;
4184 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = <1052>;
4188 cpu3_alert0: trip-point0 {
4194 cpu3_alert1: trip-point1 {
4200 cpu3_crit: cpu-crit {
4207 cooling-maps {
4210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4219 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4229 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive = <250>;
4232 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = <1052>;
4236 cpu4_alert0: trip-point0 {
4242 cpu4_alert1: trip-point1 {
4248 cpu4_crit: cpu-crit {
4255 cooling-maps {
4258 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4267 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4277 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive = <250>;
4280 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = <1052>;
4284 cpu5_alert0: trip-point0 {
4290 cpu5_alert1: trip-point1 {
4296 cpu5_crit: cpu-crit {
4303 cooling-maps {
4306 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4315 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4325 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive = <250>;
4328 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = <1425>;
4332 cpu6_alert0: trip-point0 {
4338 cpu6_alert1: trip-point1 {
4344 cpu6_crit: cpu-crit {
4351 cooling-maps {
4354 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4359 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4365 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive = <250>;
4368 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = <1425>;
4372 cpu7_alert0: trip-point0 {
4378 cpu7_alert1: trip-point1 {
4384 cpu7_crit: cpu-crit {
4391 cooling-maps {
4394 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4399 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4405 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive = <250>;
4408 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = <1425>;
4412 cpu8_alert0: trip-point0 {
4418 cpu8_alert1: trip-point1 {
4424 cpu8_crit: cpu-crit {
4431 cooling-maps {
4434 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4439 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4445 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive = <250>;
4448 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = <1425>;
4452 cpu9_alert0: trip-point0 {
4458 cpu9_alert1: trip-point1 {
4464 cpu9_crit: cpu-crit {
4471 cooling-maps {
4474 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4479 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4485 aoss0-thermal {
4486 polling-delay-passive = <250>;
4488 thermal-sensors = <&tsens0 0>;
4491 aoss0_alert0: trip-point0 {
4497 aoss0_crit: aoss0-crit {
4505 cpuss0-thermal {
4506 polling-delay-passive = <250>;
4508 thermal-sensors = <&tsens0 7>;
4511 cpuss0_alert0: trip-point0 {
4516 cpuss0_crit: cluster0-crit {
4524 cpuss1-thermal {
4525 polling-delay-passive = <250>;
4527 thermal-sensors = <&tsens0 8>;
4530 cpuss1_alert0: trip-point0 {
4535 cpuss1_crit: cluster0-crit {
4543 gpuss0-thermal {
4544 polling-delay-passive = <250>;
4546 thermal-sensors = <&tsens0 13>;
4549 gpuss0_alert0: trip-point0 {
4555 gpuss0_crit: gpuss0-crit {
4562 cooling-maps {
4565 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4570 gpuss1-thermal {
4571 polling-delay-passive = <250>;
4573 thermal-sensors = <&tsens0 14>;
4576 gpuss1_alert0: trip-point0 {
4582 gpuss1_crit: gpuss1-crit {
4589 cooling-maps {
4592 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4597 aoss1-thermal {
4598 polling-delay-passive = <250>;
4600 thermal-sensors = <&tsens1 0>;
4603 aoss1_alert0: trip-point0 {
4609 aoss1_crit: aoss1-crit {
4617 cwlan-thermal {
4618 polling-delay-passive = <250>;
4620 thermal-sensors = <&tsens1 1>;
4623 cwlan_alert0: trip-point0 {
4629 cwlan_crit: cwlan-crit {
4637 audio-thermal {
4638 polling-delay-passive = <250>;
4640 thermal-sensors = <&tsens1 2>;
4643 audio_alert0: trip-point0 {
4649 audio_crit: audio-crit {
4657 ddr-thermal {
4658 polling-delay-passive = <250>;
4660 thermal-sensors = <&tsens1 3>;
4663 ddr_alert0: trip-point0 {
4669 ddr_crit: ddr-crit {
4677 q6-hvx-thermal {
4678 polling-delay-passive = <250>;
4680 thermal-sensors = <&tsens1 4>;
4683 q6_hvx_alert0: trip-point0 {
4689 q6_hvx_crit: q6-hvx-crit {
4697 camera-thermal {
4698 polling-delay-passive = <250>;
4700 thermal-sensors = <&tsens1 5>;
4703 camera_alert0: trip-point0 {
4709 camera_crit: camera-crit {
4717 mdm-core-thermal {
4718 polling-delay-passive = <250>;
4720 thermal-sensors = <&tsens1 6>;
4723 mdm_alert0: trip-point0 {
4729 mdm_crit: mdm-crit {
4737 mdm-dsp-thermal {
4738 polling-delay-passive = <250>;
4740 thermal-sensors = <&tsens1 7>;
4743 mdm_dsp_alert0: trip-point0 {
4749 mdm_dsp_crit: mdm-dsp-crit {
4757 npu-thermal {
4758 polling-delay-passive = <250>;
4760 thermal-sensors = <&tsens1 8>;
4763 npu_alert0: trip-point0 {
4769 npu_crit: npu-crit {
4777 video-thermal {
4778 polling-delay-passive = <250>;
4780 thermal-sensors = <&tsens1 9>;
4783 video_alert0: trip-point0 {
4789 video_crit: video-crit {
4799 compatible = "arm,armv8-timer";