Lines Matching +full:0 +full:x0c40a000
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #size-cells = <0>;
80 cpu0: cpu@0 {
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 0>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
136 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw 0>;
148 qcom,freq-domain = <&cpufreq_hw 0>;
160 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw 0>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
184 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw 0>;
196 qcom,freq-domain = <&cpufreq_hw 0>;
208 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw 0>;
220 qcom,freq-domain = <&cpufreq_hw 0>;
232 reg = <0x0 0x600>;
256 reg = <0x0 0x700>;
316 little_cpu_sleep_0: cpu-sleep-0-0 {
319 arm,psci-suspend-param = <0x40000003>;
326 little_cpu_sleep_1: cpu-sleep-0-1 {
329 arm,psci-suspend-param = <0x40000004>;
336 big_cpu_sleep_0: cpu-sleep-1-0 {
339 arm,psci-suspend-param = <0x40000003>;
349 arm,psci-suspend-param = <0x40000004>;
358 cluster_sleep_pc: cluster-sleep-0 {
360 arm,psci-suspend-param = <0x41000044>;
368 arm,psci-suspend-param = <0x41001244>;
376 arm,psci-suspend-param = <0x4100b244>;
393 reg = <0 0x80000000 0 0>;
584 #power-domain-cells = <0>;
590 #power-domain-cells = <0>;
596 #power-domain-cells = <0>;
602 #power-domain-cells = <0>;
608 #power-domain-cells = <0>;
614 #power-domain-cells = <0>;
620 #power-domain-cells = <0>;
626 #power-domain-cells = <0>;
632 #power-domain-cells = <0>;
645 reg = <0x0 0x80000000 0x0 0x600000>;
650 reg = <0x0 0x80600000 0x0 0x200000>;
655 reg = <0x0 0x80800000 0x0 0x20000>;
660 reg = <0x0 0x80820000 0x0 0x20000>;
666 reg = <0x0 0x808ff000 0x0 0x1000>;
671 reg = <0x0 0x80900000 0x0 0x200000>;
676 reg = <0x0 0x80b00000 0x0 0x3900000>;
681 reg = <0 0x8b700000 0 0x10000>;
687 reg = <0x0 0x94600000 0x0 0x200000>;
709 qcom,local-pid = <0>;
733 qcom,local-pid = <0>;
754 qcom,local-pid = <0>;
780 soc: soc@0 {
783 ranges = <0 0 0 0 0x10 0>;
784 dma-ranges = <0 0 0 0 0x10 0>;
789 reg = <0 0x00100000 0 0x1f0000>;
802 reg = <0 0x00784000 0 0x7a0>,
803 <0 0x00780000 0 0x7a0>,
804 <0 0x00782000 0 0x100>,
805 <0 0x00786000 0 0x1fff>;
813 reg = <0x25b 0x1>;
818 reg = <0x1d2 0x2>;
825 reg = <0 0x007c4000 0 0x1000>,
826 <0 0x007c5000 0 0x1000>;
829 iommus = <&apps_smmu 0x60 0x0>;
838 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
839 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
862 opp-avg-kBps = <100000 0>;
869 opp-avg-kBps = <390000 0>;
876 reg = <0 0x008c0000 0 0x6000>;
883 iommus = <&apps_smmu 0x43 0x0>;
888 reg = <0 0x00880000 0 0x4000>;
892 pinctrl-0 = <&qup_i2c0_default>;
895 #size-cells = <0>;
896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
898 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
908 reg = <0 0x00880000 0 0x4000>;
912 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
915 #size-cells = <0>;
918 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
926 reg = <0 0x00880000 0 0x4000>;
930 pinctrl-0 = <&qup_uart0_default>;
934 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
935 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
942 reg = <0 0x00884000 0 0x4000>;
946 pinctrl-0 = <&qup_i2c1_default>;
949 #size-cells = <0>;
950 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
952 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
962 reg = <0 0x00884000 0 0x4000>;
966 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
969 #size-cells = <0>;
972 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
980 reg = <0 0x00884000 0 0x4000>;
984 pinctrl-0 = <&qup_uart1_default>;
988 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
989 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
996 reg = <0 0x00888000 0 0x4000>;
1000 pinctrl-0 = <&qup_i2c2_default>;
1003 #size-cells = <0>;
1004 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1005 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1016 reg = <0 0x00888000 0 0x4000>;
1020 pinctrl-0 = <&qup_uart2_default>;
1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1025 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1032 reg = <0 0x0088c000 0 0x4000>;
1036 pinctrl-0 = <&qup_i2c3_default>;
1039 #size-cells = <0>;
1040 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1042 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1052 reg = <0 0x0088c000 0 0x4000>;
1056 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1059 #size-cells = <0>;
1062 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1070 reg = <0 0x0088c000 0 0x4000>;
1074 pinctrl-0 = <&qup_uart3_default>;
1078 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1086 reg = <0 0x00890000 0 0x4000>;
1090 pinctrl-0 = <&qup_i2c4_default>;
1093 #size-cells = <0>;
1094 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1096 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1106 reg = <0 0x00890000 0 0x4000>;
1110 pinctrl-0 = <&qup_uart4_default>;
1114 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1115 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1122 reg = <0 0x00894000 0 0x4000>;
1126 pinctrl-0 = <&qup_i2c5_default>;
1129 #size-cells = <0>;
1130 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1132 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1142 reg = <0 0x00894000 0 0x4000>;
1146 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1149 #size-cells = <0>;
1152 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1153 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1160 reg = <0 0x00894000 0 0x4000>;
1164 pinctrl-0 = <&qup_uart5_default>;
1168 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1177 reg = <0 0x00ac0000 0 0x6000>;
1184 iommus = <&apps_smmu 0x4c3 0x0>;
1189 reg = <0 0x00a80000 0 0x4000>;
1193 pinctrl-0 = <&qup_i2c6_default>;
1196 #size-cells = <0>;
1197 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1198 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1199 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1209 reg = <0 0x00a80000 0 0x4000>;
1213 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1216 #size-cells = <0>;
1219 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1227 reg = <0 0x00a80000 0 0x4000>;
1231 pinctrl-0 = <&qup_uart6_default>;
1235 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1236 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1243 reg = <0 0x00a84000 0 0x4000>;
1247 pinctrl-0 = <&qup_i2c7_default>;
1250 #size-cells = <0>;
1251 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1252 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1253 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1263 reg = <0 0x00a84000 0 0x4000>;
1267 pinctrl-0 = <&qup_uart7_default>;
1271 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1272 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1279 reg = <0 0x00a88000 0 0x4000>;
1283 pinctrl-0 = <&qup_i2c8_default>;
1286 #size-cells = <0>;
1287 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1288 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1289 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1299 reg = <0 0x00a88000 0 0x4000>;
1303 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1306 #size-cells = <0>;
1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1317 reg = <0 0x00a88000 0 0x4000>;
1321 pinctrl-0 = <&qup_uart8_default>;
1325 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1326 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1333 reg = <0 0x00a8c000 0 0x4000>;
1337 pinctrl-0 = <&qup_i2c9_default>;
1340 #size-cells = <0>;
1341 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1342 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1343 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1353 reg = <0 0x00a8c000 0 0x4000>;
1357 pinctrl-0 = <&qup_uart9_default>;
1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1369 reg = <0 0x00a90000 0 0x4000>;
1373 pinctrl-0 = <&qup_i2c10_default>;
1376 #size-cells = <0>;
1377 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1378 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1379 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1389 reg = <0 0x00a90000 0 0x4000>;
1393 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1396 #size-cells = <0>;
1399 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1400 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1407 reg = <0 0x00a90000 0 0x4000>;
1411 pinctrl-0 = <&qup_uart10_default>;
1415 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1423 reg = <0 0x00a94000 0 0x4000>;
1427 pinctrl-0 = <&qup_i2c11_default>;
1430 #size-cells = <0>;
1431 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1433 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1443 reg = <0 0x00a94000 0 0x4000>;
1447 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1450 #size-cells = <0>;
1453 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1454 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1461 reg = <0 0x00a94000 0 0x4000>;
1465 pinctrl-0 = <&qup_uart11_default>;
1469 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1470 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1478 reg = <0 0x01500000 0 0x28000>;
1485 reg = <0 0x01620000 0 0x17080>;
1492 reg = <0 0x01638000 0 0x1000>;
1499 reg = <0 0x01650000 0 0x1000>;
1506 reg = <0 0x016e0000 0 0x15080>;
1513 reg = <0 0x01705000 0 0x9000>;
1520 reg = <0 0x0170e000 0 0x6000>;
1527 reg = <0 0x01740000 0 0x1c100>;
1535 reg = <0 0x01d84000 0 0x3000>;
1546 iommus = <&apps_smmu 0xa0 0x0>;
1563 <0 0>,
1564 <0 0>,
1566 <0 0>,
1567 <0 0>,
1568 <0 0>;
1583 reg = <0 0x01d87000 0 0x1000>;
1591 resets = <&ufs_mem_hc 0>;
1593 #phy-cells = <0>;
1600 reg = <0 0x01d90000 0 0x8000>;
1607 iommus = <&apps_smmu 0x440 0x0>,
1608 <&apps_smmu 0x442 0x0>;
1609 reg = <0 0x01e40000 0 0x7000>,
1610 <0 0x01e47000 0 0x2000>,
1611 <0 0x01e04000 0 0x2c000>;
1618 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1628 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1629 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1630 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1637 qcom,smem-states = <&ipa_smp2p_out 0>,
1647 reg = <0 0x01f40000 0 0x20000>;
1653 reg = <0 0x01f60000 0 0x20000>;
1658 reg = <0 0x01fc0000 0 0x40000>;
1663 reg = <0 0x03500000 0 0x300000>,
1664 <0 0x03900000 0 0x300000>,
1665 <0 0x03d00000 0 0x300000>;
1672 gpio-ranges = <&tlmm 0 0 120>;
2127 reg = <0 0x04080000 0 0x4040>;
2130 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2150 qcom,smem-states = <&modem_smp2p_out 0>;
2165 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2166 <0 0x05061000 0 0x800>;
2169 iommus = <&adreno_smmu 0>;
2178 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2188 opp-supported-hw = <0x04>;
2195 opp-supported-hw = <0x07>;
2202 opp-supported-hw = <0x07>;
2209 opp-supported-hw = <0x07>;
2216 opp-supported-hw = <0x07>;
2223 opp-supported-hw = <0x07>;
2230 opp-supported-hw = <0x07>;
2237 opp-supported-hw = <0x07>;
2244 reg = <0 0x05040000 0 0x10000>;
2267 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2268 <0 0x0b490000 0 0x10000>;
2295 reg = <0 0x05090000 0 0x9000>;
2309 reg = <0x0 0x010a2000 0x0 0x1000>,
2310 <0x0 0x010ae000 0x0 0x2000>;
2316 reg = <0 0x06002000 0 0x1000>,
2317 <0 0x16280000 0 0x180000>;
2334 reg = <0 0x06041000 0 0x1000>;
2349 #size-cells = <0>;
2362 reg = <0 0x06042000 0 0x1000>;
2377 #size-cells = <0>;
2390 reg = <0 0x06045000 0 0x1000>;
2405 #size-cells = <0>;
2407 port@0 {
2408 reg = <0>;
2425 reg = <0 0x06046000 0 0x1000>;
2449 reg = <0 0x06048000 0 0x1000>;
2450 iommus = <&apps_smmu 0x04a0 0x20>;
2467 reg = <0 0x06b04000 0 0x1000>;
2482 #size-cells = <0>;
2495 reg = <0 0x06b05000 0 0x1000>;
2519 reg = <0 0x06b06000 0 0x1000>;
2544 reg = <0 0x07040000 0 0x1000>;
2564 reg = <0 0x07140000 0 0x1000>;
2584 reg = <0 0x07240000 0 0x1000>;
2604 reg = <0 0x07340000 0 0x1000>;
2624 reg = <0 0x07440000 0 0x1000>;
2644 reg = <0 0x07540000 0 0x1000>;
2664 reg = <0 0x07640000 0 0x1000>;
2684 reg = <0 0x07740000 0 0x1000>;
2704 reg = <0 0x07800000 0 0x1000>;
2719 #size-cells = <0>;
2721 port@0 {
2722 reg = <0>;
2781 reg = <0 0x07810000 0 0x1000>;
2805 reg = <0 0x08804000 0 0x1000>;
2807 iommus = <&apps_smmu 0x80 0>;
2817 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2818 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2834 opp-avg-kBps = <100000 0>;
2841 opp-avg-kBps = <200000 0>;
2848 reg = <0 0x088dc000 0 0x600>;
2849 iommus = <&apps_smmu 0x20 0x0>;
2851 #size-cells = <0>;
2856 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2857 &config_noc SLAVE_QSPI_0 0>;
2866 reg = <0 0x088e3000 0 0x400>;
2868 #phy-cells = <0>;
2879 reg = <0 0x088e8000 0 0x3000>;
2903 reg = <0 0x090b6300 0 0x600>;
2913 opp-0 {
2941 reg = <0 0x090cd000 0 0x1000>;
2951 opp-0 {
2987 reg = <0 0x09160000 0 0x03200>;
2994 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
3001 reg = <0 0x09680000 0 0x3e200>;
3008 reg = <0 0x09990000 0 0x1600>;
3015 reg = <0 0x0a6f8800 0 0x400>;
3053 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3054 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3061 reg = <0 0x0a600000 0 0xe000>;
3063 iommus = <&apps_smmu 0x540 0>;
3077 reg = <0 0x0aa00000 0 0xff000>;
3091 iommus = <&apps_smmu 0x0c00 0x60>;
3093 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3094 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3137 reg = <0 0x0ab00000 0 0x10000>;
3147 reg = <0 0x0ac00000 0 0x1000>;
3154 reg = <0 0x0ad00000 0 0x10000>;
3166 reg = <0 0x0ae00000 0 0x1000>;
3187 iommus = <&apps_smmu 0x800 0x2>;
3197 reg = <0 0x0ae01000 0 0x8f000>,
3198 <0 0x0aeb0000 0 0x2008>;
3219 interrupts = <0>;
3223 #size-cells = <0>;
3225 port@0 {
3226 reg = <0>;
3268 reg = <0 0x0ae94000 0 0x400>;
3288 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3296 #size-cells = <0>;
3302 #size-cells = <0>;
3304 port@0 {
3305 reg = <0>;
3340 reg = <0 0x0ae94400 0 0x200>,
3341 <0 0x0ae94600 0 0x280>,
3342 <0 0x0ae94a00 0 0x1e0>;
3348 #phy-cells = <0>;
3361 reg = <0 0x0ae90000 0 0x200>,
3362 <0 0x0ae90200 0 0x200>,
3363 <0 0x0ae90400 0 0xc00>,
3364 <0 0x0ae91000 0 0x400>,
3365 <0 0x0ae91400 0 0x400>;
3387 #sound-dai-cells = <0>;
3391 #size-cells = <0>;
3392 port@0 {
3393 reg = <0>;
3433 reg = <0 0x0af00000 0 0x200000>;
3436 <&mdss_dsi0_phy 0>,
3453 reg = <0 0x0b220000 0 0x30000>;
3454 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3462 reg = <0 0x0b2e0000 0 0x20000>;
3468 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3469 <0 0x0c222000 0 0x1ff>; /* SROT */
3479 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3480 <0 0x0c223000 0 0x1ff>; /* SROT */
3490 reg = <0 0x0c2a0000 0 0x31000>;
3496 reg = <0 0x0c300000 0 0x400>;
3498 mboxes = <&apss_shared 0>;
3500 #clock-cells = <0>;
3505 reg = <0 0x0c3f0000 0 0x400>;
3510 reg = <0 0x0c440000 0 0x1100>,
3511 <0 0x0c600000 0 0x2000000>,
3512 <0 0x0e600000 0 0x100000>,
3513 <0 0x0e700000 0 0xa0000>,
3514 <0 0x0c40a000 0 0x26000>;
3518 qcom,ee = <0>;
3519 qcom,channel = <0>;
3521 #size-cells = <0>;
3528 reg = <0 0x146aa000 0 0x2000>;
3533 ranges = <0 0 0x146aa000 0x2000>;
3537 reg = <0x94c 0xc8>;
3543 reg = <0 0x15000000 0 0x100000>;
3637 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3645 reg = <0 0x17a40000 0 0x20000>;
3653 reg = <0 0x17c00000 0 0x10000>;
3659 reg = <0 0x17c10000 0 0x1000>;
3661 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3667 ranges = <0 0 0 0x20000000>;
3669 reg = <0 0x17c20000 0 0x1000>;
3672 frame-number = <0>;
3675 reg = <0x17c21000 0x1000>,
3676 <0x17c22000 0x1000>;
3682 reg = <0x17c23000 0x1000>;
3689 reg = <0x17c25000 0x1000>;
3696 reg = <0x17c27000 0x1000>;
3703 reg = <0x17c29000 0x1000>;
3710 reg = <0x17c2b000 0x1000>;
3717 reg = <0x17c2d000 0x1000>;
3724 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", "drv-1", "drv-2";
3731 qcom,tcs-offset = <0xd00>;
3807 reg = <0 0x18321000 0 0x1400>;
3817 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3829 reg = <0 0x18800000 0 0x800000>;
3831 iommus = <&apps_smmu 0xc0 0x1>;
3852 reg = <0 0x62400000 0 0x100>;
3855 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3873 qcom,smem-states = <&adsp_smp2p_out 0>;
3889 #size-cells = <0>;
3905 #size-cells = <0>;
3923 #size-cells = <0>;
3925 iommus = <&apps_smmu 0x1001 0x0>;
3936 #sound-dai-cells = <0>;
3946 #size-cells = <0>;
3951 iommus = <&apps_smmu 0x1003 0x0>;
3957 iommus = <&apps_smmu 0x1004 0x0>;
3963 iommus = <&apps_smmu 0x1005 0x0>;
3972 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 0x30000>;
3988 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3991 iommus = <&apps_smmu 0x1020 0>,
3992 <&apps_smmu 0x1021 0>,
3993 <&apps_smmu 0x1032 0>;
4014 #size-cells = <0>;
4023 reg = <0 0x63000000 0 0x28>;
4488 thermal-sensors = <&tsens0 0>;
4600 thermal-sensors = <&tsens1 0>;
4803 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;