Lines Matching +full:i2c +full:- +full:qup +full:- +full:v2
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
25 xo_board: xo-board-clk {
26 compatible = "fixed-clock";
27 clock-frequency = <19200000>;
28 #clock-cells = <0>;
31 sleep_clk: sleep-clk {
32 compatible = "fixed-clock";
33 clock-frequency = <32764>;
34 #clock-cells = <0>;
39 #address-cells = <2>;
40 #size-cells = <0>;
44 compatible = "arm,cortex-a55";
47 enable-method = "psci";
48 power-domains = <&cpu_pd0>;
49 power-domain-names = "psci";
50 qcom,freq-domains = <&cpufreq_hw 0>;
51 next-level-cache = <&l2_0>;
52 l2_0: l2-cache {
54 cache-level = <2>;
55 cache-unified;
56 next-level-cache = <&l3_0>;
57 l3_0: l3-cache {
59 cache-level = <3>;
60 cache-unified;
67 compatible = "arm,cortex-a55";
70 enable-method = "psci";
71 power-domains = <&cpu_pd1>;
72 power-domain-names = "psci";
73 qcom,freq-domains = <&cpufreq_hw 0>;
74 next-level-cache = <&l2_100>;
75 l2_100: l2-cache {
77 cache-level = <2>;
78 cache-unified;
79 next-level-cache = <&l3_0>;
85 compatible = "arm,cortex-a55";
88 enable-method = "psci";
89 power-domains = <&cpu_pd2>;
90 power-domain-names = "psci";
91 qcom,freq-domains = <&cpufreq_hw 0>;
92 next-level-cache = <&l2_200>;
93 l2_200: l2-cache {
95 cache-level = <2>;
96 cache-unified;
97 next-level-cache = <&l3_0>;
103 compatible = "arm,cortex-a55";
106 enable-method = "psci";
107 power-domains = <&cpu_pd3>;
108 power-domain-names = "psci";
109 qcom,freq-domains = <&cpufreq_hw 0>;
110 next-level-cache = <&l2_300>;
111 l2_300: l2-cache {
113 cache-level = <2>;
114 cache-unified;
115 next-level-cache = <&l3_0>;
119 cpu-map {
140 idle-states {
141 entry-method = "psci";
143 cpu_off: cpu-sleep-0 {
144 compatible = "arm,idle-state";
145 entry-latency-us = <274>;
146 exit-latency-us = <480>;
147 min-residency-us = <3934>;
148 arm,psci-suspend-param = <0x40000004>;
149 local-timer-stop;
153 domain-idle-states {
154 cluster_sleep_0: cluster-sleep-0 {
155 compatible = "domain-idle-state";
156 entry-latency-us = <584>;
157 exit-latency-us = <2332>;
158 min-residency-us = <6118>;
159 arm,psci-suspend-param = <0x41000044>;
162 cluster_sleep_1: cluster-sleep-1 {
163 compatible = "domain-idle-state";
164 entry-latency-us = <2893>;
165 exit-latency-us = <4023>;
166 min-residency-us = <9987>;
167 arm,psci-suspend-param = <0x41003344>;
173 compatible = "qcom,scm-qdu1000", "qcom,scm";
177 mc_virt: interconnect-0 {
178 compatible = "qcom,qdu1000-mc-virt";
179 qcom,bcm-voters = <&apps_bcm_voter>;
180 #interconnect-cells = <2>;
183 clk_virt: interconnect-1 {
184 compatible = "qcom,qdu1000-clk-virt";
185 qcom,bcm-voters = <&apps_bcm_voter>;
186 #interconnect-cells = <2>;
196 compatible = "arm,cortex-a55-pmu";
201 compatible = "arm,psci-1.0";
204 cpu_pd0: power-domain-cpu0 {
205 #power-domain-cells = <0>;
206 power-domains = <&cluster_pd>;
207 domain-idle-states = <&cpu_off>;
210 cpu_pd1: power-domain-cpu1 {
211 #power-domain-cells = <0>;
212 power-domains = <&cluster_pd>;
213 domain-idle-states = <&cpu_off>;
216 cpu_pd2: power-domain-cpu2 {
217 #power-domain-cells = <0>;
218 power-domains = <&cluster_pd>;
219 domain-idle-states = <&cpu_off>;
222 cpu_pd3: power-domain-cpu3 {
223 #power-domain-cells = <0>;
224 power-domains = <&cluster_pd>;
225 domain-idle-states = <&cpu_off>;
228 cluster_pd: power-domain-cluster {
229 #power-domain-cells = <0>;
230 domain-idle-states = <&cluster_sleep_0 &cluster_sleep_1>;
234 reserved_memory: reserved-memory {
235 #address-cells = <2>;
236 #size-cells = <2>;
241 no-map;
244 xbl_dt_log_mem: xbl-dt-log@80600000 {
246 no-map;
249 xbl_ramdump_mem: xbl-ramdump@80640000 {
251 no-map;
254 aop_image_mem: aop-image@80800000 {
256 no-map;
259 aop_cmd_db_mem: aop-cmd-db@80860000 {
260 compatible = "qcom,cmd-db";
262 no-map;
265 aop_config_mem: aop-config@80880000 {
267 no-map;
270 tme_crash_dump_mem: tme-crash-dump@808a0000 {
272 no-map;
275 tme_log_mem: tme-log@808e0000 {
277 no-map;
280 uefi_log_mem: uefi-log@808e4000 {
282 no-map;
288 no-map;
292 cpucp_fw_mem: cpucp-fw@80b00000 {
294 no-map;
299 no-map;
302 tz_stat_mem: tz-stat@81d00000 {
304 no-map;
309 no-map;
314 no-map;
319 no-map;
324 no-map;
329 no-map;
334 no-map;
339 ipa_fw_mem: ipa-fw@8be00000 {
341 no-map;
344 ipa_gsi_mem: ipa-gsi@8be10000 {
346 no-map;
351 no-map;
354 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
356 no-map;
361 no-map;
364 oem_tenx_mem: oem-tenx@b9600000 {
366 no-map;
369 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
371 no-map;
374 ipa_buffer_mem: ipa-buffer@c3200000 {
376 no-map;
381 compatible = "simple-bus";
382 #address-cells = <2>;
383 #size-cells = <2>;
385 dma-ranges = <0 0 0 0 0x10 0>;
387 gcc: clock-controller@80000 {
388 compatible = "qcom,qdu1000-gcc";
395 #clock-cells = <1>;
396 #reset-cells = <1>;
397 #power-domain-cells = <1>;
400 ecpricc: clock-controller@280000 {
401 compatible = "qcom,qdu1000-ecpricc";
410 #clock-cells = <1>;
411 #reset-cells = <1>;
414 gpi_dma0: dma-controller@900000 {
415 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
429 dma-channels = <12>;
430 dma-channel-mask = <0x3f>;
432 #dma-cells = <3>;
436 compatible = "qcom,geni-se-qup";
440 clock-names = "m-ahb", "s-ahb";
444 interconnect-names = "qup-core";
446 #address-cells = <2>;
447 #size-cells = <2>;
452 compatible = "qcom,geni-uart";
455 clock-names = "se";
456 pinctrl-0 = <&qup_uart0_default>;
457 pinctrl-names = "default";
462 i2c1: i2c@984000 {
463 compatible = "qcom,geni-i2c";
466 clock-names = "se";
468 pinctrl-0 = <&qup_i2c1_data_clk>;
469 pinctrl-names = "default";
470 #address-cells = <1>;
471 #size-cells = <0>;
476 compatible = "qcom,geni-spi";
478 #address-cells = <1>;
479 #size-cells = <0>;
482 clock-names = "se";
483 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
484 pinctrl-names = "default";
488 i2c2: i2c@988000 {
489 compatible = "qcom,geni-i2c";
492 clock-names = "se";
494 pinctrl-0 = <&qup_i2c2_data_clk>;
495 pinctrl-names = "default";
496 #address-cells = <1>;
497 #size-cells = <0>;
502 compatible = "qcom,geni-spi";
504 #address-cells = <1>;
505 #size-cells = <0>;
508 clock-names = "se";
509 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
510 pinctrl-names = "default";
514 i2c3: i2c@98c000 {
515 compatible = "qcom,geni-i2c";
518 clock-names = "se";
520 pinctrl-0 = <&qup_i2c3_data_clk>;
521 pinctrl-names = "default";
522 #address-cells = <1>;
523 #size-cells = <0>;
528 compatible = "qcom,geni-spi";
530 #address-cells = <1>;
531 #size-cells = <0>;
534 clock-names = "se";
535 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
536 pinctrl-names = "default";
540 i2c4: i2c@990000 {
541 compatible = "qcom,geni-i2c";
544 clock-names = "se";
546 pinctrl-0 = <&qup_i2c4_data_clk>;
547 pinctrl-names = "default";
548 #address-cells = <1>;
549 #size-cells = <0>;
554 compatible = "qcom,geni-spi";
556 #address-cells = <1>;
557 #size-cells = <0>;
560 clock-names = "se";
561 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
562 pinctrl-names = "default";
566 i2c5: i2c@994000 {
567 compatible = "qcom,geni-i2c";
570 clock-names = "se";
572 pinctrl-0 = <&qup_i2c5_data_clk>;
573 pinctrl-names = "default";
574 #address-cells = <1>;
575 #size-cells = <0>;
580 compatible = "qcom,geni-spi";
582 #address-cells = <1>;
583 #size-cells = <0>;
586 clock-names = "se";
587 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
588 pinctrl-names = "default";
592 i2c6: i2c@998000 {
593 compatible = "qcom,geni-i2c";
596 clock-names = "se";
598 pinctrl-0 = <&qup_i2c6_data_clk>;
599 pinctrl-names = "default";
600 #address-cells = <1>;
601 #size-cells = <0>;
606 compatible = "qcom,geni-spi";
608 #address-cells = <1>;
609 #size-cells = <0>;
612 clock-names = "se";
613 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
614 pinctrl-names = "default";
619 compatible = "qcom,geni-debug-uart";
622 clock-names = "se";
623 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
624 pinctrl-names = "default";
630 gpi_dma1: dma-controller@a00000 {
631 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
645 dma-channels = <12>;
646 dma-channel-mask = <0x3f>;
648 #dma-cells = <3>;
652 compatible = "qcom,geni-se-qup";
656 clock-names = "m-ahb", "s-ahb";
658 #address-cells = <2>;
659 #size-cells = <2>;
664 compatible = "qcom,geni-uart";
667 clock-names = "se";
668 pinctrl-0 = <&qup_uart8_default>;
669 pinctrl-names = "default";
671 #address-cells = <1>;
672 #size-cells = <0>;
676 i2c9: i2c@a84000 {
677 compatible = "qcom,geni-i2c";
680 clock-names = "se";
682 pinctrl-0 = <&qup_i2c9_data_clk>;
683 pinctrl-names = "default";
684 #address-cells = <1>;
685 #size-cells = <0>;
690 compatible = "qcom,geni-spi";
692 #address-cells = <1>;
693 #size-cells = <0>;
696 clock-names = "se";
697 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
698 pinctrl-names = "default";
702 i2c10: i2c@a88000 {
703 compatible = "qcom,geni-i2c";
706 clock-names = "se";
708 pinctrl-0 = <&qup_i2c10_data_clk>;
709 pinctrl-names = "default";
710 #address-cells = <1>;
711 #size-cells = <0>;
716 compatible = "qcom,geni-spi";
718 #address-cells = <1>;
719 #size-cells = <0>;
722 clock-names = "se";
723 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
724 pinctrl-names = "default";
728 i2c11: i2c@a8c000 {
729 compatible = "qcom,geni-i2c";
732 clock-names = "se";
734 pinctrl-0 = <&qup_i2c11_data_clk>;
735 pinctrl-names = "default";
736 #address-cells = <1>;
737 #size-cells = <0>;
742 compatible = "qcom,geni-spi";
744 #address-cells = <1>;
745 #size-cells = <0>;
748 clock-names = "se";
749 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
750 pinctrl-names = "default";
754 i2c12: i2c@a90000 {
755 compatible = "qcom,geni-i2c";
758 clock-names = "se";
760 pinctrl-0 = <&qup_i2c12_data_clk>;
761 pinctrl-names = "default";
762 #address-cells = <1>;
763 #size-cells = <0>;
768 compatible = "qcom,geni-spi";
770 #address-cells = <1>;
771 #size-cells = <0>;
774 clock-names = "se";
775 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
776 pinctrl-names = "default";
780 i2c13: i2c@a94000 {
781 compatible = "qcom,geni-i2c";
784 clock-names = "se";
786 pinctrl-0 = <&qup_i2c13_data_clk>;
787 pinctrl-names = "default";
788 #address-cells = <1>;
789 #size-cells = <0>;
794 compatible = "qcom,geni-uart";
797 clock-names = "se";
798 pinctrl-0 = <&qup_uart13_default>;
799 pinctrl-names = "default";
801 #address-cells = <1>;
802 #size-cells = <0>;
807 compatible = "qcom,geni-spi";
809 #address-cells = <1>;
810 #size-cells = <0>;
813 clock-names = "se";
814 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
815 pinctrl-names = "default";
819 i2c14: i2c@a98000 {
820 compatible = "qcom,geni-i2c";
823 clock-names = "se";
825 pinctrl-0 = <&qup_i2c14_data_clk>;
826 pinctrl-names = "default";
827 #address-cells = <1>;
828 #size-cells = <0>;
833 compatible = "qcom,geni-spi";
835 #address-cells = <1>;
836 #size-cells = <0>;
839 clock-names = "se";
840 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
841 pinctrl-names = "default";
845 i2c15: i2c@a9c000 {
846 compatible = "qcom,geni-i2c";
849 clock-names = "se";
851 pinctrl-0 = <&qup_i2c15_data_clk>;
852 pinctrl-names = "default";
853 #address-cells = <1>;
854 #size-cells = <0>;
859 compatible = "qcom,geni-spi";
861 #address-cells = <1>;
862 #size-cells = <0>;
865 clock-names = "se";
866 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
867 pinctrl-names = "default";
873 compatible = "qcom,qdu1000-system-noc";
875 qcom,bcm-voters = <&apps_bcm_voter>;
876 #interconnect-cells = <2>;
880 compatible = "qcom,tcsr-mutex";
882 #hwlock-cells = <1>;
886 compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
889 reg-names = "hc", "cqhci";
893 interrupt-names = "hc_irq", "pwr_irq";
898 clock-names = "iface",
906 interconnect-names = "sdhc-ddr", "cpu-sdhc";
907 power-domains = <&rpmhpd QDU1000_CX>;
908 operating-points-v2 = <&sdhc1_opp_table>;
911 dma-coherent;
913 bus-width = <8>;
915 qcom,dll-config = <0x0007642c>;
916 qcom,ddr-config = <0x80040868>;
920 sdhc1_opp_table: opp-table {
921 compatible = "operating-points-v2";
923 opp-384000000 {
924 opp-hz = /bits/ 64 <384000000>;
925 required-opps = <&rpmhpd_opp_nom>;
926 opp-peak-kBps = <6528000 1652800>;
927 opp-avg-kBps = <400000 0>;
933 compatible = "qcom,qdu1000-usb-hs-phy",
934 "qcom,usb-snps-hs-7nm-phy";
936 #phy-cells = <0>;
939 clock-names = "ref";
947 compatible = "qcom,qdu1000-qmp-usb3-uni-phy";
954 clock-names = "aux",
961 reset-names = "phy",
964 #clock-cells = <0>;
965 clock-output-names = "usb3_uni_phy_pipe_clk_src";
967 #phy-cells = <0>;
973 compatible = "qcom,qdu1000-dwc3", "qcom,dwc3";
975 #address-cells = <2>;
976 #size-cells = <2>;
983 clock-names = "cfg_noc",
988 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
990 assigned-clock-rates = <19200000>, <200000000>;
992 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
997 interrupt-names = "pwr_event",
1003 power-domains = <&gcc USB30_PRIM_GDSC>;
1004 required-opps = <&rpmhpd_opp_nom>;
1013 interconnect-names = "usb-ddr",
1014 "apps-usb";
1026 snps,dis-u1-entry-quirk;
1027 snps,dis-u2-entry-quirk;
1030 phy-names = "usb2-phy",
1031 "usb3-phy";
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1054 pdc: interrupt-controller@b220000 {
1055 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
1057 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
1059 #interrupt-cells = <2>;
1060 interrupt-parent = <&intc>;
1061 interrupt-controller;
1065 compatible = "qcom,spmi-pmic-arb";
1071 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1072 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1073 interrupt-names = "periph_irq";
1076 #address-cells = <2>;
1077 #size-cells = <0>;
1078 interrupt-controller;
1079 #interrupt-cells = <4>;
1083 compatible = "qcom,qdu1000-tlmm";
1086 gpio-controller;
1087 #gpio-cells = <2>;
1088 interrupt-controller;
1089 #interrupt-cells = <2>;
1090 gpio-ranges = <&tlmm 0 0 151>;
1091 wakeup-parent = <&pdc>;
1093 qup_uart0_default: qup-uart0-default-state {
1098 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
1103 qup_spi1_data_clk: qup-spi1-data-clk-state {
1108 qup_spi1_cs: qup-spi1-cs-state {
1113 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1118 qup_spi2_data_clk: qup-spi2-data-clk-state {
1123 qup_spi2_cs: qup-spi2-cs-state {
1128 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1133 qup_spi3_data_clk: qup-spi3-data-clk-state {
1138 qup_spi3_cs: qup-spi3-cs-state {
1143 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1148 qup_spi4_data_clk: qup-spi4-data-clk-state {
1153 qup_spi4_cs: qup-spi4-cs-state {
1158 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1163 qup_spi5_data_clk: qup-spi5-data-clk-state {
1168 qup_spi5_cs: qup-spi5-cs-state {
1173 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1178 qup_spi6_data_clk: qup-spi6-data-clk-state {
1183 qup_spi6_cs: qup-spi6-cs-state {
1188 qup_uart7_rx: qup-uart7-rx-state {
1193 qup_uart7_tx: qup-uart7-tx-state {
1198 qup_uart8_default: qup-uart8-default-state {
1203 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1208 qup_spi9_data_clk: qup-spi9-data-clk-state {
1213 qup_spi9_cs: qup-spi9-cs-state {
1218 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1223 qup_spi10_data_clk: qup-spi10-data-clk-state {
1228 qup_spi10_cs: qup-spi10-cs-state {
1233 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1238 qup_spi11_data_clk: qup-spi11-data-clk-state {
1243 qup_spi11_cs: qup-spi11-cs-state {
1248 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1253 qup_spi12_data_clk: qup-spi12-data-clk-state {
1258 qup_spi12_cs: qup-spi12-cs-state {
1263 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1268 qup_spi13_data_clk: qup-spi13-data-clk-state {
1273 qup_spi13_cs: qup-spi13-cs-state {
1278 qup_uart13_default: qup-uart13-default-state {
1283 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1288 qup_spi14_data_clk: qup-spi14-data-clk-state {
1293 qup_spi14_cs: qup-spi14-cs-state {
1298 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1303 qup_spi15_data_clk: qup-spi15-data-clk-state {
1308 qup_spi15_cs: qup-spi15-cs-state {
1313 sdc_on_state: sdc-on-state {
1314 clk-pins {
1316 drive-strength = <16>;
1317 bias-disable;
1320 cmd-pins {
1322 drive-strength = <10>;
1323 bias-pull-up;
1326 data-pins {
1328 drive-strength = <10>;
1329 bias-pull-up;
1332 rclk-pins {
1334 bias-pull-down;
1338 sdc_off_state: sdc-off-state {
1339 clk-pins {
1341 drive-strength = <2>;
1342 bias-disable;
1345 cmd-pins {
1347 drive-strength = <2>;
1348 bias-pull-up;
1351 data-pins {
1353 drive-strength = <2>;
1354 bias-pull-up;
1357 rclk-pins {
1359 bias-pull-down;
1365 compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd";
1368 #address-cells = <1>;
1369 #size-cells = <1>;
1371 pil-reloc@94c {
1372 compatible = "qcom,pil-reloc-info";
1378 compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1380 #iommu-cells = <2>;
1381 #global-interrupts = <2>;
1431 dma-coherent;
1434 intc: interrupt-controller@17200000 {
1435 compatible = "arm,gic-v3";
1439 #interrupt-cells = <3>;
1440 interrupt-controller;
1441 #redistributor-regions = <1>;
1442 redistributor-stride = <0x0 0x20000>;
1446 compatible = "arm,armv7-timer-mem";
1448 #address-cells = <1>;
1449 #size-cells = <1>;
1457 frame-number = <0>;
1463 frame-number = <1>;
1471 frame-number = <2>;
1478 frame-number = <3>;
1485 frame-number = <4>;
1492 frame-number = <5>;
1499 frame-number = <6>;
1505 compatible = "qcom,rpmh-rsc";
1509 reg-names = "drv-0", "drv-1", "drv-2";
1513 qcom,tcs-offset = <0xd00>;
1514 qcom,drv-id = <2>;
1515 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1518 power-domains = <&cluster_pd>;
1520 apps_bcm_voter: bcm-voter {
1521 compatible = "qcom,bcm-voter";
1524 rpmhcc: clock-controller {
1525 compatible = "qcom,qdu1000-rpmh-clk";
1527 clock-names = "xo";
1528 #clock-cells = <1>;
1531 rpmhpd: power-controller {
1532 compatible = "qcom,qdu1000-rpmhpd";
1533 #power-domain-cells = <1>;
1534 operating-points-v2 = <&rpmhpd_opp_table>;
1536 rpmhpd_opp_table: opp-table {
1537 compatible = "operating-points-v2";
1540 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1544 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1548 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1552 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1556 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1560 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1564 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1568 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1572 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1576 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1583 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1585 reg-names = "freq-domain0", "freq-domain1";
1587 clock-names = "xo", "alternate";
1588 #freq-domain-cells = <1>;
1589 #clock-cells = <1>;
1593 compatible = "qcom,qdu1000-gem-noc";
1595 qcom,bcm-voters = <&apps_bcm_voter>;
1596 #interconnect-cells = <2>;
1599 system-cache-controller@19200000 {
1600 compatible = "qcom,qdu1000-llcc";
1610 reg-names = "llcc0_base",
1621 nvmem-cells = <&multi_chan_ddr>;
1622 nvmem-cell-names = "multi-chan-ddr";
1626 compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom";
1628 #address-cells = <1>;
1629 #size-cells = <1>;
1631 multi_chan_ddr: multi-chan-ddr@12b {
1639 compatible = "arm,armv8-timer";