Lines Matching +full:0 +full:x80c00000
28 #clock-cells = <0>;
34 #clock-cells = <0>;
40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0 0x0>;
46 clocks = <&cpufreq_hw 0>;
50 qcom,freq-domains = <&cpufreq_hw 0>;
68 reg = <0x0 0x100>;
69 clocks = <&cpufreq_hw 0>;
73 qcom,freq-domains = <&cpufreq_hw 0>;
86 reg = <0x0 0x200>;
87 clocks = <&cpufreq_hw 0>;
91 qcom,freq-domains = <&cpufreq_hw 0>;
104 reg = <0x0 0x300>;
105 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domains = <&cpufreq_hw 0>;
143 cpu_off: cpu-sleep-0 {
148 arm,psci-suspend-param = <0x40000004>;
154 cluster_sleep_0: cluster-sleep-0 {
159 arm,psci-suspend-param = <0x41000044>;
167 arm,psci-suspend-param = <0x41003344>;
177 mc_virt: interconnect-0 {
192 reg = <0x0 0x80000000 0x0 0x0>;
205 #power-domain-cells = <0>;
211 #power-domain-cells = <0>;
217 #power-domain-cells = <0>;
223 #power-domain-cells = <0>;
229 #power-domain-cells = <0>;
240 reg = <0x0 0x80000000 0x0 0x600000>;
245 reg = <0x0 0x80600000 0x0 0x40000>;
250 reg = <0x0 0x80640000 0x0 0x1c0000>;
255 reg = <0x0 0x80800000 0x0 0x60000>;
261 reg = <0x0 0x80860000 0x0 0x20000>;
266 reg = <0x0 0x80880000 0x0 0x20000>;
271 reg = <0x0 0x808a0000 0x0 0x40000>;
276 reg = <0x0 0x808e0000 0x0 0x4000>;
281 reg = <0x0 0x808e4000 0x0 0x10000>;
287 reg = <0x0 0x80900000 0x0 0x200000>;
293 reg = <0x0 0x80b00000 0x0 0x100000>;
298 reg = <0x0 0x80c00000 0x0 0x40000>;
303 reg = <0x0 0x81d00000 0x0 0x100000>;
308 reg = <0x0 0x81e00000 0x0 0x500000>;
313 reg = <0x0 0x82300000 0x0 0x500000>;
318 reg = <0x0 0x82800000 0x0 0xa00000>;
323 reg = <0x0 0x83200000 0x0 0x400000>;
328 reg = <0x0 0x83600000 0x0 0x400000>;
333 reg = <0x0 0x83a00000 0x0 0x400000>;
337 /* Linux kernel image is loaded at 0x83e00000 */
340 reg = <0x0 0x8be00000 0x0 0x10000>;
345 reg = <0x0 0x8be10000 0x0 0x14000>;
350 reg = <0x0 0x8c000000 0x0 0x12c00000>;
355 reg = <0x0 0x9ec00000 0x0 0x80000>;
360 reg = <0x0 0xa0000000 0x0 0x19600000>;
365 reg = <0x0 0xb9600000 0x0 0x6a00000>;
370 reg = <0x0 0xc0000000 0x0 0x3200000>;
375 reg = <0x0 0xc3200000 0x0 0x12c00000>;
380 soc: soc@0 {
384 ranges = <0 0 0 0 0x10 0>;
385 dma-ranges = <0 0 0 0 0x10 0>;
389 reg = <0x0 0x80000 0x0 0x1f4200>;
392 <0>,
393 <0>,
394 <0>;
402 reg = <0x0 0x00280000 0x0 0x31c00>;
416 reg = <0x0 0x900000 0x0 0x60000>;
430 dma-channel-mask = <0x3f>;
431 iommus = <&apps_smmu 0xf6 0x0>;
437 reg = <0x0 0x9c0000 0x0 0x2000>;
441 iommus = <&apps_smmu 0xe3 0x0>;
442 interconnects = <&clk_virt MASTER_QUP_CORE_0 0
443 &clk_virt SLAVE_QUP_CORE_0 0>;
453 reg = <0x0 0x980000 0x0 0x4000>;
456 pinctrl-0 = <&qup_uart0_default>;
464 reg = <0x0 0x984000 0x0 0x4000>;
468 pinctrl-0 = <&qup_i2c1_data_clk>;
471 #size-cells = <0>;
477 reg = <0x0 0x984000 0x0 0x4000>;
479 #size-cells = <0>;
483 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
490 reg = <0x0 0x988000 0x0 0x4000>;
494 pinctrl-0 = <&qup_i2c2_data_clk>;
497 #size-cells = <0>;
503 reg = <0x0 0x988000 0x0 0x4000>;
505 #size-cells = <0>;
509 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
516 reg = <0x0 0x98c000 0x0 0x4000>;
520 pinctrl-0 = <&qup_i2c3_data_clk>;
523 #size-cells = <0>;
529 reg = <0x0 0x98c000 0x0 0x4000>;
531 #size-cells = <0>;
535 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
542 reg = <0x0 0x990000 0x0 0x4000>;
546 pinctrl-0 = <&qup_i2c4_data_clk>;
549 #size-cells = <0>;
555 reg = <0x0 0x990000 0x0 0x4000>;
557 #size-cells = <0>;
561 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
568 reg = <0x0 0x994000 0x0 0x4000>;
572 pinctrl-0 = <&qup_i2c5_data_clk>;
575 #size-cells = <0>;
581 reg = <0x0 0x994000 0x0 0x4000>;
583 #size-cells = <0>;
587 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
594 reg = <0x0 0x998000 0x0 0x4000>;
598 pinctrl-0 = <&qup_i2c6_data_clk>;
601 #size-cells = <0>;
607 reg = <0x0 0x998000 0x0 0x4000>;
609 #size-cells = <0>;
613 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
620 reg = <0x0 0x99c000 0x0 0x4000>;
623 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
632 reg = <0x0 0xa00000 0x0 0x60000>;
646 dma-channel-mask = <0x3f>;
647 iommus = <&apps_smmu 0x116 0x0>;
653 reg = <0x0 0xac0000 0x0 0x2000>;
657 iommus = <&apps_smmu 0x103 0x0>;
665 reg = <0x0 0xa80000 0x0 0x4000>;
668 pinctrl-0 = <&qup_uart8_default>;
672 #size-cells = <0>;
678 reg = <0x0 0xa84000 0x0 0x4000>;
682 pinctrl-0 = <&qup_i2c9_data_clk>;
685 #size-cells = <0>;
691 reg = <0x0 0xa84000 0x0 0x4000>;
693 #size-cells = <0>;
697 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
704 reg = <0x0 0xa88000 0x0 0x4000>;
708 pinctrl-0 = <&qup_i2c10_data_clk>;
711 #size-cells = <0>;
717 reg = <0x0 0xa88000 0x0 0x4000>;
719 #size-cells = <0>;
723 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
730 reg = <0x0 0xa8c000 0x0 0x4000>;
734 pinctrl-0 = <&qup_i2c11_data_clk>;
737 #size-cells = <0>;
743 reg = <0x0 0xa8c000 0x0 0x4000>;
745 #size-cells = <0>;
749 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
756 reg = <0x0 0xa90000 0x0 0x4000>;
760 pinctrl-0 = <&qup_i2c12_data_clk>;
763 #size-cells = <0>;
769 reg = <0x0 0xa90000 0x0 0x4000>;
771 #size-cells = <0>;
775 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
782 reg = <0x0 0xa94000 0x0 0x4000>;
786 pinctrl-0 = <&qup_i2c13_data_clk>;
789 #size-cells = <0>;
795 reg = <0x0 0xa94000 0x0 0x4000>;
798 pinctrl-0 = <&qup_uart13_default>;
802 #size-cells = <0>;
808 reg = <0x0 0xa94000 0x0 0x4000>;
810 #size-cells = <0>;
814 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
821 reg = <0x0 0xa98000 0x0 0x4000>;
825 pinctrl-0 = <&qup_i2c14_data_clk>;
828 #size-cells = <0>;
834 reg = <0x0 0xa98000 0x0 0x4000>;
836 #size-cells = <0>;
840 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
847 reg = <0x0 0xa9c000 0x0 0x4000>;
851 pinctrl-0 = <&qup_i2c15_data_clk>;
854 #size-cells = <0>;
860 reg = <0x0 0xa9c000 0x0 0x4000>;
862 #size-cells = <0>;
866 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
874 reg = <0x0 0x1640000 0x0 0x45080>;
881 reg = <0x0 0x1f40000 0x0 0x20000>;
887 reg = <0x0 0x08804000 0x0 0x1000>,
888 <0x0 0x08805000 0x0 0x1000>;
904 interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
905 <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
910 iommus = <&apps_smmu 0x80 0x0>;
915 qcom,dll-config = <0x0007642c>;
916 qcom,ddr-config = <0x80040868>;
927 opp-avg-kBps = <400000 0>;
935 reg = <0x0 0x088e3000 0x0 0x120>;
936 #phy-cells = <0>;
948 reg = <0x0 0x088e5000 0x0 0x2000>;
964 #clock-cells = <0>;
967 #phy-cells = <0>;
974 reg = <0 0x0a6f8800 0 0x400>;
1020 reg = <0 0x0a600000 0 0xcd00>;
1023 iommus = <&apps_smmu 0xc0 0x0>;
1035 #size-cells = <0>;
1037 port@0 {
1038 reg = <0>;
1056 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
1057 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
1066 reg = <0x0 0xc400000 0x0 0x3000>,
1067 <0x0 0xc500000 0x0 0x400000>,
1068 <0x0 0xc440000 0x0 0x80000>,
1069 <0x0 0xc4c0000 0x0 0x10000>,
1070 <0x0 0xc42d000 0x0 0x4000>;
1074 qcom,ee = <0>;
1075 qcom,channel = <0>;
1077 #size-cells = <0>;
1084 reg = <0x0 0xf000000 0x0 0x1000000>;
1090 gpio-ranges = <&tlmm 0 0 151>;
1366 reg = <0 0x14680000 0 0x1000>;
1367 ranges = <0 0 0x14680000 0x1000>;
1373 reg = <0x94c 0xc8>;
1379 reg = <0x0 0x15000000 0x0 0x100000>;
1436 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
1437 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
1442 redistributor-stride = <0x0 0x20000>;
1447 reg = <0x0 0x17420000 0x0 0x1000>;
1450 ranges = <0x0 0x0 0x0 0x20000000>;
1453 reg = <0x17421000 0x1000>,
1454 <0x17422000 0x1000>;
1457 frame-number = <0>;
1461 reg = <0x17423000 0x1000>;
1468 reg = <0x17425000 0x1000>,
1469 <0x17426000 0x1000>;
1476 reg = <0x17427000 0x1000>;
1483 reg = <0x17429000 0x1000>;
1490 reg = <0x1742b000 0x1000>;
1497 reg = <0x1742d000 0x1000>;
1506 reg = <0x0 0x17a00000 0x0 0x10000>,
1507 <0x0 0x17a10000 0x0 0x10000>,
1508 <0x0 0x17a20000 0x0 0x10000>;
1509 reg-names = "drv-0", "drv-1", "drv-2";
1513 qcom,tcs-offset = <0xd00>;
1516 <WAKE_TCS 3>, <CONTROL_TCS 0>;
1584 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
1594 reg = <0x0 0x19100000 0x0 0xB8080>;
1601 reg = <0 0x19200000 0 0x80000>,
1602 <0 0x19300000 0 0x80000>,
1603 <0 0x19600000 0 0x80000>,
1604 <0 0x19700000 0 0x80000>,
1605 <0 0x19a00000 0 0x80000>,
1606 <0 0x19b00000 0 0x80000>,
1607 <0 0x19e00000 0 0x80000>,
1608 <0 0x19f00000 0 0x80000>,
1609 <0 0x1a200000 0 0x80000>;
1627 reg = <0 0x221c8000 0 0x1000>;
1632 reg = <0x12b 0x1>;
1633 bits = <0 2>;