Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
316 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
334 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
335 <&gcc GCC_USB3_PHY_PIPE_CLK>;
337 resets = <&gcc GCC_USB3_PHY_BCR>,
338 <&gcc GCC_USB3PHY_PHY_BCR>;
348 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
349 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
351 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
352 <&gcc GCC_USB2A_PHY_BCR>;
362 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
363 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
365 resets = <&gcc GCC_QUSB2_PHY_BCR>,
366 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
553 clocks = <&gcc GCC_PRNG_AHB_CLK>;
627 * <&gcc GCC_CDSP_CFG_AHB_CLK>,
628 * <&gcc GCC_CDSP_TBU_CLK>,
629 * <&gcc GCC_BIMC_CDSP_CLK>,
642 * resets = <&gcc GCC_CDSP_RESTART>;
670 clocks = <&gcc GCC_USB30_MASTER_CLK>,
671 <&gcc GCC_SYS_NOC_USB3_CLK>,
672 <&gcc GCC_USB30_SLEEP_CLK>,
673 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
675 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
676 <&gcc GCC_USB30_MASTER_CLK>;
709 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
710 <&gcc GCC_PCNOC_USB2_CLK>,
711 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
712 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
714 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
715 <&gcc GCC_USB_HS_SYSTEM_CLK>;
884 gcc: clock-controller@1800000 { label
885 compatible = "qcom,gcc-qcs404";
898 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
972 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
973 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
974 <&gcc GCC_PCIE_0_PIPE_ARES>;
993 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
994 <&gcc GCC_SDCC1_APPS_CLK>,
1005 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1016 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1029 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1042 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1057 clocks = <&gcc GCC_ETH_AXI_CLK>,
1058 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
1059 <&gcc GCC_ETH_PTP_CLK>,
1060 <&gcc GCC_ETH_RGMII_CLK>;
1096 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1109 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
1110 <&gcc GCC_BLSP1_AHB_CLK>;
1123 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
1124 <&gcc GCC_BLSP1_AHB_CLK>;
1137 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1138 <&gcc GCC_BLSP1_AHB_CLK>;
1151 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1152 <&gcc GCC_BLSP1_AHB_CLK>;
1165 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1166 <&gcc GCC_BLSP1_AHB_CLK>;
1179 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1180 <&gcc GCC_BLSP1_AHB_CLK>;
1193 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1194 <&gcc GCC_BLSP1_AHB_CLK>;
1207 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1208 <&gcc GCC_BLSP1_AHB_CLK>;
1221 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1222 <&gcc GCC_BLSP1_AHB_CLK>;
1235 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1236 <&gcc GCC_BLSP1_AHB_CLK>;
1249 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1260 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1273 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
1274 <&gcc GCC_BLSP2_AHB_CLK>;
1287 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
1288 <&gcc GCC_BLSP2_AHB_CLK>;
1325 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
1500 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1501 <&gcc GCC_PCIE_0_AUX_CLK>,
1502 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1503 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1506 resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
1507 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
1508 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
1509 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
1510 <&gcc GCC_PCIE_0_BCR>,
1511 <&gcc GCC_PCIE_0_AHB_ARES>;