Lines Matching +full:gcc +full:- +full:msm8917
1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
4 #include <dt-bindings/clock/qcom,rpmcc.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/power/qcom-rpmpd.h>
7 #include <dt-bindings/thermal/thermal.h>
10 interrupt-parent = <&intc>;
12 #address-cells = <2>;
13 #size-cells = <2>;
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
23 xo_board: xo-board {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
37 next-level-cache = <&l2_0>;
38 enable-method = "psci";
40 operating-points-v2 = <&cpu_opp_table>;
41 #cooling-cells = <2>;
42 power-domains = <&cpu_pd0>;
43 power-domain-names = "psci";
45 l2_0: l2-cache {
47 cache-level = <2>;
48 cache-unified;
53 compatible = "arm,cortex-a53";
56 next-level-cache = <&l2_0>;
57 enable-method = "psci";
59 operating-points-v2 = <&cpu_opp_table>;
60 #cooling-cells = <2>;
61 power-domains = <&cpu_pd1>;
62 power-domain-names = "psci";
66 compatible = "arm,cortex-a53";
69 next-level-cache = <&l2_0>;
70 enable-method = "psci";
72 operating-points-v2 = <&cpu_opp_table>;
73 #cooling-cells = <2>;
74 power-domains = <&cpu_pd2>;
75 power-domain-names = "psci";
79 compatible = "arm,cortex-a53";
82 next-level-cache = <&l2_0>;
83 enable-method = "psci";
85 operating-points-v2 = <&cpu_opp_table>;
86 #cooling-cells = <2>;
87 power-domains = <&cpu_pd3>;
88 power-domain-names = "psci";
91 cpu-map {
111 domain-idle-states {
112 cluster_sleep_0: cluster-sleep-0 {
113 compatible = "domain-idle-state";
114 arm,psci-suspend-param = <0x41000053>;
115 entry-latency-us = <700>;
116 exit-latency-us = <1000>;
117 min-residency-us = <6500>;
121 idle-states {
122 entry-method = "psci";
124 cpu_sleep_0: cpu-sleep-0 {
125 compatible = "arm,idle-state";
126 idle-state-name = "standalone-power-collapse";
127 arm,psci-suspend-param = <0x40000003>;
128 entry-latency-us = <125>;
129 exit-latency-us = <180>;
130 min-residency-us = <595>;
131 local-timer-stop;
135 cpu_opp_table: opp-table-cpu {
136 compatible = "operating-points-v2";
137 opp-shared;
139 opp-960000000 {
140 opp-hz = /bits/ 64 <960000000>;
143 opp-1094400000 {
144 opp-hz = /bits/ 64 <1094400000>;
147 opp-1248000000 {
148 opp-hz = /bits/ 64 <1248000000>;
151 opp-1401600000 {
152 opp-hz = /bits/ 64 <1401600000>;
159 compatible = "qcom,scm-msm8916", "qcom,scm";
160 clocks = <&gcc GCC_CRYPTO_CLK>,
161 <&gcc GCC_CRYPTO_AXI_CLK>,
162 <&gcc GCC_CRYPTO_AHB_CLK>;
163 clock-names = "core", "bus", "iface";
164 #reset-cells = <1>;
166 qcom,dload-mode = <&tcsr 0x6100>;
177 compatible = "arm,cortex-a53-pmu";
182 compatible = "arm,psci-1.0";
185 cluster_pd: power-domain-cluster {
186 #power-domain-cells = <0>;
187 domain-idle-states = <&cluster_sleep_0>;
190 cpu_pd0: power-domain-cpu0 {
191 #power-domain-cells = <0>;
192 power-domains = <&cluster_pd>;
193 domain-idle-states = <&cpu_sleep_0>;
196 cpu_pd1: power-domain-cpu1 {
197 #power-domain-cells = <0>;
198 power-domains = <&cluster_pd>;
199 domain-idle-states = <&cpu_sleep_0>;
202 cpu_pd2: power-domain-cpu2 {
203 #power-domain-cells = <0>;
204 power-domains = <&cluster_pd>;
205 domain-idle-states = <&cpu_sleep_0>;
208 cpu_pd3: power-domain-cpu3 {
209 #power-domain-cells = <0>;
210 power-domains = <&cluster_pd>;
211 domain-idle-states = <&cpu_sleep_0>;
216 compatible = "qcom,msm8917-rpm-proc", "qcom,rpm-proc";
218 smd-edge {
221 qcom,smd-edge = <15>;
223 rpm_requests: rpm-requests {
224 compatible = "qcom,rpm-msm8917", "qcom,smd-rpm";
225 qcom,smd-channels = "rpm_requests";
227 rpmcc: clock-controller {
228 compatible = "qcom,rpmcc-msm8917", "qcom,rpmcc";
229 #clock-cells = <1>;
231 clock-names = "xo";
234 rpmpd: power-controller {
235 compatible = "qcom,msm8917-rpmpd";
236 #power-domain-cells = <1>;
237 operating-points-v2 = <&rpmpd_opp_table>;
239 rpmpd_opp_table: opp-table {
240 compatible = "operating-points-v2";
243 opp-level = <RPM_SMD_LEVEL_RETENTION>;
247 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
251 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
255 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
259 opp-level = <RPM_SMD_LEVEL_SVS>;
263 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
267 opp-level = <RPM_SMD_LEVEL_NOM>;
271 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
275 opp-level = <RPM_SMD_LEVEL_TURBO>;
283 reserved-memory {
285 #address-cells = <2>;
286 #size-cells = <2>;
290 no-map;
296 no-map;
299 qcom,rpm-msg-ram = <&rpm_msg_ram>;
304 no-map;
308 compatible = "qcom,rmtfs-mem";
310 no-map;
312 qcom,client-id = <1>;
318 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
319 no-map;
326 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
327 no-map;
334 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
335 no-map;
342 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
343 no-map;
348 smp2p-adsp {
356 qcom,local-pid = <0>;
357 qcom,remote-pid = <2>;
359 adsp_smp2p_out: master-kernel {
360 qcom,entry-name = "master-kernel";
362 #qcom,smem-state-cells = <1>;
365 adsp_smp2p_in: slave-kernel {
366 qcom,entry-name = "slave-kernel";
368 interrupt-controller;
369 #interrupt-cells = <2>;
373 smp2p-modem {
381 qcom,local-pid = <0>;
382 qcom,remote-pid = <1>;
384 modem_smp2p_out: master-kernel {
385 qcom,entry-name = "master-kernel";
387 #qcom,smem-state-cells = <1>;
390 modem_smp2p_in: slave-kernel {
391 qcom,entry-name = "slave-kernel";
393 interrupt-controller;
394 #interrupt-cells = <2>;
398 smp2p-wcnss {
406 qcom,local-pid = <0>;
407 qcom,remote-pid = <4>;
409 wcnss_smp2p_out: master-kernel {
410 qcom,entry-name = "master-kernel";
412 #qcom,smem-state-cells = <1>;
415 wcnss_smp2p_in: slave-kernel {
416 qcom,entry-name = "slave-kernel";
418 interrupt-controller;
419 #interrupt-cells = <2>;
426 #address-cells = <1>;
427 #size-cells = <0>;
434 #qcom,smem-state-cells = <1>;
441 interrupt-controller;
442 #interrupt-cells = <2>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
455 compatible = "simple-bus";
457 #address-cells = <1>;
458 #size-cells = <1>;
461 compatible = "qcom,rpm-msg-ram";
466 compatible = "qcom,usb-hs-28nm-femtophy";
468 #phy-cells = <0>;
470 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
471 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
472 clock-names = "ref", "ahb", "sleep";
473 resets = <&gcc GCC_QUSB2_PHY_BCR>,
474 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
475 reset-names = "phy", "por";
480 compatible = "qcom,msm8917-qfprom", "qcom,qfprom";
482 #address-cells = <1>;
483 #size-cells = <1>;
490 tsens_s5_p1: s5-p1@1d9 {
495 tsens_s5_p2: s5-p2@1d9 {
500 tsens_s6_p1: s6-p1@1da {
505 tsens_s6_p2: s6-p2@1db {
510 tsens_s7_p1: s7-p1@1dc {
515 tsens_s7_p2: s7-p2@1dc {
520 tsens_s8_p1: s8-p1@1dd {
525 tsens_s8_p2: s8-p2@1de {
540 tsens_s0_p1: s0-p1@210 {
545 tsens_s0_p2: s0-p2@211 {
550 tsens_s1_p1: s1-p1@211 {
555 tsens_s1_p2: s1-p2@212 {
560 tsens_s2_p1: s2-p1@213 {
565 tsens_s2_p2: s2-p2@214 {
570 tsens_s3_p1: s3-p1@214 {
575 tsens_s3_p2: s3-p2@215 {
580 tsens_s4_p1: s4-p1@216 {
585 tsens_s4_p2: s4-p2@217 {
590 tsens_s9_p1: s9-p1@230{
595 tsens_s9_p2: s9-p2@230 {
600 tsens_s10_p1: s10-p1@231 {
605 tsens_s10_p2: s10-p2@232 {
614 clocks = <&gcc GCC_PRNG_AHB_CLK>;
615 clock-names = "core";
618 tsens: thermal-sensor@4a9000 {
619 compatible = "qcom,msm8937-tsens", "qcom,tsens-v1";
623 interrupt-names = "uplow";
624 nvmem-cells = <&tsens_mode>,
637 nvmem-cell-names = "mode",
651 #thermal-sensor-cells = <1>;
660 compatible = "qcom,msm8917-pinctrl";
663 gpio-controller;
664 gpio-ranges = <&tlmm 0 0 134>;
665 #gpio-cells = <2>;
666 interrupt-controller;
667 #interrupt-cells = <2>;
669 blsp1_i2c2_default: blsp1-i2c2-default-state {
672 drive-strength = <2>;
673 bias-disable;
676 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
679 drive-strength = <2>;
680 bias-disable;
683 blsp1_i2c3_default: blsp1-i2c3-default-state {
686 drive-strength = <2>;
687 bias-disable;
690 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
693 drive-strength = <2>;
694 bias-disable;
697 blsp1_i2c4_default: blsp1-i2c4-default-state {
700 drive-strength = <2>;
701 bias-disable;
704 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
707 drive-strength = <2>;
708 bias-disable;
711 blsp2_i2c1_default: blsp2-i2c1-default-state {
714 drive-strength = <2>;
715 bias-disable;
718 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
721 drive-strength = <2>;
722 bias-disable;
725 blsp1_spi3_default: blsp1-spi3-default-state {
726 cs-pins {
729 drive-strength = <2>;
730 bias-disable;
733 spi-pins {
736 drive-strength = <12>;
737 bias-disable;
741 blsp1_spi3_sleep: blsp1-spi3-sleep-state {
742 cs-pins {
745 drive-strength = <2>;
746 bias-disable;
749 spi-pins {
752 drive-strength = <2>;
753 bias-pull-down;
757 blsp2_spi2_default: blsp2-spi2-default-state {
758 cs0-pins {
761 drive-strength = <16>;
762 bias-disable;
765 cs1-pins {
768 drive-strength = <16>;
769 bias-disable;
772 spi-pins {
775 drive-strength = <16>;
776 bias-disable;
780 blsp2_spi2_sleep: blsp2-spi2-sleep-state {
781 cs0-pins {
784 drive-strength = <2>;
785 bias-disable;
788 cs1-pins {
791 drive-strength = <2>;
792 bias-disable;
795 spi-pins {
798 drive-strength = <2>;
799 bias-pull-down;
803 blsp1_uart1_default: blsp1-uart1-default-state {
806 drive-strength = <2>;
807 bias-disable;
810 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
813 drive-strength = <2>;
814 bias-disable;
817 blsp1_uart2_default: blsp1-uart2-default-state {
820 drive-strength = <2>;
821 bias-disable;
824 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
827 drive-strength = <2>;
828 bias-pull-down;
831 sdc1_default: sdc1-default-state {
832 clk-pins {
834 bias-disable;
835 drive-strength = <16>;
838 cmd-pins {
840 bias-pull-up;
841 drive-strength = <10>;
844 data-pins {
846 bias-pull-up;
847 drive-strength = <10>;
850 rclk-pins {
852 bias-pull-down;
856 sdc1_sleep: sdc1-sleep-state {
857 clk-pins {
859 bias-disable;
860 drive-strength = <2>;
863 cmd-pins {
865 bias-pull-up;
866 drive-strength = <2>;
869 data-pins {
871 bias-pull-up;
872 drive-strength = <2>;
875 rclk-pins {
877 bias-pull-down;
881 sdc2_default: sdc2-default-state {
882 clk-pins {
884 bias-disable;
885 drive-strength = <16>;
888 cmd-pins {
890 bias-pull-up;
891 drive-strength = <10>;
894 data-pins {
896 bias-pull-up;
897 drive-strength = <10>;
901 sdc2_sleep: sdc2-sleep-state {
902 clk-pins {
904 bias-disable;
905 drive-strength = <2>;
908 cmd-pins {
910 bias-pull-up;
911 drive-strength = <2>;
914 data-pins {
916 bias-pull-up;
917 drive-strength = <2>;
921 wcnss_pin_a: wcnss-active-state {
922 wcss-wlan-pins {
925 drive-strength = <6>;
926 bias-pull-up;
930 wcss-wlan0-pins {
933 drive-strength = <6>;
934 bias-pull-up;
938 wcss-wlan1-pins {
941 drive-strength = <6>;
942 bias-pull-up;
946 wcss-wlan2-pins {
949 drive-strength = <6>;
950 bias-pull-up;
956 gcc: clock-controller@1800000 { label
957 compatible = "qcom,gcc-msm8917";
959 #clock-cells = <1>;
960 #reset-cells = <1>;
961 #power-domain-cells = <1>;
966 clock-names = "xo",
973 compatible = "qcom,tcsr-mutex";
975 #hwlock-cells = <1>;
979 compatible = "qcom,tcsr-msm8917", "syscon";
983 mdss: display-subsystem@1a00000 {
987 reg-names = "mdss_phys", "vbif_phys";
990 power-domains = <&gcc MDSS_GDSC>;
992 clocks = <&gcc GCC_MDSS_AHB_CLK>,
993 <&gcc GCC_MDSS_AXI_CLK>,
994 <&gcc GCC_MDSS_VSYNC_CLK>;
995 clock-names = "iface",
1001 interrupt-controller;
1002 #interrupt-cells = <1>;
1004 #address-cells = <1>;
1005 #size-cells = <1>;
1009 mdp: display-controller@1a01000 {
1010 compatible = "qcom,msm8917-mdp5", "qcom,mdp5";
1012 reg-names = "mdp_phys";
1014 interrupt-parent = <&mdss>;
1017 power-domains = <&gcc MDSS_GDSC>;
1019 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1020 <&gcc GCC_MDSS_AXI_CLK>,
1021 <&gcc GCC_MDSS_MDP_CLK>,
1022 <&gcc GCC_MDSS_VSYNC_CLK>;
1023 clock-names = "iface",
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1038 remote-endpoint = <&mdss_dsi0_in>;
1045 compatible = "qcom,mdss-dsi-ctrl";
1047 reg-names = "dsi_ctrl";
1049 interrupt-parent = <&mdss>;
1052 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1053 <&gcc PCLK0_CLK_SRC>;
1054 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1057 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1058 <&gcc GCC_MDSS_AHB_CLK>,
1059 <&gcc GCC_MDSS_AXI_CLK>,
1060 <&gcc GCC_MDSS_BYTE0_CLK>,
1061 <&gcc GCC_MDSS_PCLK0_CLK>,
1062 <&gcc GCC_MDSS_ESC0_CLK>;
1063 clock-names = "mdp_core",
1071 operating-points-v2 = <&mdss_dsi0_opp_table>;
1072 power-domains = <&rpmpd MSM8917_VDDCX>;
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1085 remote-endpoint = <&mdp5_intf1_out>;
1097 mdss_dsi0_opp_table: opp-table {
1098 compatible = "operating-points-v2";
1100 opp-125000000 {
1101 opp-hz = /bits/ 64 <125000000>;
1102 required-opps = <&rpmpd_opp_svs>;
1105 opp-187500000 {
1106 opp-hz = /bits/ 64 <187500000>;
1107 required-opps = <&rpmpd_opp_nom>;
1113 compatible = "qcom,dsi-phy-28nm-8937";
1117 reg-names = "dsi_pll",
1121 #clock-cells = <1>;
1122 #phy-cells = <0>;
1124 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1126 clock-names = "iface", "ref";
1131 compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135 #iommu-cells = <1>;
1137 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1138 <&gcc GCC_APSS_TCU_CLK>;
1139 clock-names = "iface", "bus";
1141 qcom,iommu-secure-id = <17>;
1144 iommu-ctx@14000 {
1145 compatible = "qcom,msm-iommu-v1-ns";
1151 iommu-ctx@15000 {
1152 compatible = "qcom,msm-iommu-v1-ns";
1158 iommu-ctx@16000 {
1159 compatible = "qcom,msm-iommu-v1-ns";
1166 compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
1169 #address-cells = <1>;
1170 #size-cells = <1>;
1171 #iommu-cells = <1>;
1173 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1174 <&gcc GCC_GFX_TCU_CLK>;
1175 clock-names = "iface", "bus";
1176 qcom,iommu-secure-id = <18>;
1178 iommu-ctx@0 {
1179 compatible = "qcom,msm-iommu-v2-ns";
1186 compatible = "qcom,adreno-306.32", "qcom,adreno";
1188 reg-names = "kgsl_3d0_reg_memory";
1190 interrupt-names = "kgsl_3d0_irq";
1191 clock-names = "core",
1196 clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1197 <&gcc GCC_OXILI_AHB_CLK>,
1198 <&gcc GCC_BIMC_GFX_CLK>,
1199 <&gcc GCC_BIMC_GPU_CLK>,
1200 <&gcc GFX3D_CLK_SRC>;
1201 power-domains = <&gcc OXILI_GX_GDSC>;
1202 operating-points-v2 = <&gpu_opp_table>;
1203 #cooling-cells = <2>;
1209 gpu_opp_table: opp-table {
1210 compatible = "operating-points-v2";
1212 opp-19200000 {
1213 opp-hz = /bits/ 64 <19200000>;
1216 opp-270000000 {
1217 opp-hz = /bits/ 64 <270000000>;
1220 opp-400000000 {
1221 opp-hz = /bits/ 64 <400000000>;
1224 opp-484800000 {
1225 opp-hz = /bits/ 64 <484800000>;
1228 opp-523200000 {
1229 opp-hz = /bits/ 64 <523200000>;
1232 opp-598000000 {
1233 opp-hz = /bits/ 64 <598000000>;
1239 compatible = "qcom,spmi-pmic-arb";
1245 reg-names = "core",
1250 interrupt-names = "periph_irq";
1254 #address-cells = <2>;
1255 #size-cells = <0>;
1256 interrupt-controller;
1257 #interrupt-cells = <4>;
1260 bam_dmux_dma: dma-controller@4044000 {
1261 compatible = "qcom,bam-v1.7.0";
1264 #dma-cells = <1>;
1267 num-channels = <6>;
1268 qcom,num-ees = <1>;
1269 qcom,powered-remotely;
1275 compatible = "qcom,sdhci-msm-v4";
1278 reg-names = "hc", "core";
1282 interrupt-names = "hc_irq", "pwr_irq";
1283 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1284 <&gcc GCC_SDCC1_APPS_CLK>,
1286 clock-names = "iface", "core", "xo";
1287 pinctrl-0 = <&sdc1_default>;
1288 pinctrl-1 = <&sdc1_sleep>;
1289 pinctrl-names = "default", "sleep";
1290 power-domains = <&rpmpd MSM8917_VDDCX>;
1291 mmc-hs200-1_8v;
1292 mmc-hs400-1_8v;
1293 mmc-ddr-1_8v;
1294 bus-width = <8>;
1295 non-removable;
1300 compatible = "qcom,sdhci-msm-v4";
1303 reg-names = "hc", "core";
1307 interrupt-names = "hc_irq", "pwr_irq";
1308 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1309 <&gcc GCC_SDCC2_APPS_CLK>,
1311 clock-names = "iface", "core", "xo";
1312 pinctrl-0 = <&sdc2_default>;
1313 pinctrl-1 = <&sdc2_sleep>;
1314 pinctrl-names = "default", "sleep";
1315 power-domains = <&rpmpd MSM8917_VDDCX>;
1316 bus-width = <4>;
1320 blsp1_dma: dma-controller@7884000 {
1321 compatible = "qcom,bam-v1.7.0";
1324 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1325 clock-names = "bam_clk";
1326 qcom,controlled-remotely;
1327 #dma-cells = <1>;
1328 num-channels = <12>;
1329 qcom,num-ees = <4>;
1333 blsp2_dma: dma-controller@7ac4000 {
1334 compatible = "qcom,bam-v1.7.0";
1337 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1338 clock-names = "bam_clk";
1339 qcom,controlled-remotely;
1340 #dma-cells = <1>;
1341 num-channels = <10>;
1342 qcom,num-ees = <4>;
1347 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1350 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1351 <&gcc GCC_BLSP1_AHB_CLK>;
1352 clock-names = "core", "iface";
1354 dma-names = "tx", "rx";
1355 pinctrl-0 = <&blsp1_uart1_default>;
1356 pinctrl-1 = <&blsp1_uart1_sleep>;
1357 pinctrl-names = "default", "sleep";
1362 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1365 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1366 <&gcc GCC_BLSP1_AHB_CLK>;
1367 clock-names = "core", "iface";
1369 dma-names = "tx", "rx";
1370 pinctrl-0 = <&blsp1_uart2_default>;
1371 pinctrl-1 = <&blsp1_uart2_sleep>;
1372 pinctrl-names = "default", "sleep";
1377 compatible = "qcom,i2c-qup-v2.2.1";
1380 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1381 <&gcc GCC_BLSP1_AHB_CLK>;
1382 clock-names = "core", "iface";
1384 dma-names = "tx", "rx";
1385 pinctrl-0 = <&blsp1_i2c2_default>;
1386 pinctrl-1 = <&blsp1_i2c2_sleep>;
1387 pinctrl-names = "default", "sleep";
1388 #address-cells = <1>;
1389 #size-cells = <0>;
1394 compatible = "qcom,i2c-qup-v2.2.1";
1397 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1398 <&gcc GCC_BLSP1_AHB_CLK>;
1399 clock-names = "core", "iface";
1401 dma-names = "tx", "rx";
1402 pinctrl-0 = <&blsp1_i2c3_default>;
1403 pinctrl-1 = <&blsp1_i2c3_sleep>;
1404 pinctrl-names = "default", "sleep";
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1411 compatible = "qcom,spi-qup-v2.2.1";
1414 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1415 <&gcc GCC_BLSP1_AHB_CLK>;
1416 clock-names = "core", "iface";
1418 dma-names = "tx", "rx";
1419 pinctrl-0 = <&blsp1_spi3_default>;
1420 pinctrl-1 = <&blsp1_spi3_sleep>;
1421 pinctrl-names = "default", "sleep";
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1428 compatible = "qcom,i2c-qup-v2.2.1";
1431 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1432 <&gcc GCC_BLSP1_AHB_CLK>;
1433 clock-names = "core", "iface";
1435 dma-names = "tx", "rx";
1436 pinctrl-0 = <&blsp1_i2c4_default>;
1437 pinctrl-1 = <&blsp1_i2c4_sleep>;
1438 pinctrl-names = "default", "sleep";
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1445 compatible = "qcom,i2c-qup-v2.2.1";
1448 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1449 <&gcc GCC_BLSP2_AHB_CLK>;
1450 clock-names = "core", "iface";
1452 dma-names = "tx", "rx";
1453 pinctrl-0 = <&blsp2_i2c1_default>;
1454 pinctrl-1 = <&blsp2_i2c1_sleep>;
1455 pinctrl-names = "default", "sleep";
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1462 compatible = "qcom,spi-qup-v2.2.1";
1465 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
1466 <&gcc GCC_BLSP2_AHB_CLK>;
1467 clock-names = "core", "iface";
1469 dma-names = "tx", "rx";
1470 pinctrl-0 = <&blsp2_spi2_default>;
1471 pinctrl-1 = <&blsp2_spi2_sleep>;
1472 pinctrl-names = "default", "sleep";
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1479 compatible = "qcom,ci-hdrc";
1484 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1485 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1486 clock-names = "iface", "core";
1487 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1488 assigned-clock-rates = <80000000>;
1489 resets = <&gcc GCC_USB_HS_BCR>;
1490 reset-names = "core";
1493 hnp-disable;
1494 srp-disable;
1495 adp-disable;
1496 ahb-burst-config = <0>;
1497 phy-names = "usb-phy";
1500 #reset-cells = <1>;
1504 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1508 reg-names = "ccu", "dxe", "pmu";
1510 memory-region = <&wcnss_mem>;
1512 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1517 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1519 power-domains = <&rpmpd MSM8917_VDDCX>,
1521 power-domain-names = "cx", "mx";
1523 qcom,smem-states = <&wcnss_smp2p_out 0>;
1524 qcom,smem-state-names = "stop";
1526 pinctrl-0 = <&wcnss_pin_a>;
1527 pinctrl-names = "default";
1533 clock-names = "xo";
1536 smd-edge {
1540 qcom,smd-edge = <6>;
1541 qcom,remote-pid = <4>;
1547 qcom,smd-channels = "WCNSS_CTRL";
1552 compatible = "qcom,wcnss-bt";
1556 compatible = "qcom,wcnss-wlan";
1560 interrupt-names = "tx", "rx";
1562 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1563 qcom,smem-state-names = "tx-enable",
1564 "tx-rings-empty";
1570 intc: interrupt-controller@b000000 {
1571 compatible = "qcom,msm-qgic2";
1574 interrupt-controller;
1575 #interrupt-cells = <3>;
1579 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
1581 #mbox-cells = <1>;
1582 clocks = <&a53pll>, <&gcc GPLL0_EARLY>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1583 clock-names = "pll", "aux", "ref";
1584 #clock-cells = <0>;
1588 compatible = "qcom,msm8939-a53pll";
1591 clock-names = "xo";
1592 #clock-cells = <0>;
1593 operating-points-v2 = <&pll_opp_table>;
1595 pll_opp_table: opp-table {
1596 compatible = "operating-points-v2";
1598 opp-960000000 {
1599 opp-hz = /bits/ 64 <960000000>;
1602 opp-1094400000 {
1603 opp-hz = /bits/ 64 <1094400000>;
1606 opp-1248000000 {
1607 opp-hz = /bits/ 64 <1248000000>;
1610 opp-1401600000 {
1611 opp-hz = /bits/ 64 <1401600000>;
1617 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1623 compatible = "arm,armv7-timer-mem";
1626 #address-cells = <1>;
1627 #size-cells = <1>;
1632 frame-number = <0>;
1639 frame-number = <1>;
1646 frame-number = <2>;
1653 frame-number = <3>;
1660 frame-number = <4>;
1667 frame-number = <5>;
1674 frame-number = <6>;
1682 compatible = "arm,armv8-timer";
1689 thermal_zones: thermal-zones {
1690 aoss-thermal {
1691 polling-delay-passive = <250>;
1693 thermal-sensors = <&tsens 0>;
1696 aoss_alert0: trip-point0 {
1704 camera-thermal {
1705 polling-delay-passive = <250>;
1707 thermal-sensors = <&tsens 3>;
1710 camera_alert0: trip-point0 {
1718 cpuss1-thermal {
1719 polling-delay-passive = <250>;
1721 thermal-sensors = <&tsens 4>;
1723 cooling-maps {
1726 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1734 cpuss1_alert0: trip-point0 {
1740 cpuss1_alert1: trip-point1 {
1746 cpuss1_crit: cpuss1-crit {
1754 cpu0-thermal {
1755 polling-delay-passive = <250>;
1757 thermal-sensors = <&tsens 5>;
1759 cooling-maps {
1762 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1770 cpu0_alert0: trip-point0 {
1776 cpu0_alert1: trip-point1 {
1782 cpu0_crit: cpu-crit {
1790 cpu1-thermal {
1791 polling-delay-passive = <250>;
1793 thermal-sensors = <&tsens 6>;
1795 cooling-maps {
1798 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1806 cpu1_alert0: trip-point0 {
1812 cpu1_alert1: trip-point1 {
1818 cpu1_crit: cpu-crit {
1826 cpu2-thermal {
1827 polling-delay-passive = <250>;
1829 thermal-sensors = <&tsens 7>;
1831 cooling-maps {
1834 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1842 cpu2_alert0: trip-point0 {
1848 cpu2_alert1: trip-point1 {
1854 cpu2_crit: cpu-crit {
1862 cpu3-thermal {
1863 polling-delay-passive = <250>;
1865 thermal-sensors = <&tsens 8>;
1867 cooling-maps {
1870 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1878 cpu3_alert0: trip-point0 {
1884 cpu3_alert1: trip-point1 {
1890 cpu3_crit: cpu-crit {
1898 gpu-thermal {
1899 polling-delay-passive = <250>;
1901 thermal-sensors = <&tsens 9>;
1903 cooling-maps {
1906 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1911 gpu_alert: trip-point0 {
1917 gpu_crit: gpu-crit {
1926 mdm-core-thermal {
1927 polling-delay-passive = <250>;
1929 thermal-sensors = <&tsens 1>;
1932 mdm_core_alert0: trip-point0 {
1940 q6-thermal {
1941 polling-delay-passive = <250>;
1943 thermal-sensors = <&tsens 2>;
1946 q6_alert0: trip-point0 {