Lines Matching +full:1 +full:a01000

30 		#address-cells = <1>;
164 #reset-cells = <1>;
229 #clock-cells = <1>;
236 #power-domain-cells = <1>;
312 qcom,client-id = <1>;
362 #qcom,smem-state-cells = <1>;
382 qcom,remote-pid = <1>;
387 #qcom,smem-state-cells = <1>;
412 #qcom,smem-state-cells = <1>;
426 #address-cells = <1>;
434 #qcom,smem-state-cells = <1>;
437 hexagon_smsm: hexagon@1 {
438 reg = <1>;
457 #address-cells = <1>;
458 #size-cells = <1>;
482 #address-cells = <1>;
483 #size-cells = <1>;
485 tsens_base1: base1@1d8 {
486 reg = <0x1d8 1>;
490 tsens_s5_p1: s5-p1@1d9 {
491 reg = <0x1d9 1>;
495 tsens_s5_p2: s5-p2@1d9 {
500 tsens_s6_p1: s6-p1@1da {
505 tsens_s6_p2: s6-p2@1db {
506 reg = <0x1db 1>;
510 tsens_s7_p1: s7-p1@1dc {
511 reg = <0x1dc 1>;
515 tsens_s7_p2: s7-p2@1dc {
520 tsens_s8_p1: s8-p1@1dd {
525 tsens_s8_p2: s8-p2@1de {
526 reg = <0x1de 1>;
530 tsens_base2: base2@1df {
531 reg = <0x1df 1>;
536 reg = <0x210 1>;
546 reg = <0x211 1>;
547 bits = <1 6>;
566 reg = <0x214 1>;
567 bits = <1 6>;
586 reg = <0x217 1>;
587 bits = <1 6>;
591 reg = <0x230 1>;
606 reg = <0x232 1>;
651 #thermal-sensor-cells = <1>;
959 #clock-cells = <1>;
960 #reset-cells = <1>;
961 #power-domain-cells = <1>;
964 <&mdss_dsi0_phy 1>,
975 #hwlock-cells = <1>;
983 mdss: display-subsystem@1a00000 {
1002 #interrupt-cells = <1>;
1004 #address-cells = <1>;
1005 #size-cells = <1>;
1009 mdp: display-controller@1a01000 {
1031 #address-cells = <1>;
1044 mdss_dsi0: dsi@1a94000 {
1055 <&mdss_dsi0_phy 1>;
1074 #address-cells = <1>;
1078 #address-cells = <1>;
1089 port@1 {
1090 reg = <1>;
1112 mdss_dsi0_phy: phy@1a94a00 {
1121 #clock-cells = <1>;
1130 apps_iommu: iommu@1e20000 {
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135 #iommu-cells = <1>;
1165 gpu_iommu: iommu@1f08000 {
1169 #address-cells = <1>;
1170 #size-cells = <1>;
1171 #iommu-cells = <1>;
1185 gpu: gpu@1c00000 {
1264 #dma-cells = <1>;
1268 qcom,num-ees = <1>;
1288 pinctrl-1 = <&sdc1_sleep>;
1291 mmc-hs200-1_8v;
1292 mmc-hs400-1_8v;
1293 mmc-ddr-1_8v;
1313 pinctrl-1 = <&sdc2_sleep>;
1327 #dma-cells = <1>;
1340 #dma-cells = <1>;
1353 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1356 pinctrl-1 = <&blsp1_uart1_sleep>;
1371 pinctrl-1 = <&blsp1_uart2_sleep>;
1386 pinctrl-1 = <&blsp1_i2c2_sleep>;
1388 #address-cells = <1>;
1403 pinctrl-1 = <&blsp1_i2c3_sleep>;
1405 #address-cells = <1>;
1420 pinctrl-1 = <&blsp1_spi3_sleep>;
1422 #address-cells = <1>;
1437 pinctrl-1 = <&blsp1_i2c4_sleep>;
1439 #address-cells = <1>;
1454 pinctrl-1 = <&blsp2_i2c1_sleep>;
1456 #address-cells = <1>;
1471 pinctrl-1 = <&blsp2_spi2_sleep>;
1473 #address-cells = <1>;
1500 #reset-cells = <1>;
1514 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1581 #mbox-cells = <1>;
1626 #address-cells = <1>;
1627 #size-cells = <1>;
1639 frame-number = <1>;
1686 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1929 thermal-sensors = <&tsens 1>;