Lines Matching +full:0 +full:x0200a000
20 #clock-cells = <0>;
25 #clock-cells = <0>;
31 #size-cells = <0>;
35 reg = <0x100>;
54 reg = <0x101>;
67 reg = <0x102>;
80 reg = <0x103>;
112 cluster_sleep_0: cluster-sleep-0 {
114 arm,psci-suspend-param = <0x41000053>;
124 cpu_sleep_0: cpu-sleep-0 {
127 arm,psci-suspend-param = <0x40000003>;
166 qcom,dload-mode = <&tcsr 0x6100>;
172 reg = <0 0x80000000 0 0>;
186 #power-domain-cells = <0>;
191 #power-domain-cells = <0>;
197 #power-domain-cells = <0>;
203 #power-domain-cells = <0>;
209 #power-domain-cells = <0>;
220 qcom,ipc = <&apcs 8 0>;
289 reg = <0x0 0x85b00000 0x0 0x800000>;
295 reg = <0x0 0x86300000 0x0 0x100000>;
303 reg = <0x0 0x86400000 0x0 0x400000>;
309 reg = <0x0 0x92100000 0x0 0x180000>;
316 size = <0x0 0x1100000>;
317 alignment = <0x0 0x100000>;
318 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
324 size = <0x0 0x100000>;
325 alignment = <0x0 0x100000>;
326 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
332 size = <0x0 0x400000>;
333 alignment = <0x0 0x100000>;
334 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
340 size = <0x0 0x700000>;
341 alignment = <0x0 0x100000>;
342 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
356 qcom,local-pid = <0>;
381 qcom,local-pid = <0>;
406 qcom,local-pid = <0>;
427 #size-cells = <0>;
429 mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>;
431 apps_smsm: apps@0 {
432 reg = <0>;
454 soc: soc@0 {
456 ranges = <0 0 0 0xffffffff>;
462 reg = <0x00060000 0x8000>;
467 reg = <0x0006c000 0x200>;
468 #phy-cells = <0>;
481 reg = <0x000a4000 0x1000>;
486 reg = <0x1d8 1>;
487 bits = <0 8>;
491 reg = <0x1d9 1>;
492 bits = <0 6>;
496 reg = <0x1d9 2>;
501 reg = <0x1da 2>;
506 reg = <0x1db 1>;
511 reg = <0x1dc 1>;
512 bits = <0 6>;
516 reg = <0x1dc 2>;
521 reg = <0x1dd 2>;
526 reg = <0x1de 1>;
531 reg = <0x1df 1>;
532 bits = <0 8>;
536 reg = <0x210 1>;
537 bits = <0 3>;
541 reg = <0x210 2>;
546 reg = <0x211 1>;
551 reg = <0x211 2>;
556 reg = <0x212 2>;
561 reg = <0x213 2>;
566 reg = <0x214 1>;
571 reg = <0x214 2>;
576 reg = <0x215 2>;
581 reg = <0x216 2>;
586 reg = <0x217 1>;
591 reg = <0x230 1>;
592 bits = <0 6>;
596 reg = <0x230 2>;
601 reg = <0x231 2>;
606 reg = <0x232 1>;
613 reg = <0x000e3000 0x1000>;
620 reg = <0x004a9000 0x1000>,
621 <0x004a8000 0x1000>;
656 reg = <0x004ab000 0x4>;
661 reg = <0x01000000 0x300000>;
664 gpio-ranges = <&tlmm 0 0 134>;
958 reg = <0x01800000 0x80000>;
965 <&mdss_dsi0_phy 0>;
974 reg = <0x01905000 0x20000>;
980 reg = <0x01937000 0x30000>;
985 reg = <0x01a00000 0x1000>,
986 <0x01ab0000 0x1040>;
1011 reg = <0x01a01000 0x89000>;
1015 interrupts = <0>;
1028 iommus = <&apps_iommu 0x15>;
1032 #size-cells = <0>;
1034 port@0 {
1035 reg = <0>;
1046 reg = <0x01a94000 0x300>;
1054 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1075 #size-cells = <0>;
1079 #size-cells = <0>;
1081 port@0 {
1082 reg = <0>;
1114 reg = <0x01a94a00 0xd4>,
1115 <0x01a94400 0x280>,
1116 <0x01a94b80 0x30>;
1122 #phy-cells = <0>;
1132 ranges = <0 0x01e20000 0x20000>;
1146 reg = <0x14000 0x1000>;
1153 reg = <0x15000 0x1000>;
1160 reg = <0x16000 0x1000>;
1167 ranges = <0 0x01f08000 0x10000>;
1178 iommu-ctx@0 {
1180 reg = <0 0x1000>;
1187 reg = <0x01c00000 0x20000>;
1205 iommus = <&gpu_iommu 0>;
1240 reg = <0x0200f000 0x001000>,
1241 <0x02400000 0x800000>,
1242 <0x02c00000 0x800000>,
1243 <0x03800000 0x200000>,
1244 <0x0200a000 0x002100>;
1252 qcom,ee = <0>;
1253 qcom,channel = <0>;
1255 #size-cells = <0>;
1262 reg = <0x04044000 0x19000>;
1265 qcom,ee = <0>;
1276 reg = <0x07824900 0x500>,
1277 <0x07824000 0x800>;
1287 pinctrl-0 = <&sdc1_default>;
1301 reg = <0x07864900 0x500>,
1302 <0x07864000 0x800>;
1312 pinctrl-0 = <&sdc2_default>;
1322 reg = <0x07884000 0x1f000>;
1330 qcom,ee = <0>;
1335 reg = <0x07ac4000 0x1d000>;
1343 qcom,ee = <0>;
1348 reg = <0x078af000 0x200>;
1353 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1355 pinctrl-0 = <&blsp1_uart1_default>;
1363 reg = <0x078b0000 0x200>;
1370 pinctrl-0 = <&blsp1_uart2_default>;
1378 reg = <0x078b6000 0x600>;
1385 pinctrl-0 = <&blsp1_i2c2_default>;
1389 #size-cells = <0>;
1395 reg = <0x078b7000 0x600>;
1402 pinctrl-0 = <&blsp1_i2c3_default>;
1406 #size-cells = <0>;
1412 reg = <0x078b7000 0x600>;
1419 pinctrl-0 = <&blsp1_spi3_default>;
1423 #size-cells = <0>;
1429 reg = <0x078b8000 0x500>;
1436 pinctrl-0 = <&blsp1_i2c4_default>;
1440 #size-cells = <0>;
1446 reg = <0x07af5000 0x600>;
1453 pinctrl-0 = <&blsp2_i2c1_default>;
1457 #size-cells = <0>;
1463 reg = <0x07af6000 0x600>;
1470 pinctrl-0 = <&blsp2_spi2_default>;
1474 #size-cells = <0>;
1480 reg = <0x078db000 0x200>,
1481 <0x078db200 0x200>;
1496 ahb-burst-config = <0>;
1505 reg = <0x0a204000 0x2000>,
1506 <0x0a202000 0x1000>,
1507 <0x0a21b000 0x3000>;
1513 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1523 qcom,smem-states = <&wcnss_smp2p_out 0>;
1526 pinctrl-0 = <&wcnss_pin_a>;
1572 reg = <0x0b000000 0x1000>,
1573 <0x0b002000 0x1000>;
1580 reg = <0x0b011000 0x1000>;
1584 #clock-cells = <0>;
1589 reg = <0x0b016000 0x40>;
1592 #clock-cells = <0>;
1618 reg = <0x0b017000 0x1000>;
1624 reg = <0x0b120000 0x1000>;
1630 reg = <0x0b121000 0x1000>,
1631 <0x0b122000 0x1000>;
1632 frame-number = <0>;
1638 reg = <0x0b123000 0x1000>;
1645 reg = <0x0b124000 0x1000>;
1652 reg = <0x0b125000 0x1000>;
1659 reg = <0x0b126000 0x1000>;
1666 reg = <0x0b127000 0x1000>;
1673 reg = <0x0b128000 0x1000>;
1693 thermal-sensors = <&tsens 0>;