Lines Matching full:gcc
11 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
14 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
246 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
247 <&gcc GCC_PCIE0_AHB_CLK>,
248 <&gcc GCC_PCIE0_PIPE_CLK>;
251 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
254 resets = <&gcc GCC_PCIE0_PHY_BCR>,
255 <&gcc GCC_PCIE0PHY_PHY_BCR>;
269 clocks = <&gcc GCC_PCIE2_AUX_CLK>,
270 <&gcc GCC_PCIE2_AHB_CLK>,
271 <&gcc GCC_PCIE2_PIPE_CLK>;
274 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
277 resets = <&gcc GCC_PCIE2_PHY_BCR>,
278 <&gcc GCC_PCIE2PHY_PHY_BCR>;
291 clocks = <&gcc GCC_PRNG_AHB_CLK>;
300 clocks = <&gcc GCC_MDIO_AHB_CLK>;
309 clocks = <&gcc GCC_PCIE3_AUX_CLK>,
310 <&gcc GCC_PCIE3_AHB_CLK>,
311 <&gcc GCC_PCIE3_PIPE_CLK>;
314 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
317 resets = <&gcc GCC_PCIE3_PHY_BCR>,
318 <&gcc GCC_PCIE3PHY_PHY_BCR>;
332 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
333 <&gcc GCC_PCIE1_AHB_CLK>,
334 <&gcc GCC_PCIE1_PIPE_CLK>;
337 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
340 resets = <&gcc GCC_PCIE1_PHY_BCR>,
341 <&gcc GCC_PCIE1PHY_PHY_BCR>;
355 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
356 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
387 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
388 <&gcc GCC_CRYPTO_AXI_CLK>,
389 <&gcc GCC_CRYPTO_CLK>;
423 gcc: clock-controller@1800000 { label
424 compatible = "qcom,ipq9574-gcc";
461 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
462 <&gcc GCC_SDCC1_APPS_CLK>,
464 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
475 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
485 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
486 <&gcc GCC_BLSP1_AHB_CLK>;
495 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
496 <&gcc GCC_BLSP1_AHB_CLK>;
505 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
506 <&gcc GCC_BLSP1_AHB_CLK>;
515 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
516 <&gcc GCC_BLSP1_AHB_CLK>;
525 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
526 <&gcc GCC_BLSP1_AHB_CLK>;
535 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
536 <&gcc GCC_BLSP1_AHB_CLK>;
547 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
548 <&gcc GCC_BLSP1_AHB_CLK>;
561 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
562 <&gcc GCC_BLSP1_AHB_CLK>;
564 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
577 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
578 <&gcc GCC_BLSP1_AHB_CLK>;
591 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
592 <&gcc GCC_BLSP1_AHB_CLK>;
594 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
607 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
608 <&gcc GCC_BLSP1_AHB_CLK>;
621 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
622 <&gcc GCC_BLSP1_AHB_CLK>;
624 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
638 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
639 <&gcc GCC_BLSP1_AHB_CLK>;
652 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
653 <&gcc GCC_BLSP1_AHB_CLK>;
655 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
668 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
669 <&gcc GCC_BLSP1_AHB_CLK>;
681 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
686 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
695 clocks = <&gcc GCC_USB0_AUX_CLK>,
697 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
698 <&gcc GCC_USB0_PIPE_CLK>;
704 resets = <&gcc GCC_USB0_PHY_BCR>,
705 <&gcc GCC_USB3PHY_0_PHY_BCR>;
722 clocks = <&gcc GCC_SNOC_USB_CLK>,
723 <&gcc GCC_USB0_MASTER_CLK>,
724 <&gcc GCC_ANOC_USB_AXI_CLK>,
725 <&gcc GCC_USB0_SLEEP_CLK>,
726 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
734 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
735 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
742 resets = <&gcc GCC_USB_BCR>;
748 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
806 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
919 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
920 <&gcc GCC_PCIE1_AXI_S_CLK>,
921 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
922 <&gcc GCC_PCIE1_RCHNG_CLK>,
923 <&gcc GCC_PCIE1_AHB_CLK>,
924 <&gcc GCC_PCIE1_AUX_CLK>;
932 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
933 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
934 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
935 <&gcc GCC_PCIE1_AXI_S_ARES>,
936 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
937 <&gcc GCC_PCIE1_AXI_M_ARES>,
938 <&gcc GCC_PCIE1_AUX_ARES>,
939 <&gcc GCC_PCIE1_AHB_ARES>;
951 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
952 <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
999 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
1000 <&gcc GCC_PCIE3_AXI_S_CLK>,
1001 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
1002 <&gcc GCC_PCIE3_RCHNG_CLK>,
1003 <&gcc GCC_PCIE3_AHB_CLK>,
1004 <&gcc GCC_PCIE3_AUX_CLK>;
1012 resets = <&gcc GCC_PCIE3_PIPE_ARES>,
1013 <&gcc GCC_PCIE3_CORE_STICKY_ARES>,
1014 <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
1015 <&gcc GCC_PCIE3_AXI_S_ARES>,
1016 <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
1017 <&gcc GCC_PCIE3_AXI_M_ARES>,
1018 <&gcc GCC_PCIE3_AUX_ARES>,
1019 <&gcc GCC_PCIE3_AHB_ARES>;
1031 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
1032 <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
1079 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
1080 <&gcc GCC_PCIE2_AXI_S_CLK>,
1081 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
1082 <&gcc GCC_PCIE2_RCHNG_CLK>,
1083 <&gcc GCC_PCIE2_AHB_CLK>,
1084 <&gcc GCC_PCIE2_AUX_CLK>;
1092 resets = <&gcc GCC_PCIE2_PIPE_ARES>,
1093 <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
1094 <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
1095 <&gcc GCC_PCIE2_AXI_S_ARES>,
1096 <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
1097 <&gcc GCC_PCIE2_AXI_M_ARES>,
1098 <&gcc GCC_PCIE2_AUX_ARES>,
1099 <&gcc GCC_PCIE2_AHB_ARES>;
1111 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
1112 <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>;
1158 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
1159 <&gcc GCC_PCIE0_AXI_S_CLK>,
1160 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
1161 <&gcc GCC_PCIE0_RCHNG_CLK>,
1162 <&gcc GCC_PCIE0_AHB_CLK>,
1163 <&gcc GCC_PCIE0_AUX_CLK>;
1171 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
1172 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
1173 <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>,
1174 <&gcc GCC_PCIE0_AXI_S_ARES>,
1175 <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>,
1176 <&gcc GCC_PCIE0_AXI_M_ARES>,
1177 <&gcc GCC_PCIE0_AUX_ARES>,
1178 <&gcc GCC_PCIE0_AHB_ARES>;
1190 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
1191 <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;