Lines Matching +full:tcsr +full:- +full:reg
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
11 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
12 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&intc>;
20 sleep_clk: sleep-clk {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
25 xo_board: xo-board-clk {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a55";
38 reg = <0x0>;
39 enable-method = "psci";
40 next-level-cache = <&l2_0>;
41 l2_0: l2-cache {
43 cache-level = <2>;
44 cache-unified;
45 next-level-cache = <&l3_0>;
47 l3_0: l3-cache {
49 cache-level = <3>;
50 cache-unified;
57 compatible = "arm,cortex-a55";
58 enable-method = "psci";
59 reg = <0x100>;
60 next-level-cache = <&l2_100>;
62 l2_100: l2-cache {
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&l3_0>;
72 compatible = "arm,cortex-a55";
73 enable-method = "psci";
74 reg = <0x200>;
75 next-level-cache = <&l2_200>;
77 l2_200: l2-cache {
79 cache-level = <2>;
80 cache-unified;
81 next-level-cache = <&l3_0>;
87 compatible = "arm,cortex-a55";
88 enable-method = "psci";
89 reg = <0x300>;
90 next-level-cache = <&l2_300>;
92 l2_300: l2-cache {
94 cache-level = <2>;
95 cache-unified;
96 next-level-cache = <&l3_0>;
103 compatible = "qcom,scm-ipq5424", "qcom,scm";
104 qcom,dload-mode = <&tcsr 0x25100>;
111 reg = <0x0 0x80000000 0x0 0x0>;
114 pmu-a55 {
115 compatible = "arm,cortex-a55-pmu";
119 pmu-dsu {
120 compatible = "arm,dsu-pmu";
126 compatible = "arm,psci-1.0";
130 reserved-memory {
131 #address-cells = <2>;
132 #size-cells = <2>;
136 reg = <0x0 0x8a600000 0x0 0x200000>;
137 no-map;
142 reg = <0x0 0x8a800000 0x0 0x32000>;
143 no-map;
150 compatible = "simple-bus";
151 #address-cells = <2>;
152 #size-cells = <2>;
156 compatible = "qcom,ipq5424-trng", "qcom,trng";
157 reg = <0 0x004c3000 0 0x1000>;
159 clock-names = "core";
162 system-cache-controller@800000 {
163 compatible = "qcom,ipq5424-llcc";
164 reg = <0 0x00800000 0 0x200000>;
165 reg-names = "llcc0_base";
170 compatible = "qcom,ipq5424-tlmm";
171 reg = <0 0x01000000 0 0x300000>;
173 gpio-controller;
174 #gpio-cells = <2>;
175 gpio-ranges = <&tlmm 0 0 50>;
176 interrupt-controller;
177 #interrupt-cells = <2>;
179 uart1_pins: uart1-state {
182 drive-strength = <8>;
183 bias-pull-up;
187 gcc: clock-controller@1800000 {
188 compatible = "qcom,ipq5424-gcc";
189 reg = <0 0x01800000 0 0x40000>;
197 #clock-cells = <1>;
198 #reset-cells = <1>;
199 #interconnect-cells = <1>;
203 compatible = "qcom,tcsr-mutex";
204 reg = <0 0x01905000 0 0x20000>;
205 #hwlock-cells = <1>;
208 tcsr: syscon@1937000 { label
209 compatible = "qcom,tcsr-ipq5424", "syscon";
210 reg = <0 0x01937000 0 0x2a000>;
214 compatible = "qcom,geni-se-qup";
215 reg = <0 0x01ac0000 0 0x2000>;
219 clock-names = "m-ahb", "s-ahb";
220 #address-cells = <2>;
221 #size-cells = <2>;
224 compatible = "qcom,geni-debug-uart";
225 reg = <0 0x01a84000 0 0x4000>;
227 clock-names = "se";
232 compatible = "qcom,geni-spi";
233 reg = <0 0x01a90000 0 0x4000>;
235 clock-names = "se";
237 #address-cells = <1>;
238 #size-cells = <0>;
243 compatible = "qcom,geni-spi";
244 reg = <0 0x01a94000 0 0x4000>;
246 clock-names = "se";
248 #address-cells = <1>;
249 #size-cells = <0>;
255 compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
256 reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
257 reg-names = "hc", "cqhci";
261 interrupt-names = "hc_irq", "pwr_irq";
266 clock-names = "iface", "core", "xo";
271 intc: interrupt-controller@f200000 {
272 compatible = "arm,gic-v3";
273 reg = <0 0xf200000 0 0x10000>, /* GICD */
275 #interrupt-cells = <0x3>;
276 interrupt-controller;
277 #redistributor-regions = <1>;
278 redistributor-stride = <0x0 0x20000>;
280 mbi-ranges = <672 128>;
281 msi-controller;
285 compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
286 reg = <0 0x0f410000 0 0x1000>;
292 compatible = "qcom,ipq5424-qusb2-phy";
293 reg = <0 0x00071000 0 0x180>;
294 #phy-cells = <0>;
298 clock-names = "cfg_ahb", "ref";
305 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
306 reg = <0 0x01ef8800 0 0x400>;
307 #address-cells = <2>;
308 #size-cells = <2>;
317 clock-names = "core",
323 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
325 assigned-clock-rates = <200000000>,
328 interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
332 interrupt-names = "pwr_event",
338 qcom,select-utmi-as-pipe-clk;
343 reg = <0 0x01e00000 0 0xe000>;
345 clock-names = "ref";
348 phy-names = "usb2-phy";
349 tx-fifo-resize;
350 snps,is-utmi-l1-suspend;
351 snps,hird-threshold = /bits/ 8 <0x0>;
358 compatible = "qcom,ipq5424-qusb2-phy";
359 reg = <0 0x0007b000 0 0x180>;
360 #phy-cells = <0>;
364 clock-names = "cfg_ahb", "ref";
371 compatible = "qcom,ipq5424-qmp-usb3-phy";
372 reg = <0 0x0007d000 0 0xa00>;
373 #phy-cells = <0>;
379 clock-names = "aux",
386 reset-names = "phy",
389 #clock-cells = <0>;
390 clock-output-names = "usb0_pipe_clk";
396 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
397 reg = <0 0x08af8800 0 0x400>;
399 #address-cells = <2>;
400 #size-cells = <2>;
409 clock-names = "core",
415 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
417 assigned-clock-rates = <200000000>,
420 interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
424 interrupt-names = "pwr_event",
434 reg = <0 0x08a00000 0 0xcd00>;
436 clock-names = "ref";
439 phy-names = "usb2-phy", "usb3-phy";
440 tx-fifo-resize;
441 snps,is-utmi-l1-suspend;
442 snps,hird-threshold = /bits/ 8 <0x0>;
445 snps,dis-u1-entry-quirk;
446 snps,dis-u2-entry-quirk;
451 compatible = "arm,armv7-timer-mem";
452 reg = <0 0xf420000 0 0x1000>;
454 #address-cells = <1>;
455 #size-cells = <1>;
458 reg = <0xf421000 0x1000>,
462 frame-number = <0>;
466 reg = <0xf423000 0x1000>;
468 frame-number = <1>;
473 reg = <0xf425000 0x1000>,
476 frame-number = <2>;
481 reg = <0xf427000 0x1000>;
483 frame-number = <3>;
488 reg = <0xf429000 0x1000>;
490 frame-number = <4>;
495 reg = <0xf42b000 0x1000>;
497 frame-number = <5>;
502 reg = <0xf42d000 0x1000>;
504 frame-number = <6>;
512 compatible = "arm,armv8-timer";