Lines Matching full:bpmp
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
124 resets = <&bpmp TEGRA234_RESET_GPCDMA>;
167 clocks = <&bpmp TEGRA234_CLK_APE>,
168 <&bpmp TEGRA234_CLK_APB2APE>;
170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
180 clocks = <&bpmp TEGRA234_CLK_AHUB>;
182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
195 clocks = <&bpmp TEGRA234_CLK_I2S1>,
196 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
198 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
231 clocks = <&bpmp TEGRA234_CLK_I2S2>,
232 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
234 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
235 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
267 clocks = <&bpmp TEGRA234_CLK_I2S3>,
268 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
270 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
271 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
303 clocks = <&bpmp TEGRA234_CLK_I2S4>,
304 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
306 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
307 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
339 clocks = <&bpmp TEGRA234_CLK_I2S5>,
340 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
342 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
343 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
375 clocks = <&bpmp TEGRA234_CLK_I2S6>,
376 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
378 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
940 clocks = <&bpmp TEGRA234_CLK_DMIC1>;
942 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
943 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
974 clocks = <&bpmp TEGRA234_CLK_DMIC2>;
976 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
977 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1008 clocks = <&bpmp TEGRA234_CLK_DMIC3>;
1010 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
1011 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1042 clocks = <&bpmp TEGRA234_CLK_DMIC4>;
1044 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
1045 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1076 clocks = <&bpmp TEGRA234_CLK_DSPK1>;
1078 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
1079 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1110 clocks = <&bpmp TEGRA234_CLK_DSPK2>;
1112 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
1113 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
2674 clocks = <&bpmp TEGRA234_CLK_AHUB>;
2689 clocks = <&bpmp TEGRA234_CLK_APE>;
2750 clocks = <&bpmp TEGRA234_CLK_EMC>;
2756 nvidia,bpmp = <&bpmp>;
2764 clocks = <&bpmp TEGRA234_CLK_UARTA>;
2765 resets = <&bpmp TEGRA234_RESET_UARTA>;
2775 clocks = <&bpmp TEGRA234_CLK_UARTE>;
2776 resets = <&bpmp TEGRA234_RESET_UARTE>;
2790 clocks = <&bpmp TEGRA234_CLK_I2C1>,
2791 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2792 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
2793 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2795 resets = <&bpmp TEGRA234_RESET_I2C1>;
2809 clocks = <&bpmp TEGRA234_CLK_I2C3>,
2810 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2811 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
2812 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2814 resets = <&bpmp TEGRA234_RESET_I2C3>;
2828 clocks = <&bpmp TEGRA234_CLK_I2C4>,
2829 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2830 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
2831 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2833 resets = <&bpmp TEGRA234_RESET_I2C4>;
2847 clocks = <&bpmp TEGRA234_CLK_I2C6>,
2848 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2849 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
2850 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2852 resets = <&bpmp TEGRA234_RESET_I2C6>;
2866 clocks = <&bpmp TEGRA234_CLK_I2C7>,
2867 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2868 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
2869 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2871 resets = <&bpmp TEGRA234_RESET_I2C7>;
2892 clocks = <&bpmp TEGRA234_CLK_I2C9>,
2893 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2894 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
2895 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2897 resets = <&bpmp TEGRA234_RESET_I2C9>;
2909 clocks = <&bpmp TEGRA234_CLK_SPI1>;
2910 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
2911 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2914 resets = <&bpmp TEGRA234_RESET_SPI1>;
2928 clocks = <&bpmp TEGRA234_CLK_SPI3>;
2931 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
2932 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2933 resets = <&bpmp TEGRA234_RESET_SPI3>;
2947 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
2948 <&bpmp TEGRA234_CLK_QSPI0_PM>;
2950 resets = <&bpmp TEGRA234_RESET_QSPI0>;
2957 clocks = <&bpmp TEGRA234_CLK_PWM1>;
2958 resets = <&bpmp TEGRA234_RESET_PWM1>;
2967 clocks = <&bpmp TEGRA234_CLK_PWM2>;
2968 resets = <&bpmp TEGRA234_RESET_PWM2>;
2977 clocks = <&bpmp TEGRA234_CLK_PWM3>;
2978 resets = <&bpmp TEGRA234_RESET_PWM3>;
2987 clocks = <&bpmp TEGRA234_CLK_PWM5>;
2988 resets = <&bpmp TEGRA234_RESET_PWM5>;
2997 clocks = <&bpmp TEGRA234_CLK_PWM6>;
2998 resets = <&bpmp TEGRA234_RESET_PWM6>;
3007 clocks = <&bpmp TEGRA234_CLK_PWM7>;
3008 resets = <&bpmp TEGRA234_RESET_PWM7>;
3017 clocks = <&bpmp TEGRA234_CLK_PWM8>;
3018 resets = <&bpmp TEGRA234_RESET_PWM8>;
3030 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
3031 <&bpmp TEGRA234_CLK_QSPI1_PM>;
3033 resets = <&bpmp TEGRA234_RESET_QSPI1>;
3041 clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
3042 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
3044 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
3045 <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
3046 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
3047 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
3048 resets = <&bpmp TEGRA234_RESET_SDMMC1>;
3076 clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
3077 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
3079 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
3080 <&bpmp TEGRA234_CLK_PLLC4>;
3081 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
3082 resets = <&bpmp TEGRA234_RESET_SDMMC4>;
3105 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
3106 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
3108 resets = <&bpmp TEGRA234_RESET_HDA>,
3109 <&bpmp TEGRA234_RESET_HDACODEC>;
3111 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
3126 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
3133 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
3233 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
3234 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
3235 <&bpmp TEGRA234_CLK_XUSB_SS>,
3236 <&bpmp TEGRA234_CLK_XUSB_FS>;
3242 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
3243 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
3260 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
3261 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
3262 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
3263 <&bpmp TEGRA234_CLK_XUSB_SS>,
3264 <&bpmp TEGRA234_CLK_CLK_M>,
3265 <&bpmp TEGRA234_CLK_XUSB_FS>,
3266 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
3267 <&bpmp TEGRA234_CLK_CLK_M>,
3268 <&bpmp TEGRA234_CLK_PLLE>;
3278 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
3279 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
3290 clocks = <&bpmp TEGRA234_CLK_FUSE>;
3520 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
3521 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
3522 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
3523 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
3524 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
3525 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
3526 <&bpmp TEGRA234_CLK_MGBE0_TX>,
3527 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
3528 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
3529 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
3530 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
3531 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
3535 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
3536 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
3542 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
3562 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
3563 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
3564 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
3565 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
3566 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
3567 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
3568 <&bpmp TEGRA234_CLK_MGBE1_TX>,
3569 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
3570 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
3571 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
3572 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
3573 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
3577 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
3578 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
3584 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
3604 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
3605 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
3606 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
3607 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
3608 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
3609 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
3610 <&bpmp TEGRA234_CLK_MGBE2_TX>,
3611 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
3612 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
3613 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
3614 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
3615 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
3619 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
3620 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
3626 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
3646 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
3647 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
3648 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
3649 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
3650 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
3651 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
3652 <&bpmp TEGRA234_CLK_MGBE3_TX>,
3653 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
3654 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
3655 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
3656 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
3657 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
3661 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
3662 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
3668 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
3860 clocks = <&bpmp TEGRA234_CLK_I2C2>,
3861 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3863 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
3864 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3865 resets = <&bpmp TEGRA234_RESET_I2C2>;
3879 clocks = <&bpmp TEGRA234_CLK_I2C8>,
3880 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3882 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
3883 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3884 resets = <&bpmp TEGRA234_RESET_I2C8>;
3896 clocks = <&bpmp TEGRA234_CLK_SPI2>;
3899 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
3900 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3901 resets = <&bpmp TEGRA234_RESET_SPI2>;
3914 clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
3943 clocks = <&bpmp TEGRA234_CLK_PWM4>;
3944 resets = <&bpmp TEGRA234_RESET_PWM4>;
3990 bpmp-fabric@d600000 {
3991 compatible = "nvidia,tegra234-bpmp-fabric";
4007 nvidia,bpmp = <&bpmp>;
4331 clocks = <&bpmp TEGRA234_CLK_HOST1X>;
4365 clocks = <&bpmp TEGRA234_CLK_VIC>;
4367 resets = <&bpmp TEGRA234_RESET_VIC>;
4370 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
4381 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
4382 <&bpmp TEGRA234_CLK_FUSE>,
4383 <&bpmp TEGRA234_CLK_TSEC_PKA>;
4385 resets = <&bpmp TEGRA234_RESET_NVDEC>;
4387 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
4417 clocks = <&bpmp TEGRA234_CLK_SE>;
4425 clocks = <&bpmp TEGRA234_CLK_SE>;
4433 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
4448 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
4451 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
4452 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
4463 nvidia,bpmp = <&bpmp 8>;
4487 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
4502 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
4505 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
4506 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
4517 nvidia,bpmp = <&bpmp 9>;
4541 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
4556 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
4559 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
4560 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
4571 nvidia,bpmp = <&bpmp 10>;
4595 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
4604 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
4607 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
4608 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
4614 nvidia,bpmp = <&bpmp 10>;
4633 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4648 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
4651 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
4652 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
4663 nvidia,bpmp = <&bpmp 1>;
4687 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4702 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
4705 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
4706 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
4717 nvidia,bpmp = <&bpmp 2>;
4741 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4756 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
4759 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
4760 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
4771 nvidia,bpmp = <&bpmp 3>;
4795 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
4810 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
4813 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
4814 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
4825 nvidia,bpmp = <&bpmp 4>;
4849 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
4856 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
4858 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
4859 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
4864 nvidia,bpmp = <&bpmp 4>;
4880 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
4895 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
4898 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
4899 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
4910 nvidia,bpmp = <&bpmp 0>;
4934 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
4949 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
4952 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
4953 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
4964 nvidia,bpmp = <&bpmp 5>;
4988 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
4997 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
5000 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
5001 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
5007 nvidia,bpmp = <&bpmp 5>;
5026 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
5041 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
5044 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
5045 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
5056 nvidia,bpmp = <&bpmp 6>;
5080 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
5089 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
5092 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
5093 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
5099 nvidia,bpmp = <&bpmp 6>;
5118 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
5133 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
5136 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
5137 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
5148 nvidia,bpmp = <&bpmp 7>;
5172 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
5181 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
5184 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
5185 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
5191 nvidia,bpmp = <&bpmp 7>;
5221 label = "cpu-bpmp-tx";
5227 label = "cpu-bpmp-rx";
5232 bpmp: bpmp { label
5233 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
5248 compatible = "nvidia,tegra186-bpmp-i2c";
5249 nvidia,bpmp-bus-id = <5>;
5255 compatible = "nvidia,tegra186-bpmp-thermal";
5737 clocks = <&bpmp TEGRA234_CLK_PLLA>,
5738 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
5740 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
5741 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
5742 <&bpmp TEGRA234_CLK_AUD_MCLK>;
5744 <&bpmp TEGRA234_CLK_PLLA>,
5745 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
5750 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
5755 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
5760 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
5765 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
5770 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
5775 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
5780 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
5785 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
5790 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;