Lines Matching +full:1 +full:c60000

69 		snps,write-requests = <1>;
113 		#dma-cells = <1>;
127 		#address-cells = <1>;
128 		#size-cells = <1>;
140 			#address-cells = <1>;
141 			#size-cells = <1>;
401 				#address-cells = <1>;
402 				#size-cells = <1>;
447 				dmas = <&adma 1>, <&adma 1>,
503 				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
534 			#dma-cells = <1>;
567 		#interconnect-cells = <1>;
579 		emc: external-memory-controller@2c60000 {
596 			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
670 		#address-cells = <1>;
685 		#address-cells = <1>;
701 		#address-cells = <1>;
709 		pinctrl-1 = <&state_dpaux1_off>;
720 		#address-cells = <1>;
734 		#address-cells = <1>;
742 		pinctrl-1 = <&state_dpaux_off>;
752 		#address-cells = <1>;
767 		#address-cells = <1>;
861 		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
863 		pinctrl-1 = <&sdmmc1_1v8>;
866 		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
867 		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
891 		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
893 		pinctrl-1 = <&sdmmc2_1v8>;
896 		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
897 		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
916 		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
918 		pinctrl-1 = <&sdmmc3_1v8>;
919 		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
920 		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
923 		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
924 		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
948 		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
949 		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
955 		mmc-hs400-1_8v;
1032 					usb2-1 {
1066 					usb3-1 {
1084 			usb2-1 {
1100 			usb3-1 {
1136 		#address-cells = <1>;
1207 		#address-cells = <1>;
1222 		#address-cells = <1>;
1300 		sdmmc1_1v8: sdmmc1-1v8 {
1310 		sdmmc2_1v8: sdmmc2-1v8 {
1320 		sdmmc3_1v8: sdmmc3-1v8 {
1351 		#interrupt-cells = <1>;
1360 			 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1386 		pci@1,0 {
1409 			nvidia,num-lanes = <1>;
1422 			nvidia,num-lanes = <1>;
1495 		#global-interrupts = <1>;
1496 		#iommu-cells = <1>;
1514 		#address-cells = <1>;
1515 		#size-cells = <1>;
1525 		iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
1526 			    <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>,
1527 			    <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>,
1528 			    <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>,
1529 			    <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>,
1530 			    <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>,
1531 			    <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>,
1532 			    <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
1563 				#address-cells = <1>;
1588 			#address-cells = <1>;
1589 			#size-cells = <1>;
1605 				interconnect-names = "dma-mem", "read-1";
1624 				interconnect-names = "dma-mem", "read-1";
1628 				nvidia,head = <1>;
1643 				interconnect-names = "dma-mem", "read-1";
1724 			interconnect-names = "dma-mem", "read-1", "write";
1758 			pinctrl-1 = <&state_dpaux_i2c>;
1782 			pinctrl-1 = <&state_dpaux1_i2c>;
1788 			nvidia,interface = <1>;
1820 				#address-cells = <1>;
1884 		interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1890 		#address-cells = <1>;
1891 		#size-cells = <1>;
1919 		#clock-cells = <1>;
1920 		#reset-cells = <1>;
1921 		#power-domain-cells = <1>;
1926 			#address-cells = <1>;
1933 			#thermal-sensor-cells = <1>;
1938 		#address-cells = <1>;
1954 		denver_1: cpu@1 {