Lines Matching +full:0 +full:x17000000
24 #size-cells = <0>;
26 cluster0_opp: opp-table-0 {
128 cpu0: cpu@0 {
131 reg = <0x0>;
135 i-cache-size = <0x8000>;
138 d-cache-size = <0x8000>;
151 reg = <0x1>;
155 i-cache-size = <0x8000>;
158 d-cache-size = <0x8000>;
171 reg = <0x2>;
175 i-cache-size = <0x8000>;
178 d-cache-size = <0x8000>;
191 reg = <0x3>;
195 i-cache-size = <0x8000>;
198 d-cache-size = <0x8000>;
214 arm,psci-suspend-param = <0x00010001>;
223 arm,psci-suspend-param = <0x01010001>;
232 arm,psci-suspend-param = <0x01010004>;
242 cache-size = <0x80000>;
251 #clock-cells = <0>;
272 reg = <0 0x0c000000 0 0x10000>, /* GICD */
273 <0 0x0c080000 0 0x80000>, /* GICR */
274 <0 0x0c400000 0 0x2000>, /* GICC */
275 <0 0x0c410000 0 0x1000>, /* GICH */
276 <0 0x0c420000 0 0x2000>; /* GICV */
283 reg = <0 0x10000000 0 0x1000>;
289 reg = <0 0x10001000 0 0x1000>;
295 reg = <0 0x10003000 0 0x1000>;
301 reg = <0 0x10005000 0 0x1000>;
306 reg = <0 0x10006000 0 0x1000>;
312 #size-cells = <0>;
323 clock-names = "mm", "mm-0", "mm-1",
325 #power-domain-cells = <0>;
329 #size-cells = <0>;
339 clock-names = "cam-0", "cam-1",
342 #power-domain-cells = <0>;
349 #power-domain-cells = <0>;
355 #power-domain-cells = <0>;
368 clock-names = "apu", "apu-0",
372 #power-domain-cells = <0>;
383 #power-domain-cells = <0>;
391 #power-domain-cells = <0>;
401 #power-domain-cells = <0>;
410 #power-domain-cells = <0>;
418 reg = <0 0x10007000 0 0x100>;
424 reg = <0 0x1000b000 0 0x1000>;
435 reg = <0 0x1000c000 0 0x1000>;
441 reg = <0 0x1000d000 0 0x1000>;
454 reg = <0 0x10010000 0 0x1000>;
464 reg = <0 0x10200000 0 0x2000>;
473 reg = <0 0x10200a80 0 0x20>;
478 reg = <0 0x10205000 0 0x1000>;
486 reg = <0 0x1020e000 0 0x1000>;
492 reg = <0 0x1020f000 0 0x100>;
499 reg = <0 0x11000280 0 0x80>,
500 <0 0x11000300 0 0x80>,
501 <0 0x11000380 0 0x80>,
502 <0 0x11000400 0 0x80>,
503 <0 0x11000580 0 0x80>,
504 <0 0x11000600 0 0x80>;
519 reg = <0 0x11002000 0 0x1000>;
523 dmas = <&apdma 0>, <&apdma 1>;
530 reg = <0 0x11003000 0 0x1000>;
541 reg = <0 0x11004000 0 0x1000>;
552 reg = <0 0x11006000 0 0x1000>;
565 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
571 #size-cells = <0>;
577 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
583 #size-cells = <0>;
589 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
595 #size-cells = <0>;
601 reg = <0 0x1100a000 0 0x100>;
603 #size-cells = <0>;
614 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
620 #size-cells = <0>;
626 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
643 reg = <0 0x11200000 0 0x1000>;
659 reg = <0 0x11230000 0 0x1000>,
660 <0 0x11cd0000 0 0x1000>;
671 reg = <0 0x11240000 0 0x1000>,
672 <0 0x11c90000 0 0x1000>;
683 reg = <0 0x11250000 0 0x1000>,
684 <0 0x11c60000 0 0x1000>;
698 reg = <0 0x112a0000 0 0x1000>;
712 ranges = <0 0 0x11cc0000 0x9000>;
714 u2port0: usb-phy@0 {
715 reg = <0x0 0x400>;
723 reg = <0x1000 0x400>;
733 reg = <0 0x14000000 0 0x1000>;
739 reg = <0 0x14002000 0 0x1000>;
751 reg = <0 0x14003000 0 0x1000>;
757 mediatek,larb-id = <0>;
762 reg = <0 0x15000000 0 0x1000>;
769 reg = <0 0x15001000 0 0x1000>;
780 reg = <0 0x16000000 0 0x1000>;
787 reg = <0 0x16010000 0 0x1000>;
798 reg = <0 0x17000000 0 0x1000>;
805 reg = <0 0x17010000 0 0x1000>;
815 reg = <0 0x19020000 0 0x1000>;
821 reg = <0 0x11220000 0 0x1000>;
822 #sound-dai-cells = <0>;
869 #clock-cells = <0>;
874 reg = <0 0x10017000 0 0x100>;