Lines Matching full:vppsys0
588 <&vppsys0 CLK_VPP0_SMI_COMMON>,
589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
593 <&vppsys0 CLK_VPP0_GALS_INFRA>,
594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
597 <&vppsys0 CLK_VPP0_SMI_REORDER>,
598 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
602 <&vppsys0 CLK_VPP0_SMI_RSI>,
603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
2024 vppsys0: syscon@14000000 { label
2025 compatible = "mediatek,mt8195-vppsys0", "syscon";
2040 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
2053 clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
2060 clocks = <&vppsys0 CLK_VPP0_STITCH>;
2067 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
2075 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
2085 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
2092 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
2100 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
2109 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
2118 clocks = <&vppsys0 CLK_VPP0_PADDING>;
2126 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
2135 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
2146 clocks = <&vppsys0 CLK_VPP0_MUTEX>;
2153 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2154 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2155 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2164 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2165 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2166 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2175 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2176 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2177 <&vppsys0 CLK_VPP0_SMI_RSI>,
2178 <&vppsys0 CLK_VPP0_SMI_RSI>;
2188 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2189 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2202 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2244 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2272 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2284 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2595 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2714 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2921 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2955 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
3132 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3276 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
3287 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3288 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
3357 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;