Lines Matching full:vdosys1
703 <&vdosys1 CLK_VDO1_SMI_LARB2>,
704 <&vdosys1 CLK_VDO1_SMI_LARB3>,
705 <&vdosys1 CLK_VDO1_GALS>;
706 clock-names = "vdosys1", "vdosys1-0",
707 "vdosys1-1", "vdosys1-2";
3293 vdosys1: syscon@1c100000 { label
3294 compatible = "mediatek,mt8195-vdosys1", "syscon";
3333 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3343 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
3344 <&vdosys1 CLK_VDO1_SMI_LARB2>,
3345 <&vdosys1 CLK_VDO1_GALS>;
3355 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
3356 <&vdosys1 CLK_VDO1_GALS>,
3366 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
3377 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
3388 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
3399 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
3410 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
3421 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
3432 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
3443 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
3454 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
3455 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
3460 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
3467 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
3468 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
3473 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
3480 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
3481 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
3486 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
3493 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
3494 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
3499 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3506 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3507 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3512 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3520 clocks = <&vdosys1 CLK_VDO1_DPINTF>,
3521 <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3545 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
3546 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
3547 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
3548 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
3549 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
3550 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
3551 <&vdosys1 CLK_VDO1_26M_SLOW>,
3552 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
3553 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
3554 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
3555 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
3556 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
3566 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
3567 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
3568 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
3569 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
3570 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;