Lines Matching +full:1 +full:e40000
50 #address-cells = <1>;
134 performance-domains = <&performance 1>;
153 performance-domains = <&performance 1>;
172 performance-domains = <&performance 1>;
191 performance-domains = <&performance 1>;
335 clock-mult = <1>;
356 #performance-domain-cells = <1>;
465 #redistributor-regions = <1>;
477 ppi_cluster1: interrupt-partition-1 {
486 #clock-cells = <1>;
492 #clock-cells = <1>;
493 #reset-cells = <1>;
499 #clock-cells = <1>;
530 #address-cells = <1>;
532 #power-domain-cells = <1>;
537 #address-cells = <1>;
539 #power-domain-cells = <1>;
547 #address-cells = <1>;
549 #power-domain-cells = <1>;
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
616 #address-cells = <1>;
618 #power-domain-cells = <1>;
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
649 #address-cells = <1>;
651 #power-domain-cells = <1>;
659 "vppsys1-1";
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
707 "vdosys1-1", "vdosys1-2";
709 #address-cells = <1>;
711 #power-domain-cells = <1>;
737 clock-names = "img-0", "img-1";
739 #address-cells = <1>;
741 #power-domain-cells = <1>;
753 clock-names = "ipe", "ipe-0", "ipe-1";
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
769 #address-cells = <1>;
771 #power-domain-cells = <1>;
833 #address-cells = <1>;
836 #power-domain-cells = <1>;
857 #reset-cells = <1>;
863 #clock-cells = <1>;
909 #iommu-cells = <1>;
941 #clock-cells = <1>;
1096 #io-channel-cells = <1>;
1103 #clock-cells = <1>;
1109 #address-cells = <1>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1169 #address-cells = <1>;
1183 #address-cells = <1>;
1197 #address-cells = <1>;
1211 #address-cells = <1>;
1225 #address-cells = <1>;
1293 #address-cells = <1>;
1436 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1437 #thermal-sensor-cells = <1>;
1565 #interrupt-cells = <1>;
1567 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1568 <0 0 0 2 &pcie_intc0 1>,
1576 #interrupt-cells = <1>;
1614 #interrupt-cells = <1>;
1616 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1617 <0 0 0 2 &pcie_intc1 1>,
1625 #interrupt-cells = <1>;
1638 #address-cells = <1>;
1646 #address-cells = <1>;
1647 #size-cells = <1>;
1648 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1660 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1672 u2_intr_p0: usb2-intr-p0@188,1 {
1680 u2_intr_p2: usb2-intr-p2@189,1 {
1688 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1696 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1704 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1716 dp_calibration: dp-data@1ac {
1719 lvts_efuse_data1: lvts1-calib@1bc {
1722 lvts_efuse_data2: lvts2-calib@1d0 {
1735 #address-cells = <1>;
1736 #size-cells = <1>;
1744 #phy-cells = <1>;
1750 #address-cells = <1>;
1751 #size-cells = <1>;
1759 #phy-cells = <1>;
1789 clock-div = <1>;
1793 #address-cells = <1>;
1804 clock-div = <1>;
1808 #address-cells = <1>;
1819 clock-div = <1>;
1823 #address-cells = <1>;
1831 #clock-cells = <1>;
1840 clock-div = <1>;
1844 #address-cells = <1>;
1855 clock-div = <1>;
1859 #address-cells = <1>;
1870 clock-div = <1>;
1874 #address-cells = <1>;
1885 clock-div = <1>;
1889 #address-cells = <1>;
1900 clock-div = <1>;
1904 #address-cells = <1>;
1912 #clock-cells = <1>;
1917 #address-cells = <1>;
1918 #size-cells = <1>;
1928 #phy-cells = <1>;
1940 #phy-cells = <1>;
1944 u3phy0: t-phy@11e40000 {
1946 #address-cells = <1>;
1947 #size-cells = <1>;
1956 #phy-cells = <1>;
1968 #phy-cells = <1>;
2021 #clock-cells = <1>;
2027 #clock-cells = <1>;
2046 #dma-cells = <1>;
2138 #dma-cells = <1>;
2204 #iommu-cells = <1>;
2211 #clock-cells = <1>;
2217 #clock-cells = <1>;
2223 #clock-cells = <1>;
2252 #clock-cells = <1>;
2315 #dma-cells = <1>;
2327 #dma-cells = <1>;
2339 #dma-cells = <1>;
2545 #dma-cells = <1>;
2557 #dma-cells = <1>;
2569 #dma-cells = <1>;
2575 #clock-cells = <1>;
2615 #clock-cells = <1>;
2632 #clock-cells = <1>;
2638 #clock-cells = <1>;
2655 #clock-cells = <1>;
2672 #clock-cells = <1>;
2767 #clock-cells = <1>;
2773 #clock-cells = <1>;
2779 #clock-cells = <1>;
2785 #clock-cells = <1>;
2791 #clock-cells = <1>;
2821 #clock-cells = <1>;
2930 #clock-cells = <1>;
2947 #clock-cells = <1>;
2964 #clock-cells = <1>;
2970 #clock-cells = <1>;
2973 vencsys: clock-controller@1a000000 {
2976 #clock-cells = <1>;
2979 larb19: larb@1a010000 {
2990 venc: video-codec@1a020000 {
3026 jpgdec@1a040000 {
3041 jpgdec@1a050000 {
3056 jpgdec@1b040000 {
3072 vencsys_core1: clock-controller@1b000000 {
3075 #clock-cells = <1>;
3078 vdosys0: syscon@1c01a000 {
3082 #clock-cells = <1>;
3098 jpgenc@1a030000 {
3111 jpgenc@1b030000 {
3125 larb20: larb@1b010000 {
3137 ovl0: ovl@1c000000 {
3147 rdma0: rdma@1c002000 {
3157 color0: color@1c003000 {
3166 ccorr0: ccorr@1c004000 {
3175 aal0: aal@1c005000 {
3184 gamma0: gamma@1c006000 {
3193 dither0: dither@1c007000 {
3202 dsi0: dsi@1c008000 {
3216 dsc0: dsc@1c009000 {
3225 dsi1: dsi@1c012000 {
3239 merge0: merge@1c014000 {
3248 dp_intf0: dp-intf@1c015000 {
3259 mutex: mutex@1c016000 {
3269 larb0: larb@1c018000 {
3281 larb1: larb@1c019000 {
3284 mediatek,larb-id = <1>;
3293 vdosys1: syscon@1c100000 {
3296 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
3298 #clock-cells = <1>;
3299 #reset-cells = <1>;
3302 smi_common_vdo: smi@1c01b000 {
3314 iommu_vdo: iommu@1c01f000 {
3322 #iommu-cells = <1>;
3328 mutex1: mutex@1c101000 {
3338 larb2: larb@1c102000 {
3350 larb3: larb@1c103000 {
3362 vdo1_rdma0: dma-controller@1c104000 {
3370 #dma-cells = <1>;
3373 vdo1_rdma1: dma-controller@1c105000 {
3381 #dma-cells = <1>;
3384 vdo1_rdma2: dma-controller@1c106000 {
3392 #dma-cells = <1>;
3395 vdo1_rdma3: dma-controller@1c107000 {
3403 #dma-cells = <1>;
3406 vdo1_rdma4: dma-controller@1c108000 {
3414 #dma-cells = <1>;
3417 vdo1_rdma5: dma-controller@1c109000 {
3425 #dma-cells = <1>;
3428 vdo1_rdma6: dma-controller@1c10a000 {
3436 #dma-cells = <1>;
3439 vdo1_rdma7: dma-controller@1c10b000 {
3447 #dma-cells = <1>;
3450 merge1: vpp-merge@1c10c000 {
3463 merge2: vpp-merge@1c10d000 {
3476 merge3: vpp-merge@1c10e000 {
3489 merge4: vpp-merge@1c10f000 {
3502 merge5: vpp-merge@1c110000 {
3515 dp_intf1: dp-intf@1c113000 {
3527 ethdr0: hdr-engine@1c114000 {
3575 edp_tx: edp-tx@1c500000 {
3586 dp_tx: dp-tx@1c600000 {