Lines Matching full:vdosys1
1189 <&vdosys1 CLK_VDO1_SMI_LARB2>,
1190 <&vdosys1 CLK_VDO1_SMI_LARB3>,
1191 <&vdosys1 CLK_VDO1_GALS>;
2675 vdosys1: syscon@1c100000 { label
2676 compatible = "mediatek,mt8188-vdosys1", "syscon";
2687 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
2697 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
2698 <&vdosys1 CLK_VDO1_SMI_LARB2>;
2708 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2709 <&vdosys1 CLK_VDO1_SMI_LARB3>;
2719 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
2730 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
2741 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
2752 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
2763 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
2774 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
2785 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
2796 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
2807 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
2808 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
2812 resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>;
2820 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
2821 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
2825 resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>;
2833 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
2834 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
2838 resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>;
2846 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
2847 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
2851 resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>;
2859 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
2860 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
2864 resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>;
2872 clocks = <&vdosys1 CLK_VDO1_DPINTF>,
2873 <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>,
2893 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
2894 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
2895 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
2896 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
2897 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
2898 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
2899 <&vdosys1 CLK_VDO1_26M_SLOW>,
2900 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
2901 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
2902 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
2903 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
2904 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
2914 resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>,
2915 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>,
2916 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>,
2917 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>,
2918 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>;
2932 clocks = <&vdosys1 CLK_VDO1_PADDING0>;
2940 clocks = <&vdosys1 CLK_VDO1_PADDING1>;
2948 clocks = <&vdosys1 CLK_VDO1_PADDING2>;
2956 clocks = <&vdosys1 CLK_VDO1_PADDING3>;
2964 clocks = <&vdosys1 CLK_VDO1_PADDING4>;
2972 clocks = <&vdosys1 CLK_VDO1_PADDING5>;
2980 clocks = <&vdosys1 CLK_VDO1_PADDING6>;
2988 clocks = <&vdosys1 CLK_VDO1_PADDING7>;