Lines Matching full:topckgen
956 topckgen: syscon@10000000 { label
957 compatible = "mediatek,mt8188-topckgen", "syscon";
1014 <&topckgen CLK_TOP_MFG_CORE_TMP>;
1040 clocks = <&topckgen CLK_TOP_VPP>,
1041 <&topckgen CLK_TOP_CAM>,
1042 <&topckgen CLK_TOP_CCU>,
1043 <&topckgen CLK_TOP_IMG>,
1044 <&topckgen CLK_TOP_VENC>,
1045 <&topckgen CLK_TOP_VDEC>,
1046 <&topckgen CLK_TOP_WPE_VPP>,
1047 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>,
1048 <&topckgen CLK_TOP_CFGREG_F26M_VPP0>,
1084 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>,
1085 <&topckgen CLK_TOP_CFGREG_F26M_VDO0>,
1103 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
1104 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>,
1136 clocks = <&topckgen CLK_TOP_CAM>,
1137 <&topckgen CLK_TOP_CCU>,
1138 <&topckgen CLK_TOP_CCU_AHB>,
1139 <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>;
1187 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>,
1188 <&topckgen CLK_TOP_CFGREG_F26M_VDO1>,
1201 clocks = <&topckgen CLK_TOP_HDMI_APB>,
1202 <&topckgen CLK_TOP_HDCP_24M>;
1254 clocks = <&topckgen CLK_TOP_SENINF>,
1255 <&topckgen CLK_TOP_SENINF1>;
1267 clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1268 <&topckgen CLK_TOP_ADSP>;
1284 clocks = <&topckgen CLK_TOP_ASM_H>;
1292 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
1293 <&topckgen CLK_TOP_AUD_INTBUS>,
1352 assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>;
1353 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1356 <&topckgen CLK_TOP_SPMI_M_MST>;
1394 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
1395 assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>;
1399 <&topckgen CLK_TOP_APLL12_CK_DIV0>,
1400 <&topckgen CLK_TOP_APLL12_CK_DIV1>,
1401 <&topckgen CLK_TOP_APLL12_CK_DIV2>,
1402 <&topckgen CLK_TOP_APLL12_CK_DIV3>,
1403 <&topckgen CLK_TOP_APLL12_CK_DIV9>,
1404 <&topckgen CLK_TOP_A1SYS_HP>,
1405 <&topckgen CLK_TOP_AUD_INTBUS>,
1406 <&topckgen CLK_TOP_AUDIO_H>,
1407 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1408 <&topckgen CLK_TOP_DPTX>,
1409 <&topckgen CLK_TOP_I2SO1>,
1410 <&topckgen CLK_TOP_I2SO2>,
1411 <&topckgen CLK_TOP_I2SI1>,
1412 <&topckgen CLK_TOP_I2SI2>,
1414 <&topckgen CLK_TOP_APLL1_D4>,
1415 <&topckgen CLK_TOP_APLL2_D4>,
1416 <&topckgen CLK_TOP_APLL12_CK_DIV4>,
1417 <&topckgen CLK_TOP_A2SYS>,
1418 <&topckgen CLK_TOP_AUD_IEC>;
1447 mediatek,topckgen = <&topckgen>;
1458 assigned-clocks = <&topckgen CLK_TOP_ADSP>;
1459 clocks = <&topckgen CLK_TOP_ADSP>,
1460 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
1545 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1546 <&topckgen CLK_TOP_SPI>,
1566 clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1577 clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1591 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1592 <&topckgen CLK_TOP_SPI>,
1604 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1605 <&topckgen CLK_TOP_SPI>,
1617 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1618 <&topckgen CLK_TOP_SPI>,
1630 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1631 <&topckgen CLK_TOP_SPI>,
1643 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1644 <&topckgen CLK_TOP_SPI>,
1658 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1659 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1660 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1664 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1665 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1666 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1667 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1668 <&topckgen CLK_TOP_ETHPLL_D8>,
1669 <&topckgen CLK_TOP_ETHPLL_D10>;
1755 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1756 <&topckgen CLK_TOP_SSUSB_XHCI>;
1757 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1758 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1760 <&topckgen CLK_TOP_SSUSB_TOP_REF>,
1773 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1786 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1790 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1791 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1861 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
1862 <&topckgen CLK_TOP_USB_TOP_3P>;
1863 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1864 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1866 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>,
1879 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
1880 <&topckgen CLK_TOP_USB_TOP_2P>;
1881 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1882 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1884 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>,
1943 clocks = <&topckgen CLK_TOP_SPINOR>,
1947 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1964 clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>;
2033 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>,
2049 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
2073 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>,
2346 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2347 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
2348 clocks = <&topckgen CLK_TOP_VDEC>,
2351 <&topckgen CLK_TOP_UNIVPLL_D6>;
2369 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2370 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
2371 clocks = <&topckgen CLK_TOP_VDEC>,
2374 <&topckgen CLK_TOP_UNIVPLL_D6>;
2448 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2449 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2905 <&topckgen CLK_TOP_ETHDR>;