Lines Matching +full:0 +full:x2e00
17 #size-cells = <0>;
19 cpu0: cpu@0 {
21 reg = <0x0>;
32 reg = <0x1>;
43 reg = <0x2>;
54 reg = <0x3>;
63 cluster0_opp: opp-table-0 {
89 #clock-cells = <0>;
111 reg = <0 0x43000000 0 0x50000>;
124 reg = <0 0x0c000000 0 0x40000>, /* GICD */
125 <0 0x0c080000 0 0x200000>, /* GICR */
126 <0 0x0c400000 0 0x2000>, /* GICC */
127 <0 0x0c410000 0 0x1000>, /* GICH */
128 <0 0x0c420000 0 0x2000>; /* GICV */
137 reg = <0 0x10001000 0 0x1000>;
144 reg = <0 0x1001b000 0 0x1000>;
150 reg = <0 0x1001c000 0 0x1000>;
157 reg = <0 0x1001e000 0 0x1000>;
163 reg = <0 0x1001f000 0 0x1000>,
164 <0 0x11c10000 0 0x1000>,
165 <0 0x11d00000 0 0x1000>,
166 <0 0x11d20000 0 0x1000>,
167 <0 0x11e00000 0 0x1000>,
168 <0 0x11f00000 0 0x1000>,
169 <0 0x1000b000 0 0x1000>;
175 gpio-ranges = <&pio 0 0 84>;
216 reg = <0 0x10048000 0 0x1000>;
235 reg = <0 0x100e0000 0 0x1000>;
241 reg = <0 0x11000000 0 0x100>;
252 reg = <0 0x11000100 0 0x100>;
263 reg = <0 0x11000200 0 0x100>;
274 reg = <0 0x11003000 0 0x1000>,
275 <0 0x10217080 0 0x80>;
282 #size-cells = <0>;
288 reg = <0 0x11004000 0 0x1000>,
289 <0 0x10217100 0 0x80>;
296 #size-cells = <0>;
302 reg = <0 0x11005000 0 0x1000>,
303 <0 0x10217180 0 0x80>;
310 #size-cells = <0>;
317 reg = <0 0x1100a000 0 0x1000>;
327 reg = <0 0x11190000 0 0x2e00>,
328 <0 0x11193e00 0 0x0100>;
342 reg = <0 0x11200000 0 0x2e00>,
343 <0 0x11203e00 0 0x0100>;
359 reg = <0 0x11230000 0 0x1000>,
360 <0 0x11D60000 0 0x1000>;
372 #size-cells = <0>;
382 reg = <0 0x11280000 0 0x2000>;
386 bus-range = <0x00 0xff>;
387 ranges = <0x81000000 0x00 0x20000000 0x00
388 0x20000000 0x00 0x00200000>,
389 <0x82000000 0x00 0x20200000 0x00
390 0x20200000 0x00 0x07e00000>;
398 pinctrl-0 = <&pcie2_pins>;
402 interrupt-map-mask = <0 0 0 0x7>;
403 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
404 <0 0 0 2 &pcie_intc2 1>,
405 <0 0 0 3 &pcie_intc2 2>,
406 <0 0 0 4 &pcie_intc2 3>;
408 #address-cells = <0>;
420 reg = <0 0x11290000 0 0x2000>;
424 bus-range = <0x00 0xff>;
425 ranges = <0x81000000 0x00 0x28000000 0x00
426 0x28000000 0x00 0x00200000>,
427 <0x82000000 0x00 0x28200000 0x00
428 0x28200000 0x00 0x07e00000>;
436 pinctrl-0 = <&pcie3_pins>;
440 interrupt-map-mask = <0 0 0 0x7>;
441 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
442 <0 0 0 2 &pcie_intc3 1>,
443 <0 0 0 3 &pcie_intc3 2>,
444 <0 0 0 4 &pcie_intc3 3>;
446 #address-cells = <0>;
458 reg = <0 0x11300000 0 0x2000>;
460 linux,pci-domain = <0>;
462 bus-range = <0x00 0xff>;
463 ranges = <0x81000000 0x00 0x30000000 0x00
464 0x30000000 0x00 0x00200000>,
465 <0x82000000 0x00 0x30200000 0x00
466 0x30200000 0x00 0x07e00000>;
474 pinctrl-0 = <&pcie0_pins>;
478 interrupt-map-mask = <0 0 0 0x7>;
479 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
480 <0 0 0 2 &pcie_intc0 1>,
481 <0 0 0 3 &pcie_intc0 2>,
482 <0 0 0 4 &pcie_intc0 3>;
484 #address-cells = <0>;
496 reg = <0 0x11310000 0 0x2000>;
500 bus-range = <0x00 0xff>;
501 ranges = <0x81000000 0x00 0x38000000 0x00
502 0x38000000 0x00 0x00200000>,
503 <0x82000000 0x00 0x38200000 0x00
504 0x38200000 0x00 0x07e00000>;
512 pinctrl-0 = <&pcie1_pins>;
516 interrupt-map-mask = <0 0 0 0x7>;
517 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
518 <0 0 0 2 &pcie_intc1 1>,
519 <0 0 0 3 &pcie_intc1 2>,
520 <0 0 0 4 &pcie_intc1 3>;
522 #address-cells = <0>;
537 reg = <0 0x11c50000 0 0x700>;
544 reg = <0 0x11c50700 0 0x900>;
553 reg = <0 0x11f40000 0 0x1000>;
560 reg = <0 0x11f50000 0 0x1000>;
565 reg = <0x918 0x28>;
571 reg = <0 0x15000000 0 0x1000>;
578 reg = <0 0x15031000 0 0x1000>;
588 thermal-sensors = <&lvts 0>;