Lines Matching +full:timer +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
24 compatible = "shared-dma-pool";
27 no-map;
32 #address-cells = <1>;
33 #size-cells = <0>;
36 compatible = "arm,cortex-a55";
39 enable-method = "psci";
43 compatible = "arm,cortex-a55";
46 enable-method = "psci";
50 compatible = "arm,cortex-a76";
53 enable-method = "psci";
57 compatible = "arm,cortex-a76";
60 enable-method = "psci";
65 compatible = "arm,psci-0.2";
69 intc: interrupt-controller@1d000000 {
70 compatible = "arm,gic-v3";
74 #interrupt-cells = <3>;
75 #address-cells = <2>;
76 #size-cells = <2>;
77 interrupt-controller;
78 #redistributor-regions = <1>;
79 redistributor-stride = <0x0 0x20000>;
81 its: msi-controller@1d040000 {
82 compatible = "arm,gic-v3-its";
84 msi-controller;
85 #msi-cells = <1>;
91 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
92 #clock-cells = <0>;
93 compatible = "fixed-clock";
94 clock-frequency = <0>;
97 cb_intosc_ls_clk: cb-intosc-ls-clk {
98 #clock-cells = <0>;
99 compatible = "fixed-clock";
100 clock-frequency = <0>;
103 f2s_free_clk: f2s-free-clk {
104 #clock-cells = <0>;
105 compatible = "fixed-clock";
106 clock-frequency = <0>;
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 clock-frequency = <0>;
115 qspi_clk: qspi-clk {
116 #clock-cells = <0>;
117 compatible = "fixed-clock";
118 clock-frequency = <200000000>;
122 timer {
123 compatible = "arm,armv8-timer";
124 interrupt-parent = <&intc>;
132 #phy-cells = <0>;
133 compatible = "usb-nop-xceiv";
137 compatible = "simple-bus";
139 #address-cells = <1>;
140 #size-cells = <1>;
142 interrupt-parent = <&intc>;
144 clkmgr: clock-controller@10d10000 {
145 compatible = "intel,agilex5-clkmgr";
147 #clock-cells = <1>;
151 compatible = "snps,designware-i2c";
153 #address-cells = <1>;
154 #size-cells = <0>;
162 compatible = "snps,designware-i2c";
164 #address-cells = <1>;
165 #size-cells = <0>;
173 compatible = "snps,designware-i2c";
175 #address-cells = <1>;
176 #size-cells = <0>;
184 compatible = "snps,designware-i2c";
186 #address-cells = <1>;
187 #size-cells = <0>;
195 compatible = "snps,designware-i2c";
197 #address-cells = <1>;
198 #size-cells = <0>;
206 compatible = "snps,dw-i3c-master-1.00a";
208 #address-cells = <3>;
209 #size-cells = <0>;
216 compatible = "snps,dw-i3c-master-1.00a";
218 #address-cells = <3>;
219 #size-cells = <0>;
226 compatible = "snps,dw-apb-gpio";
228 #address-cells = <1>;
229 #size-cells = <0>;
233 porta: gpio-controller@0 {
234 compatible = "snps,dw-apb-gpio-port";
236 gpio-controller;
237 #gpio-cells = <2>;
238 snps,nr-gpios = <24>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
246 compatible = "snps,dw-apb-gpio";
248 #address-cells = <1>;
249 #size-cells = <0>;
253 portb: gpio-controller@0 {
254 compatible = "snps,dw-apb-gpio-port";
256 gpio-controller;
257 #gpio-cells = <2>;
258 snps,nr-gpios = <24>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
265 nand: nand-controller@10b80000 {
266 compatible = "cdns,hp-nfc";
269 reg-names = "reg", "sdma";
270 #address-cells = <1>;
271 #size-cells = <0>;
274 cdns,board-delay-ps = <4830>;
279 compatible = "mmio-sram";
282 #address-cells = <1>;
283 #size-cells = <1>;
286 dmac0: dma-controller@10db0000 {
287 compatible = "snps,axi-dma-1.01a";
291 clock-names = "core-clk", "cfgr-clk";
292 interrupt-parent = <&intc>;
294 #dma-cells = <1>;
295 dma-channels = <4>;
296 snps,dma-masters = <1>;
297 snps,data-width = <2>;
298 snps,block-size = <32767 32767 32767 32767>;
300 snps,axi-max-burst-len = <8>;
303 dmac1: dma-controller@10dc0000 {
304 compatible = "snps,axi-dma-1.01a";
308 clock-names = "core-clk", "cfgr-clk";
309 interrupt-parent = <&intc>;
311 #dma-cells = <1>;
312 dma-channels = <4>;
313 snps,dma-masters = <1>;
314 snps,data-width = <2>;
315 snps,block-size = <32767 32767 32767 32767>;
317 snps,axi-max-burst-len = <8>;
321 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
323 #reset-cells = <1>;
327 compatible = "snps,dw-apb-ssi";
329 #address-cells = <1>;
330 #size-cells = <0>;
333 reset-names = "spi";
334 reg-io-width = <4>;
335 num-cs = <4>;
338 dma-names = "tx", "rx";
344 compatible = "snps,dw-apb-ssi";
346 #address-cells = <1>;
347 #size-cells = <0>;
350 reset-names = "spi";
351 reg-io-width = <4>;
352 num-cs = <4>;
355 dma-names = "tx", "rx";
360 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
365 compatible = "snps,dw-apb-timer";
369 clock-names = "timer";
373 compatible = "snps,dw-apb-timer";
377 clock-names = "timer";
381 compatible = "snps,dw-apb-timer";
385 clock-names = "timer";
389 compatible = "snps,dw-apb-timer";
393 clock-names = "timer";
397 compatible = "snps,dw-apb-uart";
400 reg-shift = <2>;
401 reg-io-width = <4>;
408 compatible = "snps,dw-apb-uart";
411 reg-shift = <2>;
412 reg-io-width = <4>;
423 phy-names = "usb2-phy";
425 reset-names = "dwc2", "dwc2-ecc";
427 clock-names = "otg";
432 compatible = "snps,dw-wdt";
441 compatible = "snps,dw-wdt";
450 compatible = "snps,dw-wdt";
459 compatible = "snps,dw-wdt";
468 compatible = "snps,dw-wdt";
477 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
480 #address-cells = <1>;
481 #size-cells = <0>;
483 cdns,fifo-depth = <128>;
484 cdns,fifo-width = <4>;
485 cdns,trigger-address = <0x00000000>;