Lines Matching +full:enable +full:- +full:method
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <[email protected]>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
62 compatible = "arm,cortex-a53";
64 enable-method = "psci";
70 compatible = "arm,cortex-a53";
72 enable-method = "psci";
78 compatible = "arm,cortex-a53";
80 enable-method = "psci";
86 compatible = "arm,cortex-a53";
88 enable-method = "psci";
94 compatible = "arm,cortex-a53";
96 enable-method = "psci";
102 compatible = "arm,cortex-a53";
104 enable-method = "psci";
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
118 compatible = "arm,cortex-a53";
120 enable-method = "psci";
127 compatible = "arm,scmi-smc";
129 arm,smc-id = <0xc20000fe>;
130 #address-cells = <1>;
131 #size-cells = <0>;
135 #clock-cells = <1>;
140 #clock-cells = <1>;
145 compatible = "arm,psci-1.0";
146 method = "smc";
152 compatible = "arm,cortex-a53-pmu";
156 reserved-memory {
157 #address-cells = <2>;
158 #size-cells = <2>;
162 compatible = "arm,scmi-shmem";
164 no-map;
169 compatible = "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
175 compatible = "nxp,s32g2-siul2-pinctrl";
176 /* MSCR0-MSCR101 registers on siul2_0 */
178 /* MSCR112-MSCR122 registers on siul2_1 */
180 /* MSCR144-MSCR190 registers on siul2_1 */
182 /* IMCR0-IMCR83 registers on siul2_0 */
184 /* IMCR119-IMCR397 registers on siul2_1 */
186 /* IMCR430-IMCR495 registers on siul2_1 */
189 jtag_pins: jtag-pins {
190 jtag-grp0 {
192 input-enable;
193 bias-pull-up;
194 slew-rate = <166>;
197 jtag-grp1 {
199 slew-rate = <166>;
202 jtag-grp2 {
204 input-enable;
205 bias-pull-down;
206 slew-rate = <166>;
209 jtag-grp3 {
215 jtag-grp4 {
217 input-enable;
218 bias-pull-up;
219 slew-rate = <166>;
223 pinctrl_usdhc0: usdhc0grp-pins {
224 usdhc0-grp0 {
227 output-enable;
228 bias-pull-down;
229 slew-rate = <150>;
232 usdhc0-grp1 {
242 output-enable;
243 input-enable;
244 bias-pull-up;
245 slew-rate = <150>;
248 usdhc0-grp2 {
250 output-enable;
251 slew-rate = <150>;
254 usdhc0-grp3 {
256 input-enable;
257 slew-rate = <150>;
260 usdhc0-grp4 {
274 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
275 usdhc0-100mhz-grp0 {
278 output-enable;
279 bias-pull-down;
280 slew-rate = <150>;
283 usdhc0-100mhz-grp1 {
293 output-enable;
294 input-enable;
295 bias-pull-up;
296 slew-rate = <150>;
299 usdhc0-100mhz-grp2 {
301 output-enable;
302 slew-rate = <150>;
305 usdhc0-100mhz-grp3 {
307 input-enable;
308 slew-rate = <150>;
311 usdhc0-100mhz-grp4 {
325 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
326 usdhc0-200mhz-grp0 {
329 output-enable;
330 bias-pull-down;
331 slew-rate = <208>;
334 usdhc0-200mhz-grp1 {
344 output-enable;
345 input-enable;
346 bias-pull-up;
347 slew-rate = <208>;
350 usdhc0-200mhz-grp2 {
352 output-enable;
353 slew-rate = <208>;
356 usdhc0-200mhz-grp3 {
358 input-enable;
359 slew-rate = <208>;
362 usdhc0-200mhz-grp4 {
378 compatible = "nxp,s32g3-linflexuart",
379 "fsl,s32v234-linflexuart";
386 compatible = "nxp,s32g3-linflexuart",
387 "fsl,s32v234-linflexuart";
394 compatible = "nxp,s32g3-linflexuart",
395 "fsl,s32v234-linflexuart";
402 compatible = "nxp,s32g3-usdhc",
403 "nxp,s32g2-usdhc";
409 clock-names = "ipg", "ahb", "per";
413 gic: interrupt-controller@50800000 {
414 compatible = "arm,gic-v3";
415 #interrupt-cells = <3>;
416 interrupt-controller;
427 compatible = "arm,armv8-timer";
428 interrupt-parent = <&gic>;
429 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
432 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
433 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
434 arm,no-tick-in-suspend;