Lines Matching +full:output +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright 2017-2021, 2024 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "arm,scmi-shmem";
25 no-map;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
38 next-level-cache = <&cluster0_l2>;
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 next-level-cache = <&cluster0_l2>;
51 compatible = "arm,cortex-a53";
53 enable-method = "psci";
54 next-level-cache = <&cluster1_l2>;
59 compatible = "arm,cortex-a53";
61 enable-method = "psci";
62 next-level-cache = <&cluster1_l2>;
65 cluster0_l2: l2-cache0 {
67 cache-level = <2>;
68 cache-unified;
71 cluster1_l2: l2-cache1 {
73 cache-level = <2>;
74 cache-unified;
79 compatible = "arm,cortex-a53-pmu";
84 compatible = "arm,armv8-timer";
93 compatible = "arm,scmi-smc";
94 arm,smc-id = <0xc20000fe>;
95 #address-cells = <1>;
96 #size-cells = <0>;
101 #clock-cells = <1>;
106 compatible = "arm,psci-1.0";
112 compatible = "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
118 compatible = "nxp,s32g2-siul2-pinctrl";
119 /* MSCR0-MSCR101 registers on siul2_0 */
121 /* MSCR112-MSCR122 registers on siul2_1 */
123 /* MSCR144-MSCR190 registers on siul2_1 */
125 /* IMCR0-IMCR83 registers on siul2_0 */
127 /* IMCR119-IMCR397 registers on siul2_1 */
129 /* IMCR430-IMCR495 registers on siul2_1 */
132 jtag_pins: jtag-pins {
133 jtag-grp0 {
135 input-enable;
136 bias-pull-up;
137 slew-rate = <166>;
140 jtag-grp1 {
142 slew-rate = <166>;
145 jtag-grp2 {
147 input-enable;
148 bias-pull-down;
149 slew-rate = <166>;
152 jtag-grp3 {
158 jtag-grp4 {
160 input-enable;
161 bias-pull-up;
162 slew-rate = <166>;
166 pinctrl_usdhc0: usdhc0grp-pins {
167 usdhc0-grp0 {
170 output-enable;
171 bias-pull-down;
172 slew-rate = <150>;
175 usdhc0-grp1 {
185 output-enable;
186 input-enable;
187 bias-pull-up;
188 slew-rate = <150>;
191 usdhc0-grp2 {
193 output-enable;
194 slew-rate = <150>;
197 usdhc0-grp3 {
199 input-enable;
200 slew-rate = <150>;
203 usdhc0-grp4 {
217 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
218 usdhc0-100mhz-grp0 {
221 output-enable;
222 bias-pull-down;
223 slew-rate = <150>;
226 usdhc0-100mhz-grp1 {
236 output-enable;
237 input-enable;
238 bias-pull-up;
239 slew-rate = <150>;
242 usdhc0-100mhz-grp2 {
244 output-enable;
245 slew-rate = <150>;
248 usdhc0-100mhz-grp3 {
250 input-enable;
251 slew-rate = <150>;
254 usdhc0-100mhz-grp4 {
268 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
269 usdhc0-200mhz-grp0 {
272 output-enable;
273 bias-pull-down;
274 slew-rate = <208>;
277 usdhc0-200mhz-grp1 {
287 output-enable;
288 input-enable;
289 bias-pull-up;
290 slew-rate = <208>;
293 usdhc0-200mhz-grp2 {
295 output-enable;
296 slew-rate = <208>;
299 usdhc0-200mhz-grp3 {
301 input-enable;
302 slew-rate = <208>;
305 usdhc0-200mhz-grp4 {
321 compatible = "nxp,s32g2-linflexuart",
322 "fsl,s32v234-linflexuart";
329 compatible = "nxp,s32g2-linflexuart",
330 "fsl,s32v234-linflexuart";
337 compatible = "nxp,s32g2-linflexuart",
338 "fsl,s32v234-linflexuart";
345 compatible = "nxp,s32g2-usdhc";
349 clock-names = "ipg", "ahb", "per";
350 bus-width = <8>;
354 gic: interrupt-controller@50800000 {
355 compatible = "arm,gic-v3";
362 interrupt-controller;
363 #interrupt-cells = <3>;