Lines Matching +full:0 +full:x48060000
23 #size-cells = <0>;
30 arm,psci-suspend-param = <0x0010033>;
39 A55_0: cpu@0 {
42 reg = <0x0>;
60 reg = <0x100>;
78 reg = <0x200>;
96 reg = <0x300>;
114 reg = <0x400>;
132 reg = <0x500>;
247 #clock-cells = <0>;
248 clock-frequency = <0>;
254 #clock-cells = <0>;
261 #clock-cells = <0>;
262 clock-frequency= <0>;
268 #clock-cells = <0>;
269 clock-frequency= <0>;
275 #clock-cells = <0>;
276 clock-frequency= <0>;
282 #clock-cells = <0>;
283 clock-frequency= <0>;
289 #clock-cells = <0>;
290 clock-frequency= <0>;
296 #clock-cells = <0>;
303 reg = <0x0 0x204c0000 0x0 0x18000>;
304 ranges = <0x0 0x0 0x204c0000 0x18000>;
312 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>;
315 #size-cells = <0>;
319 reg = <0x11>;
324 reg = <0x12>;
328 reg = <0x13>;
333 reg = <0x14>;
338 reg = <0x15>;
343 reg = <0x19>;
347 reg = <0x81>;
351 reg = <0x84>;
398 thermal-sensors = <&scmi_sensor 0>;
446 reg = <0 0x48000000 0 0x10000>,
447 <0 0x48060000 0 0xc0000>;
459 reg = <0 0x48040000 0 0x20000>;
474 reg = <0x0 0x42000000 0x0 0x800000>;
475 ranges = <0x42000000 0x0 0x42000000 0x8000000>,
476 <0x28000000 0x0 0x28000000 0x10000000>;
482 reg = <0x42000000 0x210000>;
555 reg = <0x42210000 0x210000>;
628 reg = <0x42430000 0x10000>;
637 reg = <0x42490000 0x10000>;
646 reg = <0x424e0000 0x1000>;
654 reg = <0x424f0000 0x1000>;
662 reg = <0x42500000 0x1000>;
670 reg = <0x42510000 0x1000>;
678 reg = <0x42530000 0x10000>;
684 #size-cells = <0>;
685 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>;
692 reg = <0x42540000 0x10000>;
698 #size-cells = <0>;
699 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>;
706 #size-cells = <0>;
708 reg = <0x42550000 0x10000>;
713 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>;
720 #size-cells = <0>;
722 reg = <0x42560000 0x10000>;
727 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>;
735 reg = <0x42570000 0x1000>;
739 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
747 reg = <0x42580000 0x1000>;
751 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
759 reg = <0x42590000 0x1000>;
763 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
771 reg = <0x425a0000 0x1000>;
775 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>;
782 reg = <0x425b0000 0x10000>;
790 fsl,clk-source = /bits/ 8 <0>;
796 reg = <0x42600000 0x10000>;
804 fsl,clk-source = /bits/ 8 <0>;
810 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>;
813 #size-cells = <0>;
826 reg = <0x42650000 0x10000>;
832 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>;
839 reg = <0x42660000 0x10000>;
845 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>;
852 reg = <0x42670000 0x10000>;
858 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>;
865 reg = <0x42680000 0x800>, <0x42680800 0x400>,
866 <0x42680c00 0x080>, <0x42680e00 0x080>;
868 interrupts = /* XCVR IRQ 0 */
877 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>;
885 reg = <0x42690000 0x1000>;
889 dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>;
897 reg = <0x426a0000 0x1000>;
901 dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>;
908 reg = <0x426b0000 0x10000>;
914 #size-cells = <0>;
915 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>;
922 reg = <0x426c0000 0x10000>;
928 #size-cells = <0>;
929 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>;
936 reg = <0x426d0000 0x10000>;
942 #size-cells = <0>;
943 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>;
950 reg = <0x426e0000 0x10000>;
956 #size-cells = <0>;
957 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>;
964 #size-cells = <0>;
966 reg = <0x426f0000 0x10000>;
971 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>;
978 #size-cells = <0>;
980 reg = <0x42700000 0x10000>;
985 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>;
992 #size-cells = <0>;
994 reg = <0x42710000 0x10000>;
999 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>;
1006 #size-cells = <0>;
1008 reg = <0x42720000 0x10000>;
1013 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>;
1020 reg = <0x42730000 0x10000>;
1029 reg = <0x427c0000 0x10000>;
1037 fsl,clk-source = /bits/ 8 <0>;
1043 reg = <0x427d0000 0x10000>;
1051 fsl,clk-source = /bits/ 8 <0>;
1058 reg = <0 0x42800000 0 0x800000>;
1061 ranges = <0x42800000 0x0 0x42800000 0x800000>;
1065 reg = <0x42850000 0x10000>;
1082 reg = <0x42860000 0x10000>;
1099 reg = <0x428b0000 0x10000>;
1117 reg = <0x0 0x43810000 0x0 0x1000>;
1127 gpio-ranges = <&scmi_iomuxc 0 4 32>;
1132 reg = <0x0 0x43820000 0x0 0x1000>;
1142 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>,
1143 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>;
1148 reg = <0x0 0x43840000 0x0 0x1000>;
1158 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>;
1163 reg = <0x0 0x43850000 0x0 0x1000>;
1173 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>;
1178 reg = <0x0 0x44000000 0x0 0x800000>;
1179 ranges = <0x44000000 0x0 0x44000000 0x800000>;
1185 reg = <0x44000000 0x200000>;
1225 reg = <0x44220000 0x10000>;
1234 reg = <0x44310000 0x1000>;
1242 reg = <0x44320000 0x1000>;
1250 reg = <0x44340000 0x10000>;
1256 #size-cells = <0>;
1257 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ;
1264 reg = <0x44350000 0x10000>;
1270 #size-cells = <0>;
1271 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ;
1278 #size-cells = <0>;
1280 reg = <0x44360000 0x10000>;
1285 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ;
1292 #size-cells = <0>;
1294 reg = <0x44370000 0x10000>;
1299 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ;
1307 reg = <0x44380000 0x1000>;
1311 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>;
1319 reg = <0x44390000 0x1000>;
1323 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>;
1330 reg = <0x443a0000 0x10000>;
1338 fsl,clk-source = /bits/ 8 <0>;
1344 reg = <0x443b0000 0x10000>;
1350 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>;
1357 reg = <0x44520000 0x10000>;
1369 dmas = <&edma1 6 0 5>;
1376 reg = <0x44530000 0x10000>;
1387 reg = <0x445b0000 0x1000>;
1396 reg = <0x445b1000 0x400>;
1397 ranges = <0x0 0x445b1000 0x400>;
1401 scmi_buf0: scmi-sram-section@0 {
1403 reg = <0x0 0x80>;
1408 reg = <0x80 0x80>;
1416 reg = <0x445d0000 0x10000>;
1425 reg = <0x445f0000 0x10000>;
1434 reg = <0x44630000 0x10000>;
1444 reg = <0x0 0x47320000 0x0 0x10000>;
1451 reg = <0x0 0x47350000 0x0 0x10000>;
1459 reg = <0x0 0x47400000 0x0 0x1000>;
1469 gpio-ranges = <&scmi_iomuxc 0 112 16>;
1475 reg = <0x0 0x47520000 0x0 0x10000>;
1483 reg = <0x0 0x47530000 0x0 0x10000>;
1491 reg = <0x0 0x47540000 0x0 0x10000>;
1499 reg = <0x0 0x47550000 0x0 0x10000>;
1506 reg = <0x0 0x47560000 0x0 0x10000>;
1514 reg = <0x0 0x47570000 0x0 0x10000>;
1522 reg = <0x0 0x49000000 0x0 0x800000>;
1523 ranges = <0x49000000 0x0 0x49000000 0x800000>;
1529 reg = <0x490d0000 0x100000>;
1542 reg = <0 0x4c300000 0 0x10000>,
1543 <0 0x60100000 0 0xfe00000>,
1544 <0 0x4c360000 0 0x10000>,
1545 <0 0x4c340000 0 0x2000>;
1547 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
1548 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
1552 linux,pci-domain = <0>;
1553 bus-range = <0x00 0xff>;
1559 interrupt-map-mask = <0 0 0 0x7>;
1560 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1561 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1562 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1563 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1573 assigned-clock-parents = <0>, <0>,
1582 reg = <0 0x4c300000 0 0x10000>,
1583 <0 0x4c360000 0 0x1000>,
1584 <0 0x4c320000 0 0x1000>,
1585 <0 0x4c340000 0 0x2000>,
1586 <0 0x4c370000 0 0x10000>,
1587 <0x9 0 1 0>;
1601 assigned-clock-parents = <0>, <0>,
1609 reg = <0 0x4c380000 0 0x10000>,
1610 <8 0x80100000 0 0xfe00000>,
1611 <0 0x4c3e0000 0 0x10000>,
1612 <0 0x4c3c0000 0 0x2000>;
1614 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
1615 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
1620 bus-range = <0x00 0xff>;
1626 interrupt-map-mask = <0 0 0 0x7>;
1627 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1628 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1629 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1630 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
1640 assigned-clock-parents = <0>, <0>,
1649 reg = <0 0x4c380000 0 0x10000>,
1650 <0 0x4c3e0000 0 0x1000>,
1651 <0 0x4c3a0000 0 0x1000>,
1652 <0 0x4c3c0000 0 0x2000>,
1653 <0 0x4c3f0000 0 0x10000>,
1654 <0xa 0 1 0>;
1668 assigned-clock-parents = <0>, <0>,
1676 reg = <0x0 0x4c810000 0x0 0x8>;
1688 reg = <0x0 0x4c880000 0x0 0x10000>;
1695 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>;
1702 reg = <0x0 0x4cde0000 0x0 0x10000>,
1703 <0x0 0x4cdf0000 0x0 0x10000>,
1704 <0x0 0x4c81000c 0x0 0x18>;
1721 reg = <0x0 0x4ca00000 0x0 0x100000>;
1725 bus-range = <0x0 0x0>;
1726 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF
1727 <0x10 &its 0x61 0x1>, //ENETC0 VF0
1728 <0x20 &its 0x62 0x1>, //ENETC0 VF1
1729 <0x40 &its 0x63 0x1>, //ENETC1 PF
1730 <0x80 &its 0x64 0x1>, //ENETC2 PF
1731 <0x90 &its 0x65 0x1>, //ENETC2 VF0
1732 <0xa0 &its 0x66 0x1>, //ENETC2 VF1
1733 <0xc0 &its 0x67 0x1>; //NETC Timer
1735 ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000
1737 0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000
1739 0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000
1741 0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>;
1743 enetc_port0: ethernet@0,0 {
1745 reg = <0x000000 0 0 0 0>;
1751 enetc_port1: ethernet@8,0 {
1753 reg = <0x004000 0 0 0 0>;
1759 enetc_port2: ethernet@10,0 {
1761 reg = <0x008000 0 0 0 0>;
1765 netc_timer: ethernet@18,0 {
1766 reg = <0x00c000 0 0 0 0>;
1773 reg = <0x0 0x4cb00000 0x0 0x100000>;
1777 bus-range = <0x1 0x1>;
1779 ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000
1781 0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>;
1783 netc_emdio: mdio@0,0 {
1785 reg = <0x010000 0 0 0 0>;
1787 #size-cells = <0>;
1795 reg = <0x0 0x4e090dc0 0x0 0x200>;