Lines Matching +full:imx8 +full:- +full:ddr +full:- +full:pmu
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
53 vpu-core0 = &vpu_core0;
54 vpu-core1 = &vpu_core1;
58 #address-cells = <2>;
59 #size-cells = <0>;
61 /* We have 1 clusters with 4 Cortex-A35 cores */
64 compatible = "arm,cortex-a35";
66 enable-method = "psci";
67 i-cache-size = <0x8000>;
68 i-cache-line-size = <64>;
69 i-cache-sets = <256>;
70 d-cache-size = <0x8000>;
71 d-cache-line-size = <64>;
72 d-cache-sets = <128>;
73 next-level-cache = <&A35_L2>;
75 operating-points-v2 = <&a35_opp_table>;
76 #cooling-cells = <2>;
81 compatible = "arm,cortex-a35";
83 enable-method = "psci";
84 i-cache-size = <0x8000>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <256>;
87 d-cache-size = <0x8000>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <128>;
90 next-level-cache = <&A35_L2>;
92 operating-points-v2 = <&a35_opp_table>;
93 #cooling-cells = <2>;
98 compatible = "arm,cortex-a35";
100 enable-method = "psci";
101 i-cache-size = <0x8000>;
102 i-cache-line-size = <64>;
103 i-cache-sets = <256>;
104 d-cache-size = <0x8000>;
105 d-cache-line-size = <64>;
106 d-cache-sets = <128>;
107 next-level-cache = <&A35_L2>;
109 operating-points-v2 = <&a35_opp_table>;
110 #cooling-cells = <2>;
115 compatible = "arm,cortex-a35";
117 enable-method = "psci";
118 i-cache-size = <0x8000>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <256>;
121 d-cache-size = <0x8000>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <128>;
124 next-level-cache = <&A35_L2>;
126 operating-points-v2 = <&a35_opp_table>;
127 #cooling-cells = <2>;
130 A35_L2: l2-cache0 {
132 cache-level = <2>;
133 cache-unified;
134 cache-size = <0x80000>;
135 cache-line-size = <64>;
136 cache-sets = <1024>;
140 a35_opp_table: opp-table {
141 compatible = "operating-points-v2";
142 opp-shared;
144 opp-900000000 {
145 opp-hz = /bits/ 64 <900000000>;
146 opp-microvolt = <1000000>;
147 clock-latency-ns = <150000>;
150 opp-1200000000 {
151 opp-hz = /bits/ 64 <1200000000>;
152 opp-microvolt = <1100000>;
153 clock-latency-ns = <150000>;
154 opp-suspend;
158 gic: interrupt-controller@51a00000 {
159 compatible = "arm,gic-v3";
162 #interrupt-cells = <3>;
163 interrupt-controller;
167 reserved-memory {
168 #address-cells = <2>;
169 #size-cells = <2>;
172 decoder_boot: decoder-boot@84000000 {
174 no-map;
177 encoder_boot: encoder-boot@86000000 {
179 no-map;
182 decoder_rpc: decoder-rpc@92000000 {
184 no-map;
189 no-map;
193 encoder_rpc: encoder-rpc@94400000 {
195 no-map;
199 pmu {
200 compatible = "arm,cortex-a35-pmu";
205 compatible = "arm,psci-1.0";
209 system-controller {
210 compatible = "fsl,imx-scu";
211 mbox-names = "tx0",
218 pd: power-controller {
219 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
220 #power-domain-cells = <1>;
223 clk: clock-controller {
224 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
225 #clock-cells = <2>;
229 compatible = "fsl,imx8qxp-iomuxc";
233 compatible = "fsl,imx8qxp-scu-ocotp";
234 #address-cells = <1>;
235 #size-cells = <1>;
239 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
245 compatible = "fsl,imx8qxp-sc-rtc";
249 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
250 timeout-sec = <60>;
253 tsens: thermal-sensor {
254 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
255 #thermal-sensor-cells = <1>;
260 compatible = "arm,armv8-timer";
262 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
267 clk_dummy: clock-dummy {
268 compatible = "fixed-clock";
269 #clock-cells = <0>;
270 clock-frequency = <0>;
271 clock-output-names = "clk_dummy";
274 xtal32k: clock-xtal32k {
275 compatible = "fixed-clock";
276 #clock-cells = <0>;
277 clock-frequency = <32768>;
278 clock-output-names = "xtal_32KHz";
281 xtal24m: clock-xtal24m {
282 compatible = "fixed-clock";
283 #clock-cells = <0>;
284 clock-frequency = <24000000>;
285 clock-output-names = "xtal_24MHz";
288 thermal_zones: thermal-zones {
289 cpu0-thermal {
290 polling-delay-passive = <250>;
291 polling-delay = <2000>;
292 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
308 cooling-maps {
311 cooling-device =
322 #include "imx8-ss-img.dtsi"
323 #include "imx8-ss-vpu.dtsi"
324 #include "imx8-ss-cm40.dtsi"
325 #include "imx8-ss-gpu0.dtsi"
326 #include "imx8-ss-adma.dtsi"
327 #include "imx8-ss-conn.dtsi"
328 #include "imx8-ss-ddr.dtsi"
329 #include "imx8-ss-lsio.dtsi"
330 #include "imx8-ss-hsio.dtsi"
333 #include "imx8qxp-ss-img.dtsi"
334 #include "imx8qxp-ss-vpu.dtsi"
335 #include "imx8qxp-ss-adma.dtsi"
336 #include "imx8qxp-ss-conn.dtsi"
337 #include "imx8qxp-ss-lsio.dtsi"
338 #include "imx8qxp-ss-hsio.dtsi"